diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/build/citest/etc/bbuild | 2 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/mdia-actions.patch | 637 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/patchlist.txt | 6 | ||||
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 9 | ||||
| -rwxr-xr-x | src/build/debug/simics-debug-framework.py | 2 | ||||
| -rw-r--r-- | src/usr/targeting/namedtarget.C | 6 | ||||
| -rw-r--r-- | src/usr/vpd/makefile | 2 | ||||
| -rwxr-xr-x | src/usr/vpd/test/mvpdtest.H | 24 |
8 files changed, 18 insertions, 670 deletions
diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild index d59cd1a4f..eb5578789 100644 --- a/src/build/citest/etc/bbuild +++ b/src/build/citest/etc/bbuild @@ -1 +1 @@ -/esw/fips801/Builds/b0228a_1309.801 +/esw/fips801/Builds/b0401a_1315.801 diff --git a/src/build/citest/etc/patches/mdia-actions.patch b/src/build/citest/etc/patches/mdia-actions.patch deleted file mode 100644 index 13b0c8f8f..000000000 --- a/src/build/citest/etc/patches/mdia-actions.patch +++ /dev/null @@ -1,637 +0,0 @@ ---- a/simu/data/cec-chip/centaur.chip -+++ b/simu/data/cec-chip/centaur.chip -@@ -11,6 +11,7 @@ - # uy01 859534 yadlapat 10/31/12 Correct p1 include file - # 858520 cphan 11/02/12 Add VPO_ACTIONS - # uy01 859534 yadlapat 11/02/12 Correct p1 include file -+# 871945 bradleyb 03/01/13 add prd/mdia logic regs - - - VERSION 1 # .chip file format ID -@@ -73,4 +74,17 @@ END - INTERNALREGS # List all scom registers - 0xFF00000F, 64 # Simics workaround - END -+ -+INTERNALREGS # prd / mdia testing -+ 0xFF010000, 64 # mba0 maint cmd counter -+ 0xFF010001, 64 # mba0 maint cmd error inject -+ 0xFF010002, 64 # mba0 maint cmd to inject -+ # ... -+ 0xFF018000, 64 # mba1 maint cmd counter -+ 0xFF018001, 64 # mba1 maint cmd error inject -+ 0xFF018002, 64 # mba1 maint cmd to inject -+ # ... -+ #0xFF01FFFF, 64 -+END -+ - DONE ---- a/simu/data/cec-chip/centaur.act -+++ b/simu/data/cec-chip/centaur.act -@@ -36,6 +36,7 @@ - # SW176884 bradleyb 12/15/12 re-enable command complete - # SW180168 vanlee 01/02/13 Centaur Mem PLL lock action - # SW182865 thi 01/18/13 Action file for Centaur SBE -+# SW189255 bradleyb 03/01/13 Add test logic to maint cmds - #******************************************************************** - # - -@@ -215,83 +216,115 @@ CAUSE_EFFECT { - } - - #****************************************** --# BEGIN - Maintenance Command Complete -+# BEGIN - Maintenance Commands - #****************************************** - --#Set command in progress - CAUSE_EFFECT { -- LABEL=[Maint Cmd Complete MBA0] -- WATCH=[REG(0x0301060B)] #MBMCC=0301060B -- CAUSE: TARGET=[REG(0x0301060B)] OP=[BIT,ON] BIT=[0] # Command Started -- EFFECT: TARGET=[REG(0x0301060B)] OP=[BIT,OFF] BIT=[0] # Clear Command Valid -- EFFECT: TARGET=[REG(0x0301060C)] OP=[BIT,ON] BIT=[0] # Set Command in progress -+ LABEL=[Abort Maint Cmd - MBA0] -+ WATCH=[REG(0x0301060B)] #mbmcc -+ CAUSE: TARGET=[REG(0x0301060B)] OP=[BIT,ON] BIT=[1] #stop_cmd -+ EFFECT: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] #cmd_nip -+ EFFECT: TARGET=[REG(0x0301060B)] OP=[BIT,OFF] BIT=[1] #reset stop_cmd - } - --# Set Cmd not in progress - CAUSE_EFFECT { -- LABEL=[Maint Cmd Stopped MBA0] -- WATCH=[REG(0x0301060B)] #MBMCC=0301060B -- CAUSE: TARGET=[REG(0x0301060B)] OP=[BIT,ON] BIT=[1] # Initiate stopping cmd -- EFFECT: TARGET=[REG(0x0301060B)] OP=[BIT,OFF] BIT=[1] # Clear request to stop cmd -- EFFECT: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] # Set cmd not in progress -+ LABEL=[Start Maint Cmd - MBA0] -+ WATCH=[REG(0x0301060B)] #mbmcc -+ CAUSE: TARGET=[REG(0x0301060B)] OP=[BIT,ON] BIT=[0] #start_cmd -+ EFFECT: TARGET=[REG(0x0301060B)] OP=[BIT,OFF] BIT=[0] #reset start_cmd -+ #testing counter -+ EFFECT: TARGET=[LOGIC(0xFF010000)] OP=[INCREMENT,MASK] INCVAL=[1] MASK=[LITERAL(64,FFFFFFFF 00000000)] -+ EFFECT: TARGET=[REG(0x0301060C)] OP=[BIT,ON] BIT=[0] #cmd_ip - } - --# Set maint cmd complete on reaching end address - CAUSE_EFFECT { -- LABEL=[Maint Cmd Complete on end addr MBA0] -- WATCH=[REG(0x0301060C)] #MBMSR=0301060C -- CAUSE: TARGET=[REG(0x0301060C)] OP=[BIT,ON] BIT=[0] # Command Complete -- CAUSE: TARGET=[REG(0x0301060F)] OP=[BIT,ON] BIT=[10] # Stop on end address -- EFFECT: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] # Clear when maint cmd complete -+ # Set logical Centaur register 0xff010001 (first word) to the nth -+ # command that should not reach mbmea. For example: -+ # p8Centaur03.membuf_chip.regwrite "LOGIC" 0xff010001 "00000002" 32 -+ LABEL=[Maint Cmd Error Inject - MBA0] -+ WATCH=[REG(0x0301060C)] #mbmsr -+ CAUSE: TARGET=[REG(0x0301060C)] OP=[BIT,ON] BIT=[0] #cmd_ip -+ #error inject -+ CAUSE: TARGET=[LOGIC(0xFF010000)] OP=[EQUALTO,BUF,ON] DATA=[LOGIC(0xFF010001)] -+ EFFECT: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] #cmd_nip - } - --# trigger special attention on maint cmd complete - CAUSE_EFFECT { -- LABEL=[Maint Cmd Complete Special Attention MBA0] -- WATCH=[REG(0x0301060C)] #MBMSR=0301060C -- CAUSE: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] # Maint Cmd Complete -- CAUSE: TARGET=[REG(0x0301060F)] OP=[BIT,ON] BIT=[11] # Enable Special attn -- EFFECT: TARGET=[REG(0x03010611)] OP=[BIT,ON] BIT=[0] # Set Special attn bit -+ # Set logical Centaur register 0xff010002 to the nth -+ # command that should never finish -+ LABEL=[Maint Cmd Done - MBA0] -+ WATCH=[REG(0x0301060C)] #mbmsr -+ CAUSE: TARGET=[REG(0x0301060C)] OP=[BIT,ON] BIT=[0] #cmd_ip -+ #no error inject -+ CAUSE: TARGET=[LOGIC(0xFF010000)] OP=[EQUALTO,BUF,OFF] DATA=[LOGIC(0xFF010001)] -+ CAUSE: TARGET=[LOGIC(0xFF010000)] OP=[EQUALTO,BUF,OFF] DATA=[LOGIC(0xFF010002)] -+ EFFECT: TARGET=[REG(0x0301060D)] OP=[EQUALTO,BUF] DATA=[REG(0x0301060E)] #mbmaca -+ EFFECT: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] #cmd_nip - } - --#Set command in progress - CAUSE_EFFECT { -- LABEL=[Maint Cmd Complete MBA1] -- WATCH=[REG(0x03010E0B)] #MBMCC=03010E0B -- CAUSE: TARGET=[REG(0x03010E0B)] OP=[BIT,ON] BIT=[0] # Command Started -- EFFECT: TARGET=[REG(0x03010E0B)] OP=[BIT,OFF] BIT=[0] # Clear Command Valid -- EFFECT: TARGET=[REG(0x03010E0C)] OP=[BIT,ON] BIT=[0] # Set Command in progress -+ LABEL=[Maint Cmd Complete Special Attention - MBA0] -+ WATCH=[REG(0x0301060C)] #mbmsr -+ CAUSE: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] #cmd_nip -+ CAUSE: TARGET=[REG(0x0301060F)] OP=[BIT,ON] BIT=[11] #enabled -+ EFFECT: TARGET=[REG(0x03010611)] OP=[BIT,ON] BIT=[0] #set special attn bit -+ EFFECT: TARGET=[REG(0x03010611)] OP=[BIT,ON] BIT=[8] #set wat_debug_attn - } - --# Set Cmd not in progress - CAUSE_EFFECT { -- LABEL=[Maint Cmd Stopped MBA1] -- WATCH=[REG(0x03010E0B)] #MBMCC=03010E0B -- CAUSE: TARGET=[REG(0x03010E0B)] OP=[BIT,ON] BIT=[1] # Initiate stopping cmd -- EFFECT: TARGET=[REG(0x03010E0B)] OP=[BIT,OFF] BIT=[1] # Clear request to stop cmd -- EFFECT: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] # Set cmd not in progress -+ LABEL=[Abort Maint Cmd - MBA1] -+ WATCH=[REG(0x03010E0B)] #mbmcc -+ CAUSE: TARGET=[REG(0x03010E0B)] OP=[BIT,ON] BIT=[1] #stop_cmd -+ EFFECT: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] #cmd_nip -+ EFFECT: TARGET=[REG(0x03010E0B)] OP=[BIT,OFF] BIT=[1] #reset stop_cmd - } - --# Set maint cmd complete on reaching end address - CAUSE_EFFECT { -- LABEL=[Maint Cmd Complete on end addr MBA1] -- WATCH=[REG(0x03010E0C)] #MBMSR=03010E0C -- CAUSE: TARGET=[REG(0x03010E0C)] OP=[BIT,ON] BIT=[0] # Command Complete -- CAUSE: TARGET=[REG(0x03010E0F)] OP=[BIT,ON] BIT=[10] # Stop on end address -- EFFECT: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] # Clear when maint cmd complete -+ LABEL=[Start Maint Cmd - MBA1] -+ WATCH=[REG(0x03010E0B)] #mbmcc -+ CAUSE: TARGET=[REG(0x03010E0B)] OP=[BIT,ON] BIT=[0] #start_cmd -+ EFFECT: TARGET=[REG(0x03010E0B)] OP=[BIT,OFF] BIT=[0] #reset start_cmd -+ #testing counter -+ EFFECT: TARGET=[LOGIC(0xFF018000)] OP=[INCREMENT,MASK] INCVAL=[1] MASK=[LITERAL(64,FFFFFFFF 00000000)] -+ EFFECT: TARGET=[REG(0x03010E0C)] OP=[BIT,ON] BIT=[0] #cmd_ip - } - --# trigger special attention on maint cmd complete - CAUSE_EFFECT { -- LABEL=[Maint Cmd Complete Special Attention MBA1] -- WATCH=[REG(0x03010E0C)] #MBMSR=03010E0C -- CAUSE: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] # Maint Cmd Complete -- CAUSE: TARGET=[REG(0x03010E0F)] OP=[BIT,ON] BIT=[11] # Enable Special attn -- EFFECT: TARGET=[REG(0x03010E11)] OP=[BIT,ON] BIT=[0] # Set Special attn bit -+ # Set logical Centaur register 0xff018001 (first word) to the nth -+ # command that should not reach mbmea. For example: -+ # p8Centaur03.membuf_chip.regwrite "LOGIC" 0xff018001 "00000002" 32 -+ LABEL=[Maint Cmd Error Inject - MBA1] -+ WATCH=[REG(0x03010E0C)] #mbmsr -+ CAUSE: TARGET=[REG(0x03010E0C)] OP=[BIT,ON] BIT=[0] #cmd_ip -+ #error inject -+ CAUSE: TARGET=[LOGIC(0xFF018000)] OP=[EQUALTO,BUF,ON] DATA=[LOGIC(0xFF018001)] -+ EFFECT: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] #cmd_nip -+} -+ -+CAUSE_EFFECT { -+ # Set logical Centaur register 0xff018002 to the nth -+ # command that should never finish -+ LABEL=[Maint Cmd Done - MBA1] -+ WATCH=[REG(0x03010E0C)] #mbmsr -+ CAUSE: TARGET=[REG(0x03010E0C)] OP=[BIT,ON] BIT=[0] #cmd_ip -+ #no error inject -+ CAUSE: TARGET=[LOGIC(0xFF018000)] OP=[EQUALTO,BUF,OFF] DATA=[LOGIC(0xFF018001)] -+ CAUSE: TARGET=[LOGIC(0xFF018000)] OP=[EQUALTO,BUF,OFF] DATA=[LOGIC(0xFF018002)] -+ EFFECT: TARGET=[REG(0x03010E0D)] OP=[EQUALTO,BUF] DATA=[REG(0x03010E0E)] #mbmaca -+ EFFECT: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] #cmd_nip -+} -+ -+CAUSE_EFFECT { -+ LABEL=[Maint Cmd Complete Special Attention - MBA1] -+ WATCH=[REG(0x03010E0C)] #mbmsr -+ CAUSE: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] #cmd_nip -+ CAUSE: TARGET=[REG(0x03010E0F)] OP=[BIT,ON] BIT=[11] #enabled -+ EFFECT: TARGET=[REG(0x03010E11)] OP=[BIT,ON] BIT=[0] #set special attn bit -+ EFFECT: TARGET=[REG(0x03010E11)] OP=[BIT,ON] BIT=[8] #set wat_debug_attn - } - - #*************************************** --# END - Maintenance Command Complete -+# END - Maintenance Commands - #*************************************** - - #*************************************** ---- a/simu/data/cec-chip/p8_common.chip -+++ b/simu/data/cec-chip/p8_common.chip -@@ -8,6 +8,7 @@ - # dsanner 12/05/12 Fix mbox SCRATCH regs - # D864795 dsanner 12/20/12 Add Master logic reg - # @01 D859746 dcrowell 01/30/13 Add winkle aggregator regs -+# 871945 bradleyb 03/01/13 add prd/mdia logic regs - ########################## Architected Registers ########################## - # Format: address , size, internal name (GFW,mycode), external name (simics, virtutech) - ARCHREGS -@@ -357,6 +358,10 @@ INTERNALREGS - - END - -+INTERNALREGS -+ 0xFF200000, 64 # nest gp1 (2000001) mirror (prd/mdia) -+END -+ - #dc01 - ########################## Logical Instruction State ################### - REGSPACE THREADSTATE CHIPLET ex ---- a/simu/data/cec-chip/p8_mba.act -+++ b/simu/data/cec-chip/p8_mba.act -@@ -3,7 +3,15 @@ - # ---- -------- -------- -------- ----------- - # pa01 842625 pacharya 07/18/12 File Created - # Add support for MCI FIR, GP1 Regs. -+# 871945 bradleyb 03/01/13 remove duplicated actions (s1_mba) - -+############################################ -+# -+# Note that p8.chip picks up both s1_mba & this file, -+# so common and/or port4-7 actions should -+# go in s1_mba -+# -+############################################ - ##############ATTENTIONS################ - ######################################## - #------------------------------------------ -@@ -51,52 +59,17 @@ CAUSE_EFFECT { - } - - CAUSE_EFFECT { -- LABEL=[Centaur MemChipet Special Attention] -- WATCH=[ALIAS(mymcPort4)REG(0x03040004)] #MEM_CHIPLET_SA_FIR -- -- CAUSE: TARGET=[ALIAS(mymcPort4)REG(0x03040004)] OP=[AND,ON,BUF,INVERT] DATA=[ALIAS(mymcPort4)REG(0x03040007)] #MEM_CHIPLET_SA_FIR -- -- EFFECT: TARGET=[REG(0x02011C40)] OP=[BIT,ON] BIT=[16] #Setting bit[16] MCI FIR -- EFFECT: TARGET=[REG(0x02011C40)] OP=[BIT,ON] BIT=[17] #Setting bit[17] MCI FIR --} -- --CAUSE_EFFECT { -- LABEL=[Centaur MemChipet Special Attention] -- WATCH=[ALIAS(mymcPort5)REG(0x03040004)] #MEM_CHIPLET_SA_FIR -- -- CAUSE: TARGET=[ALIAS(mymcPort5)REG(0x03040004)] OP=[AND,ON,BUF,INVERT] DATA=[ALIAS(mymcPort5)REG(0x03040007)] #MEM_CHIPLET_SA_FIR -- -- EFFECT: TARGET=[REG(0x02011CC0)] OP=[BIT,ON] BIT=[16] #Setting bit[16] MCI FIR -- EFFECT: TARGET=[REG(0x02011CC0)] OP=[BIT,ON] BIT=[17] #Setting bit[17] MCI FIR --} -- --CAUSE_EFFECT { -- LABEL=[Centaur MemChipet Special Attention] -- WATCH=[ALIAS(mymcPort6)REG(0x03040004)] #MEM_CHIPLET_SA_FIR -- -- CAUSE: TARGET=[ALIAS(mymcPort6)REG(0x03040004)] OP=[AND,ON,BUF,INVERT] DATA=[ALIAS(mymcPort6)REG(0x03040007)] #MEM_CHIPLET_SA_FIR -- -- EFFECT: TARGET=[REG(0x02011D40)] OP=[BIT,ON] BIT=[16] #Setting bit[16] MCI FIR -- EFFECT: TARGET=[REG(0x02011D40)] OP=[BIT,ON] BIT=[17] #Setting bit[17] MCI FIR --} -- --CAUSE_EFFECT { -- LABEL=[Centaur MemChipet Special Attention] -- WATCH=[ALIAS(mymcPort7)REG(0x03040004)] #MEM_CHIPLET_SA_FIR -- -- CAUSE: TARGET=[ALIAS(mymcPort7)REG(0x03040004)] OP=[AND,ON,BUF,INVERT] DATA=[ALIAS(mymcPort7)REG(0x03040007)] #MEM_CHIPLET_SA_FIR -- -- EFFECT: TARGET=[REG(0x02011DC0)] OP=[BIT,ON] BIT=[16] #Setting bit[16] MCI FIR -- EFFECT: TARGET=[REG(0x02011DC0)] OP=[BIT,ON] BIT=[17] #Setting bit[17] MCI FIR --} -- -- --CAUSE_EFFECT { - LABEL=[MCS0-Error] - WATCH=[REG(0x02011840)] # MCI00 FIR -- CAUSE: TARGET=[REG(0x02011840)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011840)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x02011843)] # MCI00 FIRMASK -+ WATCH=[REG(0x02011846)] # MCI00 ACT0 -+ WATCH=[REG(0x02011847)] # MCI00 ACT1 -+ WATCH=[REG(0x0201181A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x0201181A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x02011840)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011843)] -+ CAUSE: TARGET=[REG(0x02011840)] OP=[AND,ON,BUF] DATA=[REG(0x02011846)] -+ CAUSE: TARGET=[REG(0x02011840)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011847)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[7] #Setting bit[7] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[7] - } -@@ -104,9 +77,15 @@ CAUSE_EFFECT { - CAUSE_EFFECT { - LABEL=[MCS1-Error] - WATCH=[REG(0x020118C0)] # MCI01 FIR -- CAUSE: TARGET=[REG(0x020118C0)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x020118C0)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x020118C3)] # MCI01 FIRMASK -+ WATCH=[REG(0x020118C6)] # MCI01 ACT0 -+ WATCH=[REG(0x020118C7)] # MCI01 ACT1 -+ WATCH=[REG(0x0201189A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x0201189A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x020118C0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x020118C3)] -+ CAUSE: TARGET=[REG(0x020118C0)] OP=[AND,ON,BUF] DATA=[REG(0x020118C6)] -+ CAUSE: TARGET=[REG(0x020118C0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x020118C7)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[8] #Setting bit[8] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[8] - } -@@ -114,9 +93,15 @@ CAUSE_EFFECT { - CAUSE_EFFECT { - LABEL=[MCS2-Error] - WATCH=[REG(0x02011940)] # MCI10 FIR -- CAUSE: TARGET=[REG(0x02011940)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011940)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x02011943)] # MCI10 FIRMASK -+ WATCH=[REG(0x02011946)] # MCI10 ACT0 -+ WATCH=[REG(0x02011947)] # MCI10 ACT1 -+ WATCH=[REG(0x0201191A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x0201191A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x02011940)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011943)] -+ CAUSE: TARGET=[REG(0x02011940)] OP=[AND,ON,BUF] DATA=[REG(0x02011946)] -+ CAUSE: TARGET=[REG(0x02011940)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011947)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[9] #Setting bit[9] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[9] - } -@@ -124,77 +109,15 @@ CAUSE_EFFECT { - CAUSE_EFFECT { - LABEL=[MCS3-Error] - WATCH=[REG(0x020119C0)] # MCI11 FIR -- CAUSE: TARGET=[REG(0x020119C0)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x020119C0)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x020119C3)] # MCI11 FIRMASK -+ WATCH=[REG(0x020119C6)] # MCI11 ACT0 -+ WATCH=[REG(0x020119C7)] # MCI11 ACT1 -+ WATCH=[REG(0x0201199A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x0201199A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x020119C0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x020119C3)] -+ CAUSE: TARGET=[REG(0x020119C0)] OP=[AND,ON,BUF] DATA=[REG(0x020119C6)] -+ CAUSE: TARGET=[REG(0x020119C0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x020119C7)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[10] #Setting bit[10] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[10] - } -- --CAUSE_EFFECT { -- LABEL=[MCS4-Error] -- WATCH=[REG(0x02011C40)] # MCI20 FIR -- CAUSE: TARGET=[REG(0x02011C40)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011C40)] OP=[BIT,ON] BIT=[17] -- -- EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[11] #Setting bit[11] P8 NEST GP1 register -- ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[11] --} -- --CAUSE_EFFECT { -- LABEL=[MCS5-Error] -- WATCH=[REG(0x02011CC0)] # MCI21 FIR -- CAUSE: TARGET=[REG(0x02011CC0)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011CC0)] OP=[BIT,ON] BIT=[17] -- -- EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[12] #Setting bit[12] P8 NEST GP1 register -- ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[12] --} -- --CAUSE_EFFECT { -- LABEL=[MCS6-Error] -- WATCH=[REG(0x02011D40)] # MCI30 FIR -- CAUSE: TARGET=[REG(0x02011D40)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011D40)] OP=[BIT,ON] BIT=[17] -- -- EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[13] #Setting bit[13] P8 NEST GP1 register -- ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[13] --} -- --CAUSE_EFFECT { -- LABEL=[MCS7-Error] -- WATCH=[REG(0x02011DC0)] # MCI31 FIR -- CAUSE: TARGET=[REG(0x02011DC0)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011DC0)] OP=[BIT,ON] BIT=[17] -- -- EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[14] #Setting bit[14] P8 NEST GP1 register -- ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[14] --} -- --CAUSE_EFFECT { -- LABEL=[assert-host-err-gp1] -- WATCH=[REG(0x02000001)] # gp1 -- WATCH=[REG(0x01020013)] # ipoll -- -- CAUSE: TARGET=[REG(0x02000001)] OP=[BUF,AND,ON] DATA=[LITERAL(32,01FE0000)] -- CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,OFF] BIT=[3] -- EFFECT: TARGET=[MODULE(lclErrInterrupt, raise)] OP=[MODULECALL] --} -- --CAUSE_EFFECT { -- LABEL=[deassert-host-err-gp1] -- WATCH=[REG(0x02000001)] # gp1 -- -- CAUSE: TARGET=[REG(0x02000001)] OP=[BUF,AND,OFF] DATA=[LITERAL(32,01FE0000)] -- CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,OFF] BIT=[3] -- EFFECT: TARGET=[MODULE(lclErrInterrupt, lower)] OP=[MODULECALL] --} -- --CAUSE_EFFECT { -- LABEL=[deassert-host-err-ipoll] -- WATCH=[REG(0x01020013)] # ipoll -- -- CAUSE: TARGET=[REG(0x02000001)] OP=[BUF,AND,ON] DATA=[LITERAL(32,01FE0000)] -- CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,ON] BIT=[3] -- EFFECT: TARGET=[MODULE(lclErrInterrupt, lower)] OP=[MODULECALL] --} ---- a/simu/data/cec-chip/s1_mba.act -+++ b/simu/data/cec-chip/s1_mba.act -@@ -2,6 +2,7 @@ - # Flag PTR/DCR# Userid Date Description - # ---- -------- -------- -------- ----------- - # 844350 camvanng 07/31/12 File Created (derived from p8_mba.act) -+# 871945 bradleyb 03/01/13 many updates - - ##############ATTENTIONS################ - ######################################## -@@ -52,9 +53,15 @@ CAUSE_EFFECT { - CAUSE_EFFECT { - LABEL=[MCS4-Error] - WATCH=[REG(0x02011C40)] # MCI20 FIR -- CAUSE: TARGET=[REG(0x02011C40)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011C40)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x02011C43)] # MCI20 FIRMASK -+ WATCH=[REG(0x02011C46)] # MCI20 ACT0 -+ WATCH=[REG(0x02011C47)] # MCI20 ACT1 -+ WATCH=[REG(0x02011C1A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x02011C1A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x02011C40)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011C43)] -+ CAUSE: TARGET=[REG(0x02011C40)] OP=[AND,ON,BUF] DATA=[REG(0x02011C46)] -+ CAUSE: TARGET=[REG(0x02011C40)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011C47)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[11] #Setting bit[11] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[11] - } -@@ -62,9 +69,15 @@ CAUSE_EFFECT { - CAUSE_EFFECT { - LABEL=[MCS5-Error] - WATCH=[REG(0x02011CC0)] # MCI21 FIR -- CAUSE: TARGET=[REG(0x02011CC0)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011CC0)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x02011CC3)] # MCI21 FIRMASK -+ WATCH=[REG(0x02011CC6)] # MCI21 ACT0 -+ WATCH=[REG(0x02011CC7)] # MCI21 ACT1 -+ WATCH=[REG(0x02011C9A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x02011C9A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x02011CC0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011CC3)] -+ CAUSE: TARGET=[REG(0x02011CC0)] OP=[AND,ON,BUF] DATA=[REG(0x02011CC6)] -+ CAUSE: TARGET=[REG(0x02011CC0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011CC7)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[12] #Setting bit[12] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[12] - } -@@ -72,9 +85,15 @@ CAUSE_EFFECT { - CAUSE_EFFECT { - LABEL=[MCS6-Error] - WATCH=[REG(0x02011D40)] # MCI30 FIR -- CAUSE: TARGET=[REG(0x02011D40)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011D40)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x02011D43)] # MCI30 FIRMASK -+ WATCH=[REG(0x02011D46)] # MCI30 ACT0 -+ WATCH=[REG(0x02011D47)] # MCI30 ACT1 -+ WATCH=[REG(0x02011D1A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x02011D1A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x02011D40)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011D43)] -+ CAUSE: TARGET=[REG(0x02011D40)] OP=[AND,ON,BUF] DATA=[REG(0x02011D46)] -+ CAUSE: TARGET=[REG(0x02011D40)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011D47)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[13] #Setting bit[13] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[13] - } -@@ -82,38 +101,102 @@ CAUSE_EFFECT { - CAUSE_EFFECT { - LABEL=[MCS7-Error] - WATCH=[REG(0x02011DC0)] # MCI31 FIR -- CAUSE: TARGET=[REG(0x02011DC0)] OP=[BIT,ON] BIT=[16] -- CAUSE: TARGET=[REG(0x02011DC0)] OP=[BIT,ON] BIT=[17] -- -+ WATCH=[REG(0x02011DC3)] # MCI31 FIRMASK -+ WATCH=[REG(0x02011DC6)] # MCI31 ACT0 -+ WATCH=[REG(0x02011DC7)] # MCI31 ACT1 -+ WATCH=[REG(0x02011D9A)] # mcsmode4 -+ -+ CAUSE: TARGET=[REG(0x02011D9A)] OP=[BIT,ON] BIT=[13] #mcsmode4 -+ CAUSE: TARGET=[REG(0x02011DC0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011DC3)] -+ CAUSE: TARGET=[REG(0x02011DC0)] OP=[AND,ON,BUF] DATA=[REG(0x02011DC6)] -+ CAUSE: TARGET=[REG(0x02011DC0)] OP=[AND,ON,BUF,INVERT] DATA=[REG(0x02011DC7)] - EFFECT: TARGET=[REG(0x02000001)] OP=[BIT,ON] BIT=[14] #Setting bit[14] P8 NEST GP1 register - ELSE: TARGET=[REG(0x02000001)] OP=[BIT,OFF] BIT=[14] - } - - CAUSE_EFFECT { -- LABEL=[assert-host-err-gp1] -- WATCH=[REG(0x02000001)] # gp1 -- WATCH=[REG(0x01020013)] # ipoll -+ LABEL=[PBus Host Attention - Set] -+ WATCH=[REG(0x02000001)] -+ CAUSE: TARGET=[REG(0x02000001)] OP=[EQUALTO,BUF,OFF] DATA=[LOGIC(0xFF200000)] -+ CAUSE: TARGET=[REG(0x02000001)] OP=[AND,ON,BUF,INVERT,MASK] DATA=[LOGIC(0xFF200000)] MASK=[REG(0x02000002)] -+ EFFECT: TARGET=[REG(0x01020000)] OP=[BIT,ON] BIT=[2] -+} - -- CAUSE: TARGET=[REG(0x02000001)] OP=[BUF,AND,ON] DATA=[LITERAL(32,01FE0000)] -- CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,OFF] BIT=[3] -- EFFECT: TARGET=[MODULE(lclErrInterrupt, raise)] OP=[MODULECALL] -+CAUSE_EFFECT { -+ LABEL=[PBus Host Attention - Cleared] -+ WATCH=[REG(0x02000001)] -+ CAUSE: TARGET=[REG(0x02000001)] OP=[EQUALTO,BUF,OFF] DATA=[LOGIC(0xFF200000)] -+ CAUSE: TARGET=[LOGIC(0xFF200000)] OP=[AND,ON,BUF,INVERT,MASK] DATA=[REG(0x02000001)] MASK=[REG(0x02000002)] -+ EFFECT: TARGET=[REG(0x01020000)] OP=[BIT,ON] BIT=[2] - } - - CAUSE_EFFECT { -- LABEL=[deassert-host-err-gp1] -- WATCH=[REG(0x02000001)] # gp1 -+ LABEL=[PBus GP1 Mirror] -+ WATCH=[REG(0x02000001)] -+ # No cause since we always want this behavior -+ EFFECT: TARGET=[LOGIC(0xFF200000)] OP=[BUF,EQUALTO] DATA=[REG(0x02000001)] -+} - -- CAUSE: TARGET=[REG(0x02000001)] OP=[BUF,AND,OFF] DATA=[LITERAL(32,01FE0000)] -- CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,OFF] BIT=[3] -- EFFECT: TARGET=[MODULE(lclErrInterrupt, lower)] OP=[MODULECALL] -+CAUSE_EFFECT { -+ LABEL=[Ipoll Status - GP Host Attention - Host Bridge] -+ WATCH=[REG(0x01020000)] # GP interrupt presentation -+ WATCH=[REG(0x0102000C)] # interrupt type mask -+ WATCH=[REG(0x01020013)] # ipoll mask -+ CAUSE: TARGET=[REG(0x01020000)] OP=[BUF,AND,ON] DATA=[LITERAL(32,FFFFFFFF)] -+ CAUSE: TARGET=[REG(0x0102000C)] OP=[BIT,OFF] BIT=[0] #interrupt type mask -+ CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,OFF] BIT=[3] #ipoll mask -+ EFFECT: TARGET=[REG(0x01020014)] OP=[BIT,ON] BIT=[3] -+ ELSE: TARGET=[REG(0x01020014)] OP=[BIT,OFF] BIT=[3] - } - - CAUSE_EFFECT { -- LABEL=[deassert-host-err-ipoll] -- WATCH=[REG(0x01020013)] # ipoll -+ LABEL=[Ipoll Status - GP Host Attention - FSI] -+ WATCH=[REG(0x01020000)] # GP interrupt presentation -+ WATCH=[REG(0x0102000C)] # interrupt type mask -+ WATCH=[REG(0x01020013)] # ipoll mask -+ CAUSE: TARGET=[REG(0x01020000)] OP=[BUF,AND,ON] DATA=[LITERAL(32,FFFFFFFF)] -+ CAUSE: TARGET=[REG(0x0102000C)] OP=[BIT,OFF] BIT=[0] #interrupt type mask -+ CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,OFF] BIT=[7] #ipoll mask -+ EFFECT: TARGET=[REG(0x01020014)] OP=[BIT,ON] BIT=[7] -+ ELSE: TARGET=[REG(0x01020014)] OP=[BIT,OFF] BIT=[7] -+} - -- CAUSE: TARGET=[REG(0x02000001)] OP=[BUF,AND,ON] DATA=[LITERAL(32,01FE0000)] -- CAUSE: TARGET=[REG(0x01020013)] OP=[BIT,ON] BIT=[3] -- EFFECT: TARGET=[MODULE(lclErrInterrupt, lower)] OP=[MODULECALL] -+CAUSE_EFFECT { -+ LABEL=[local err intr] -+ WATCH=[REG(0x01020014)] # ipoll status -+ CAUSE: TARGET=[REG(0x01020014)] OP=[BUF,AND,ON] DATA=[LITERAL(8,F0000000)] -+ EFFECT: TARGET=[MODULE(lclErrInterrupt, raise)] OP=[MODULECALL] -+ ELSE: TARGET=[MODULE(lclErrInterrupt, lower)] OP=[MODULECALL] - } - -+CAUSE_EFFECT { -+ LABEL=[GPIO Interrupt Presentation Reg - Or] -+ WATCH=[REG(0x01020001)] -+ # No cause since we always want this behavior -+ EFFECT: TARGET=[REG(0x01020000)] OP=[OR,ON,BUF] DATA=[REG(0x01020001)] -+ EFFECT: TARGET=[REG(0x01020001)] OP=[ALLZEROS] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[GPIO Interrupt Presentation Reg - And] -+ WATCH=[REG(0x01020002)] -+ # No cause since we always want this behavior -+ EFFECT: TARGET=[REG(0x01020000)] OP=[AND,OFF,BUF] DATA=[REG(0x01020002)] -+ EFFECT: TARGET=[REG(0x01020002)] OP=[ALLONES] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[Interrupt Type Mask - Or] -+ WATCH=[REG(0x0102000D)] -+ # No cause since we always want this behavior -+ EFFECT: TARGET=[REG(0x0102000C)] OP=[OR,ON,BUF] DATA=[REG(0x0102000D)] -+ EFFECT: TARGET=[REG(0x0102000D)] OP=[ALLZEROS] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[Interrupt Type Mask - And] -+ WATCH=[REG(0x0102000E)] -+ # No cause since we always want this behavior -+ EFFECT: TARGET=[REG(0x0102000C)] OP=[AND,OFF,BUF] DATA=[REG(0x0102000E)] -+ EFFECT: TARGET=[REG(0x0102000E)] OP=[ALLONES] -+} ---- a/simu/data/cec-chip/p8.chip -+++ b/simu/data/cec-chip/p8.chip -@@ -22,6 +22,7 @@ - - # ch140 F853129 ched 09/13/12 Support "Scan via Scom" LOGIC regs - # pa02 852431 pacharya 09/27/12 Change chipletid of XBUS -+# SW189255 bradleyb 03/01/13 include s1_mba.act for common actions - - - VERSION 1 # .chip file format ID -@@ -44,6 +45,7 @@ SCOMDEF = default - ACTIONS=p8.act - ACTIONS=p8_inst.act - ACTIONS=p8_mba.act -+ACTIONS=s1_mba.act - - RAMOPS=p8.inst - diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt index 95d14dea9..5c8c92fb3 100644 --- a/src/build/citest/etc/patches/patchlist.txt +++ b/src/build/citest/etc/patches/patchlist.txt @@ -4,9 +4,3 @@ Brief description of the problem or reason for patch -CMVC: Defect/Req for checking the changes into fips810 -Files: list of files -Coreq: list of associated changes, e.g. workarounds.presimsetup - -Fix broken ITR Macro actions. Improve maint cmd actions. --RTC: 66137 --CMVC: 871945 --Files: mdia-actions.patch --Coreq: None diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 66e865aa5..40bf41a1a 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -25,12 +25,3 @@ ## Workarounds that are run after start_simics is executed for the first time ## to setup the sandbox ## -mkdir -p $sb/simu/data/cec-chip -echo "+++ Updating actions for mdia" -cp $BACKING_BUILD/src/simu/data/cec-chip/p8_mba.act $sb/simu/data/cec-chip -cp $BACKING_BUILD/src/simu/data/cec-chip/s1_mba.act $sb/simu/data/cec-chip -cp $BACKING_BUILD/src/simu/data/cec-chip/p8.chip $sb/simu/data/cec-chip -cp $BACKING_BUILD/src/simu/data/cec-chip/p8_common.chip $sb/simu/data/cec-chip -cp $BACKING_BUILD/src/simu/data/cec-chip/centaur.act $sb/simu/data/cec-chip -cp $BACKING_BUILD/src/simu/data/cec-chip/centaur.chip $sb/simu/data/cec-chip -patch -p1 -d $sb < $HOSTBOOTROOT/src/build/citest/etc/patches/mdia-actions.patch diff --git a/src/build/debug/simics-debug-framework.py b/src/build/debug/simics-debug-framework.py index 4e868d725..d1b4fd452 100755 --- a/src/build/debug/simics-debug-framework.py +++ b/src/build/debug/simics-debug-framework.py @@ -353,7 +353,7 @@ def hexDumpToNumber(hexlist): # Fetch the current HRMOR value. def getHRMOR(): - runStr = "(system_cmp0.cpu0_0_05_0).read-reg HRMOR" + runStr = "(system_cmp0.cpu0_0_04_0).read-reg HRMOR" ( result, out ) = quiet_run_command( runStr, output_modes.regular ) return result diff --git a/src/usr/targeting/namedtarget.C b/src/usr/targeting/namedtarget.C index df67777f8..7784ddf30 100644 --- a/src/usr/targeting/namedtarget.C +++ b/src/usr/targeting/namedtarget.C @@ -70,8 +70,8 @@ const TARGETING::Target * getMasterCore( ) true ); TRACDCOMP( g_trac_targeting, - "getMasterCore: found %d cores on master proc", - l_cores.size() ); + "getMasterCore: found %d cores on master proc, l_mastreCoreID:0x%X", + l_cores.size(),l_masterCoreID ); for (TARGETING::TargetHandleList::const_iterator coreIter = l_cores.begin(); @@ -88,7 +88,7 @@ const TARGETING::Target * getMasterCore( ) pir |= l_logicalNodeId << 10; if (pir == l_masterCoreID){ - TRACDCOMP( g_trac_targeting, + TRACFCOMP( g_trac_targeting, "found master core: 0x%x, PIR=0x%x :", l_coreId, pir ); diff --git a/src/usr/vpd/makefile b/src/usr/vpd/makefile index 38adc2ea1..db17207a6 100644 --- a/src/usr/vpd/makefile +++ b/src/usr/vpd/makefile @@ -28,7 +28,7 @@ OBJS = vpd.o spd.o ipvpd.o mvpd.o dimmPres.o cvpd.o SUBDIRS = test.d BINARY_FILES = $(IMGDIR)/dimmspd.dat:9a6e6b6a7f6d3fc77a12d38537279d402124d699 -BINARY_FILES += $(IMGDIR)/procmvpd.dat:dc85f0e2f7b26f3928c817be3f0c37a9cc0e0bed +BINARY_FILES += $(IMGDIR)/procmvpd.dat:9473e24c02c40a577700ae0292676c4b82698c13 BINARY_FILES += $(IMGDIR)/cvpd.dat:199b4db0140c2021c82c73b88d7516dde52a2718 include ${ROOTPATH}/config.mk diff --git a/src/usr/vpd/test/mvpdtest.H b/src/usr/vpd/test/mvpdtest.H index 94faefc58..d40ea22d3 100755 --- a/src/usr/vpd/test/mvpdtest.H +++ b/src/usr/vpd/test/mvpdtest.H @@ -74,7 +74,6 @@ mvpdTestData mvpdData[] = { MVPD::CP00, MVPD::pdR }, { MVPD::CP00, MVPD::pdG }, { MVPD::CP00, MVPD::pdV }, - { MVPD::CP00, MVPD::pdH }, // { MVPD::CP00, pdP }, // no #P in test data { MVPD::CP00, MVPD::SB }, { MVPD::CP00, MVPD::MK }, @@ -89,13 +88,14 @@ mvpdTestData mvpdData[] = { MVPD::LRP5, MVPD::pdP }, { MVPD::LRP5, MVPD::pdM }, { MVPD::LRP5, MVPD::CH }, - { MVPD::LRP6, MVPD::VD }, - { MVPD::LRP6, MVPD::pdV }, - { MVPD::LRP6, MVPD::pdP }, - { MVPD::LRP6, MVPD::pdM }, - { MVPD::LRP6, MVPD::CH }, - /* // no LRP7,LRP8,LRP9,LRPA,LRPB,LWPO,LWP1,LWP2,LWP3 +/* + // no LRP6, LRP7,LRP8,LRP9,LRPA,LRPB,LWPO,LWP1,LWP2,LWP3 in test data + { MVPD::LRP6, MVPD::VD }, + { MVPD::LRP6, MVPD::pdV }, + { MVPD::LRP6, MVPD::pdP }, + { MVPD::LRP6, MVPD::pdM }, + { MVPD::LRP6, MVPD::CH }, { MVPD::LRP7, VD }, { MVPD::LRP7, MVPD::pdV }, { MVPD::LRP7, MVPD::pdP }, @@ -161,11 +161,11 @@ mvpdTestData mvpdData[] = { MVPD::LWP5, MVPD::pd2 }, { MVPD::LWP5, MVPD::pd3 }, { MVPD::LWP5, MVPD::IN }, - { MVPD::LWP6, MVPD::VD }, - { MVPD::LWP6, MVPD::pd2 }, - { MVPD::LWP6, MVPD::pd3 }, - { MVPD::LWP6, MVPD::IN }, - /* // no LWP7,LWP8,LWP9,LWPA,LWPB in test data + /* // no LWP6, LWP7,LWP8,LWP9,LWPA,LWPB in test data + { MVPD::LWP6, MVPD::VD }, + { MVPD::LWP6, MVPD::pd2 }, + { MVPD::LWP6, MVPD::pd3 }, + { MVPD::LWP6, MVPD::IN }, { MVPD::LWP7, MVPD::VD }, { MVPD::LWP7, MVPD::pd2 }, { MVPD::LWP7, MVPD::pd3 }, |
