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-rw-r--r--src/build/citest/etc/patches/patchlist.txt11
-rwxr-xr-xsrc/build/citest/etc/workarounds.postsimsetup15
-rwxr-xr-xsrc/build/citest/etc/workarounds.presimsetup7
-rwxr-xr-xsrc/build/mkrules/hbfw/img/makefile2
-rw-r--r--src/usr/pnor/pnordd.C4
-rw-r--r--src/usr/pnor/pnordd.H3
6 files changed, 34 insertions, 8 deletions
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt
index 18371bf8f..0f71eeaf5 100644
--- a/src/build/citest/etc/patches/patchlist.txt
+++ b/src/build/citest/etc/patches/patchlist.txt
@@ -10,3 +10,14 @@ Additional actions for Centaur maint command complete
-CMVC: D864673 is integrating the changes
-Files: p8_mba.act.patch s1_mba.act.patch
-Coreq: there are related changes in workarounds.postsimsetup
+
+Override the simics level
+-RTC: Story 60617 will remove the patch
+-CMVC: Simics team is updating simicsInfo, Feature 864898
+-Files: workarounds.presimsetup
+-Coreq: there are related changes in workarounds.postsimsetup
+
+Override simics config file values
+-RTC: Story 60780 will remove the patch
+-CMVC: Feature 864669 used to checkin config file changes
+-Coreq: there are related changes in workarounds.presimsetup
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 7ff9800d4..b7d9c5883 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -98,3 +98,18 @@ cp $bb/src/simu/data/cec-chip/s1_mba.act $sb/simu/data/cec-chip/s1_mba.act
patch -p0 $sb/simu/data/cec-chip/p8_mba.act $HOSTBOOTROOT/src/build/citest/etc/patches/p8_mba.act.patch
patch -p0 $sb/simu/data/cec-chip/s1_mba.act $HOSTBOOTROOT/src/build/citest/etc/patches/s1_mba.act.patch
###
+
+#remove with RTC 60780
+echo "+++ Updating config files - checked in with CMVC Defect 864669"
+mkdir -p $sb/simu/configs
+egrep -v "GFW_P8_MURANO_PNOR_DIRECT_MMIO" $BACKING_BUILD/src/simu/configs/P8_MURANO.config > $sb/simu/configs/P8_MURANO.config
+echo "SETENV GFW_P8_MURANO_PNOR_DIRECT_MMIO 0xC000000 " >> $sb/simu/configs/P8_MURANO.config
+
+egrep -v "GFW_P8_VENICE_PNOR_DIRECT_MMIO" $BACKING_BUILD/src/simu/configs/P8_VENICE.config > $sb/simu/configs/P8_VENICE.config
+echo "SETENV GFW_P8_VENICE_PNOR_DIRECT_MMIO 0xC000000 " >> $sb/simu/configs/P8_VENICE.config
+
+egrep -v "GFW_P8_TULETA_PNOR_DIRECT_MMIO" $BACKING_BUILD/src/simu/configs/P8_TULETA.config > $sb/simu/configs/P8_TULETA.config
+echo "SETENV GFW_P8_TULETA_PNOR_DIRECT_MMIO 0xC000000 " >> $sb/simu/configs/P8_TULETA.config
+
+egrep -v "GFW_P8_TULETA_PNOR_DIRECT_MMIO" $BACKING_BUILD/src/simu/configs/P8_TULETA_POWERON.config > $sb/simu/configs/P8_TULETA_POWERON.config
+echo "SETENV GFW_P8_TULETA_PNOR_DIRECT_MMIO 0xC000000 " >> $sb/simu/configs/P8_TULETA_POWERON.config
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index ff8ff16ca..27e844dc9 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -33,8 +33,9 @@
#echo "WSALIAS HOSTBOOT_LEVEL FIPSLEVEL env/gfwb/simics-4.2.0/simics-4.2.83/fips/fld36/fi120201a700.42" >> $sb/simu/data/simicsInfo
#echo "WSALIAS HOSTBOOT_LEVEL SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.83/bin" >> $sb/simu/data/simicsInfo
-echo "+++ Backing to Simics Build for Scan support remove with RTC:60617."
+echo "+++ Backing to Simics Build for Scan support and PNOR mmio changes."
+# remove with RTC:60617 when simics info contains FIPSLEVEL fi121218a800.42
+# or later.
mkdir -p $sb/simu/data
egrep -v "WSALIAS DEFAULT FIPSLEVEL " $BACKING_BUILD/src/simu/data/simicsInfo > $sb/simu/data/simicsInfo
-echo "WSALIAS DEFAULT FIPSLEVEL env/gfwf/simics-4.2.0/simics-4.2.98/fips/fld36/fi121211q800.42 " >> $sb/simu/data/simicsInfo
-echo "WSALIAS DEFAULT SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.98/bin" >> $sb/simu/data/simicsInfo
+echo "WSALIAS DEFAULT FIPSLEVEL env/gfwf/simics-4.2.0/simics-4.2.98/fips/fld36/fi121218a800.42 " >> $sb/simu/data/simicsInfo
diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile
index 0c0b231ab..58f7ac72b 100755
--- a/src/build/mkrules/hbfw/img/makefile
+++ b/src/build/mkrules/hbfw/img/makefile
@@ -55,7 +55,7 @@ BASE_ECC_IMAGE = hostboot.bin.ecc
cp_hbfiles: .SPECTARG
${BASE_IMAGES:@image@cp -f -u ${SRCPATH:F${image}} ${image};@}
- echo "0000000000180000000000000800000000081000" | xxd -r -ps - sbe.header
+ echo "000000000018000000000000080000000000000000081000" | xxd -r -ps - sbe.header
dd if=/dev/zero of=secureboot.header bs=1 count=4K
cat sbe.header secureboot.header ${BASE_IMAGE} > ${BASE_W_HEADER_IMAGE}
currentsb -chain
diff --git a/src/usr/pnor/pnordd.C b/src/usr/pnor/pnordd.C
index 043f4ce39..abadd8117 100644
--- a/src/usr/pnor/pnordd.C
+++ b/src/usr/pnor/pnordd.C
@@ -425,7 +425,7 @@ void PnorDD::sfcInit( )
errlHndl_t l_err = NULL;
//Initial configuration settings for SFC:
- #define oadrnb_init 0x04000000 //Set MMIO/Direct window to start at 64MB
+ #define oadrnb_init 0x0C000000 //Set MMIO/Direct window to start at 64MB
#define oadrns_init 0x0000000F //Set the MMIO/Direct window size to 64MB
#define adrcbf_init 0x00000000 //Set the flash index to 0
#define adrcmf_init 0x0000000F //Set the flash size to 64MB
@@ -703,7 +703,7 @@ errlHndl_t PnorDD::pollSfcOpComplete(uint64_t i_pollTime)
errlHndl_t PnorDD::micronOpComplete(uint64_t i_pollTime)
{
errlHndl_t l_err = NULL;
- TRACFCOMP( g_trac_pnor, "PnorDD::micronOpComplete> i_pollTime=0x%.8x",
+ TRACDCOMP( g_trac_pnor, "PnorDD::micronOpComplete> i_pollTime=0x%.8x",
i_pollTime );
do {
diff --git a/src/usr/pnor/pnordd.H b/src/usr/pnor/pnordd.H
index 105f0cfa3..d74c6ba01 100644
--- a/src/usr/pnor/pnordd.H
+++ b/src/usr/pnor/pnordd.H
@@ -392,10 +392,9 @@ class PnorDD
LPCHC_IO_SPACE = 0xD0010000, /**< LPC Host Controller I/O Space */
LPCHC_REG_SPACE = 0xC0012000, /**< LPC Host Ctlr Register Space */
- LPC_DIRECT_READ_OFFSET = 0xFC000000,
LPC_SFC_CMDREG_OFFSET = 0xF0000C00, /** LPC Offest to SFC Cmd Regs */
LPC_SFC_CMDBUF_OFFSET = 0xF0000D00, /** LPC Off to SFC Cmd Buf space */
- LPC_SFC_MMIO_OFFSET = 0xF4000000, /** LPC Off to SFC Direct Read space*/
+ LPC_SFC_MMIO_OFFSET = 0xFC000000, /** LPC Off to SFC Direct Read space*/
LPC_TOP_OF_FLASH_OFFSET = 0xFFFFFFFF,
ECCB_CTL_REG = 0x000B0020, /**< ECCB Control Reg (FW) */
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