diff options
Diffstat (limited to 'src')
3 files changed, 52 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C index c18f014ff..88a7f5699 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C @@ -42,4 +42,7 @@ constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_UE_REGS[]; constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_AUE_REGS[]; constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::ERROR_VECTOR_REGS[]; +constexpr const uint8_t eccTraits<fapi2::TARGET_TYPE_MCA>::symbol2galois[]; +constexpr const uint8_t eccTraits<fapi2::TARGET_TYPE_MCA>::symbol2dq[]; + } // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H index 75f79b42f..d12e4ed6c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H @@ -185,6 +185,54 @@ class eccTraits<fapi2::TARGET_TYPE_MCA> }; + // Symbol to Galois code mapping table + // Reference: Nimbus workbook, Section 13.1.6.2: Firmware Mark Store + constexpr static const uint8_t symbol2galois[] = + { + 0x80, 0xa0, 0x90, 0xf0, + 0x08, 0x0a, 0x09, 0x8f, + 0x98, 0xda, 0xb9, 0x7f, + 0x91, 0xd7, 0xb2, 0x78, + 0x28, 0xea, 0x49, 0x9f, + 0x9a, 0xd4, 0xbd, 0x76, + 0x60, 0xb0, 0xc0, 0x20, + 0x06, 0x0b, 0x0c, 0x02, + 0xc6, 0xfb, 0x1c, 0x42, + 0xca, 0xf4, 0x1d, 0x46, + 0xd6, 0x8b, 0x3c, 0xc2, + 0xcb, 0xf3, 0x1f, 0x4e, + 0xe0, 0x10, 0x50, 0xd0, + 0x0e, 0x01, 0x05, 0x0d, + 0x5e, 0x21, 0xa5, 0x3d, + 0x5b, 0x23, 0xaf, 0x3e, + 0xfe, 0x61, 0x75, 0x5d, + 0x51, 0x27, 0xa2, 0x38 + }; + + // Symbol to DQ index mapping table + // Reference: Nimbus workbook, Section 13.1.6.2: Firmware Mark Store + constexpr static const uint8_t symbol2dq[] = + { + 71, 70, 69, 68, + 67, 66, 65, 64, + 63, 62, 61, 60, + 55, 54, 53, 52, + 47, 46, 45, 44, + 39, 38, 37, 36, + 31, 30, 29, 28, + 23, 22, 21, 20, + 15, 14, 13, 12, + 7, 6, 5, 4, + 59, 58, 57, 56, + 51, 50, 49, 48, + 43, 42, 41, 40, + 35, 34, 33, 32, + 27, 26, 25, 24, + 19, 18, 17, 16, + 11, 10, 9, 8, + 3, 2, 1, 0 + }; + }; /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index c10073723..133fe50c1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -49,6 +49,7 @@ enum sizes DEFAULT_POLL_LIMIT = 10, ///< the number of poll attempts in the event we can't calculate another MAX_NUM_IMP = 4, ///< number of impedances valid per slew type MAX_NUM_CAL_SLEW_RATES = 4, ///< 3V/ns, 4V/ns, 5V/ns, 6V/n + MAX_DQ_BITS = 72, /// TODO RTC:157753 This is Nimbus specific. Should be attribute/trait of processor. BYTES_PER_GB = 1000000000, ///< Multiplier to go from GB to B T_PER_MT = 1000000, ///< Multiplier to go from MT/s to T/s |
