diff options
Diffstat (limited to 'src')
11 files changed, 1459 insertions, 76 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C index 3ef743dbf..de0bbfc57 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C @@ -22,3 +22,215 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file explorer_efd_processing.C +/// @brief Processing for EFD for eff config +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#include <fapi2.H> +#include <lib/shared/exp_consts.H> +#include <exp_data_structs.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <generic/memory/lib/spd/spd_facade.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> +#include <lib/eff_config/explorer_efd_processing.H> + +namespace mss +{ +namespace exp +{ +namespace efd +{ + +/// +/// @brief Processes the CAC delay A side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_a(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_addr_delay_a[DRAMINIT_NUM_ADDR_DELAYS] = {}; + const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + FAPI_TRY(mss::attr::get_exp_atxdly_a(l_port, l_addr_delay_a)); + + // Update the values + FAPI_TRY(i_efd_data->cac_delay_a_side_group_0(l_addr_delay_a[0])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_1(l_addr_delay_a[1])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_2(l_addr_delay_a[2])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_3(l_addr_delay_a[3])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_4(l_addr_delay_a[4])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_5(l_addr_delay_a[5])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_6(l_addr_delay_a[6])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_7(l_addr_delay_a[7])); + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_atxdly_a(l_port, l_addr_delay_a)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the CAC delay B side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_addr_delay_b[DRAMINIT_NUM_ADDR_DELAYS] = {}; + const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + FAPI_TRY(mss::attr::get_exp_atxdly_b(l_port, l_addr_delay_b)); + + // Update the values + FAPI_TRY(i_efd_data->cac_delay_b_side_group_0(l_addr_delay_b[0])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_1(l_addr_delay_b[1])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_2(l_addr_delay_b[2])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_3(l_addr_delay_b[3])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_4(l_addr_delay_b[4])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_5(l_addr_delay_b[5])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_6(l_addr_delay_b[6])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_7(l_addr_delay_b[7])); + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_atxdly_b(l_port, l_addr_delay_b)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the Host RD VREF DQ +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode host_rd_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_vref = 0; + const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + FAPI_TRY(mss::attr::get_exp_init_vref_dq(l_port, l_vref)); + + // Update the values + FAPI_TRY(i_efd_data->phy_vref_percent(l_vref)); + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_init_vref_dq(l_port, l_vref)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the CS command latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_cmd_latency = 0; + FAPI_TRY(mss::attr::get_cs_cmd_latency(i_target, l_cmd_latency)); + + // Update the values + FAPI_TRY(i_efd_data->bist_ca_latency_mode(l_cmd_latency)); + + // Set the attribute + FAPI_TRY(mss::attr::set_cs_cmd_latency(i_target, l_cmd_latency)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the CA parity latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_ca_parity_latency = 0; + FAPI_TRY(mss::attr::get_ca_parity_latency(i_target, l_ca_parity_latency)); + + // Update the values + FAPI_TRY(i_efd_data->bist_ca_pl_mode(l_ca_parity_latency)); + + // Set the attribute + FAPI_TRY(mss::attr::set_ca_parity_latency(i_target, l_ca_parity_latency)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the DFIMRL_DDRCLK +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode dfimrl_ddrclk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_dfimrl_ddrclk = 0; + const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + FAPI_TRY(mss::attr::get_exp_dfimrl_clk(l_port, l_dfimrl_ddrclk)); + + // Update the values + FAPI_TRY(i_efd_data->dfimrl_ddrclk(l_dfimrl_ddrclk)); + + // Set the attribute + FAPI_TRY(mss::attr::get_exp_dfimrl_clk(l_port, l_dfimrl_ddrclk)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Process the EFD data and set attributes +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode process(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + FAPI_TRY(host_rd_vref_dq(i_target, i_efd_data)); + FAPI_TRY(cs_cmd_latency(i_target, i_efd_data)); + FAPI_TRY(ca_parity_latency(i_target, i_efd_data)); + FAPI_TRY(dfimrl_ddrclk(i_target, i_efd_data)); + FAPI_TRY(cac_delay_a(i_target, i_efd_data)); + FAPI_TRY(cac_delay_b(i_target, i_efd_data)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns efd +} // ns exp +} // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H index 7189811d4..e7c13efaa 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H @@ -22,3 +22,99 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file explorer_efd_processing.H +/// @brief Processing for EFD for eff config +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#ifndef _MSS_EXPLORER_EFD_PROCESSING_H_ +#define _MSS_EXPLORER_EFD_PROCESSING_H_ + +#include <fapi2.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <generic/memory/lib/spd/spd_facade.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> + +namespace mss +{ +namespace exp +{ +namespace efd +{ + +/// +/// @brief Processes the CAC delay A side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_a(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the CAC delay A side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the Host RD VREF DQ +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode host_rd_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the CS command latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the CA parity latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the DFIMRL_DDRCLK +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode dfimrl_ddrclk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Process the EFD data and set attributes +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode process(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); +} // ns efd +} // ns exp +} // ns mss +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H index ab24f989c..4309c7fe4 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H @@ -235,7 +235,7 @@ class phy_params /// /// @brief fetch the attributes and initialize it to the params /// @param[in] i_target the fapi2 target - /// @param[in,out] o_rc the fapi2 output + /// @param[out] o_rc the fapi2 output /// phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, fapi2::ReturnCode& o_rc): diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C index a3358f3ce..0e3224827 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C @@ -43,6 +43,7 @@ #include <mss_generic_attribute_getters.H> #include <lib/eff_config/explorer_attr_engine_traits.H> #include <lib/eff_config/pmic_attr_engine_traits.H> +#include <lib/eff_config/explorer_efd_processing.H> #include <lib/freq/axone_freq_traits.H> #include <lib/freq/axone_sync.H> #include <generic/memory/mss_git_data_helper.H> @@ -93,6 +94,8 @@ fapi2::ReturnCode p9a_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MEM // Set up SI ATTRS FAPI_TRY( mss::attr_si_engine<mss::attr_si_engine_fields>::set(l_efd_data) ); + + FAPI_TRY( mss::exp::efd::process(dimm, l_efd_data)); } { diff --git a/src/import/generic/memory/lib/data_engine/data_engine_utils.H b/src/import/generic/memory/lib/data_engine/data_engine_utils.H index cea9c7369..56d2b2d3b 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_utils.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_utils.H @@ -46,40 +46,6 @@ namespace mss { -/// -/// @brief Mapping boilerplate check -/// @tparam T FAPI2 target type -/// @tparam IT map key type -/// @tparam OT map value type -/// @param[in] i_target the FAPI target -/// @param[in] i_map SPD to attribute data mapping -/// @param[in] i_ffdc_code FFDC function code -/// @param[in] i_key Key to query map -/// @param[out] o_output value from key -/// @return FAPI2_RC_SUCCESS iff okay -/// -template< fapi2::TargetType T, typename IT, typename OT > -inline fapi2::ReturnCode lookup_table_check(const fapi2::Target<T>& i_target, - const std::vector<std::pair<IT, OT>>& i_map, - const generic_ffdc_codes i_ffdc_code, - const IT i_key, - OT& o_output) -{ - const bool l_is_val_found = mss::find_value_from_key(i_map, i_key, o_output); - - FAPI_ASSERT( l_is_val_found, - fapi2::MSS_LOOKUP_FAILED() - .set_KEY(i_key) - .set_DATA(o_output) - .set_FUNCTION(i_ffdc_code) - .set_TARGET(i_target), - "Failed to find a mapped value for %d on %s", - i_key, - mss::spd::c_str(i_target) ); -fapi_try_exit: - return fapi2::current_err; -} - // Controller agnostic functions namespace gen diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H index 12acc87ef..f3693dcd2 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H @@ -40,6 +40,7 @@ #include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <generic/memory/lib/spd/ddimm/efd_decoder.H> #include <generic/memory/lib/utils/mss_buffer_utils.H> +#include <generic/memory/lib/utils/find.H> namespace mss { @@ -501,6 +502,19 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b } /// + /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::PHY_VREF_PERCENT, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_VALUE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay @@ -631,6 +645,296 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b } /// + /// @brief Decodes BIST CAL Mode -> BIST_CA_LATENCY_MODE + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode bist_ca_latency_mode(uint8_t& o_output) const + { + // Note: using a one-to-one mapping to allow us to re-use the API + // We really just need to check that the value exists in the list + const std::vector<std::pair<uint8_t, uint8_t>> ALLOWED_VALUES = + { + {0b0000, 0b0000}, + {0b0011, 0b0011}, + {0b0100, 0b0100}, + {0b0101, 0b0101}, + {0b0110, 0b0110}, + {0b1000, 0b1000}, + }; + + FAPI_TRY( (reader<fields_t::BIST_CA_LATENCY_MODE, R>(iv_target, iv_data, o_output)) ); + + { + // Map EFD value to desired setting + // Value and key should be the same thing, just creating a helper variable to avoid confusion + const auto l_key = o_output; + uint8_t l_value = 0; + o_output = 0; + FAPI_TRY(lookup_table_check(iv_target, ALLOWED_VALUES, EFD_CA_LATENCY_MODE, l_key, o_output)); + o_output = l_value; + } + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes BIST CA Parity Latency Mode -> BIST_CA_PL_MODE + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode bist_ca_pl_mode(uint8_t& o_output) const + { + // Note: using a one-to-one mapping to allow us to re-use the API + // We really just need to check that the value exists in the list + const std::vector<std::pair<uint8_t, uint8_t>> ALLOWED_VALUES = + { + {0b0000, 0b0000}, + {0b0100, 0b0100}, + {0b0101, 0b0101}, + {0b0110, 0b0110}, + {0b1000, 0b1000}, + }; + + FAPI_TRY( (reader<fields_t::BIST_CA_PL_MODE, R>(iv_target, iv_data, o_output)) ); + + { + // Map EFD value to desired setting + // Value and key should be the same thing, just creating a helper variable to avoid confusion if we return with a bad value and an RC + const auto l_key = o_output; + uint8_t l_value = 0; + o_output = 0; + FAPI_TRY(lookup_table_check(iv_target, ALLOWED_VALUES, EFD_CA_PL_MODE, l_key, l_value)); + o_output = l_value; + } + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes DFI Max RD Latency -> DFIMRL_DDRCLK + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode dfimrl_ddrclk(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::DFIMRL_DDRCLK, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 0 -> CAC_DLY_A_0 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_0(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_0, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 1 -> CAC_DLY_A_1 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_1(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_1, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 2 -> CAC_DLY_A_2 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_2(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_2, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 3 -> CAC_DLY_A_3 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_3(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_3, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 4 -> CAC_DLY_A_4 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_4(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_4, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 5 -> CAC_DLY_A_5 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_5(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_5, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 6 -> CAC_DLY_A_6 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_6(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_6, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay A side Group 7 -> CAC_DLY_A_7 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_7(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_A_7, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 0 -> CAC_DLY_B_0 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_0(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_0, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 1 -> CAC_DLY_B_1 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_1(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_1, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 2 -> CAC_DLY_B_2 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_2(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_2, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 3 -> CAC_DLY_B_3 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_3(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_3, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 4 -> CAC_DLY_B_4 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_4(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_4, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 5 -> CAC_DLY_B_5 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_5(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_5, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 6 -> CAC_DLY_B_6 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_6(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_6, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Decodes CAC Delay B side Group 7 -> CAC_DLY_B_7 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_7(uint8_t& o_output) const + { + FAPI_TRY( (reader<fields_t::CAC_DLY_B_7, R>(iv_target, iv_data, o_output)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// /// @brief Decodes PMIC0 SWA Volt -> PMIC0_SWA_SETTING /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H index 4cebb9acb..47f0e5105 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H @@ -250,90 +250,190 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> WR_VREF_DQ_VALUE_START = 2, WR_VREF_DQ_VALUE_LEN = 6, - // Byte 45: ODT WR Map CS Byte1 - ODT_WR_MAP1_BYTE = 45, + // Byte 45: Host RD VREF DQ + RD_VREF_DQ_BYTE = 45, + PHY_VREF_PERCENT_START = 1, + PHY_VREF_PERCENT_LEN = 7, + + // Byte 46: ODT WR Map CS Byte1 + ODT_WR_MAP1_BYTE = 46, ODT_WR_MAP_RANK3_START = 0, ODT_WR_MAP_RANK3_LEN = 4, ODT_WR_MAP_RANK2_START = 4, ODT_WR_MAP_RANK2_LEN = 4, - // Byte 46: ODT WR Map CS Byte0 - ODT_WR_MAP0_BYTE = 46, + // Byte 47: ODT WR Map CS Byte0 + ODT_WR_MAP0_BYTE = 47, ODT_WR_MAP_RANK1_START = 0, ODT_WR_MAP_RANK1_LEN = 4, ODT_WR_MAP_RANK0_START = 4, ODT_WR_MAP_RANK0_LEN = 4, - // Byte 47: ODT RD Map CS Byte1 - ODT_RD_MAP1_BYTE = 47, + // Byte 48: ODT RD Map CS Byte1 + ODT_RD_MAP1_BYTE = 48, ODT_RD_MAP_RANK3_START = 0, ODT_RD_MAP_RANK3_LEN = 4, ODT_RD_MAP_RANK2_START = 4, ODT_RD_MAP_RANK2_LEN = 4, - // Byte 48: ODT RD Map CS Byte0 - ODT_RD_MAP0_BYTE = 48, + // Byte 49: ODT RD Map CS Byte0 + ODT_RD_MAP0_BYTE = 49, ODT_RD_MAP_RANK1_START = 0, ODT_RD_MAP_RANK1_LEN = 4, ODT_RD_MAP_RANK0_START = 4, ODT_RD_MAP_RANK0_LEN = 4, - // Byte 49: Geardown during training - GEARDOWN_DURING_TRAINING_BYTE = 49, + // Byte 50: Geardown during training + GEARDOWN_DURING_TRAINING_BYTE = 50, GEARDOWN_DURING_TRAINING_START = 7, GEARDOWN_DURING_TRAINING_LEN = 1, - // Byte 50: PMIC0 SWA Volt - PMIC0_SWA_BYTE = 50, + // Byte 51: BIST CAL Mode + BIST_CA_LATENCY_MODE_BYTE = 51, + BIST_CA_LATENCY_MODE_START = 4, + BIST_CA_LATENCY_MODE_LEN = 4, + + // Byte 52: BIST CA Parity Latency Mode + BIST_CA_PL_MODE_BYTE = 52, + BIST_CA_PL_MODE_START = 4, + BIST_CA_PL_MODE_LEN = 4, + + // Byte 53: DFI Max RD Latency + DFI_MAX_RD_LATENCY_BYTE = 53, + DFIMRL_DDRCLK_START = 3, + DFIMRL_DDRCLK_LEN = 5, + + // Byte 54: CAC Delay A side Group 0 + CAC_DELAY_A_SIDE_GROUP_0_BYTE = 54, + CAC_DLY_A_0_START = 3, + CAC_DLY_A_0_LEN = 5, + + // Byte 55: CAC Delay A side Group 1 + CAC_DELAY_A_SIDE_GROUP_1_BYTE = 55, + CAC_DLY_A_1_START = 3, + CAC_DLY_A_1_LEN = 5, + + // Byte 56: CAC Delay A side Group 2 + CAC_DELAY_A_SIDE_GROUP_2_BYTE = 56, + CAC_DLY_A_2_START = 3, + CAC_DLY_A_2_LEN = 5, + + // Byte 57: CAC Delay A side Group 3 + CAC_DELAY_A_SIDE_GROUP_3_BYTE = 57, + CAC_DLY_A_3_START = 3, + CAC_DLY_A_3_LEN = 5, + + // Byte 58: CAC Delay A side Group 4 + CAC_DELAY_A_SIDE_GROUP_4_BYTE = 58, + CAC_DLY_A_4_START = 3, + CAC_DLY_A_4_LEN = 5, + + // Byte 59: CAC Delay A side Group 5 + CAC_DELAY_A_SIDE_GROUP_5_BYTE = 59, + CAC_DLY_A_5_START = 3, + CAC_DLY_A_5_LEN = 5, + + // Byte 60: CAC Delay A side Group 6 + CAC_DELAY_A_SIDE_GROUP_6_BYTE = 60, + CAC_DLY_A_6_START = 3, + CAC_DLY_A_6_LEN = 5, + + // Byte 61: CAC Delay A side Group 7 + CAC_DELAY_A_SIDE_GROUP_7_BYTE = 61, + CAC_DLY_A_7_START = 3, + CAC_DLY_A_7_LEN = 5, + + // Byte 62: CAC Delay B side Group 0 + CAC_DELAY_B_SIDE_GROUP_0_BYTE = 62, + CAC_DLY_B_0_START = 3, + CAC_DLY_B_0_LEN = 5, + + // Byte 63: CAC Delay B side Group 1 + CAC_DELAY_B_SIDE_GROUP_1_BYTE = 63, + CAC_DLY_B_1_START = 3, + CAC_DLY_B_1_LEN = 5, + + // Byte 64: CAC Delay B side Group 2 + CAC_DELAY_B_SIDE_GROUP_2_BYTE = 64, + CAC_DLY_B_2_START = 3, + CAC_DLY_B_2_LEN = 5, + + // Byte 65: CAC Delay B side Group 3 + CAC_DELAY_B_SIDE_GROUP_3_BYTE = 65, + CAC_DLY_B_3_START = 3, + CAC_DLY_B_3_LEN = 5, + + // Byte 66: CAC Delay B side Group 4 + CAC_DELAY_B_SIDE_GROUP_4_BYTE = 66, + CAC_DLY_B_4_START = 3, + CAC_DLY_B_4_LEN = 5, + + // Byte 67: CAC Delay B side Group 5 + CAC_DELAY_B_SIDE_GROUP_5_BYTE = 67, + CAC_DLY_B_5_START = 3, + CAC_DLY_B_5_LEN = 5, + + // Byte 68: CAC Delay B side Group 6 + CAC_DELAY_B_SIDE_GROUP_6_BYTE = 68, + CAC_DLY_B_6_START = 3, + CAC_DLY_B_6_LEN = 5, + + // Byte 69: CAC Delay B side Group 7 + CAC_DELAY_B_SIDE_GROUP_7_BYTE = 69, + CAC_DLY_B_7_START = 3, + CAC_DLY_B_7_LEN = 5, + + // Byte 70: PMIC0 SWA Volt + PMIC0_SWA_BYTE = 70, PMIC0_SWA_SETTING_START = 0, PMIC0_SWA_SETTING_LEN = 7, PMIC0_SWA_RANGE_START = 7, PMIC0_SWA_RANGE_LEN = 1, - // Byte 51: PMIC0 SWB Volt - PMIC0_SWB_BYTE = 51, + // Byte 71: PMIC0 SWB Volt + PMIC0_SWB_BYTE = 71, PMIC0_SWB_SETTING_START = 0, PMIC0_SWB_SETTING_LEN = 7, PMIC0_SWB_RANGE_START = 7, PMIC0_SWB_RANGE_LEN = 1, - // Byte 52: PMIC0 SWC Volt - PMIC0_SWC_BYTE = 52, + // Byte 72: PMIC0 SWC Volt + PMIC0_SWC_BYTE = 72, PMIC0_SWC_SETTING_START = 0, PMIC0_SWC_SETTING_LEN = 7, PMIC0_SWC_RANGE_START = 7, PMIC0_SWC_RANGE_LEN = 1, - // Byte 53: PMIC0 SWD Volt - PMIC0_SWD_BYTE = 53, + // Byte 73: PMIC0 SWD Volt + PMIC0_SWD_BYTE = 73, PMIC0_SWD_SETTING_START = 0, PMIC0_SWD_SETTING_LEN = 7, PMIC0_SWD_RANGE_START = 7, PMIC0_SWD_RANGE_LEN = 1, - // Byte 54: PMIC1 SWA Volt - PMIC1_SWA_BYTE = 54, + // Byte 74: PMIC1 SWA Volt + PMIC1_SWA_BYTE = 74, PMIC1_SWA_SETTING_START = 0, PMIC1_SWA_SETTING_LEN = 7, PMIC1_SWA_RANGE_START = 7, PMIC1_SWA_RANGE_LEN = 1, - // Byte 55: PMIC1 SWB Volt - PMIC1_SWB_BYTE = 55, + // Byte 75: PMIC1 SWB Volt + PMIC1_SWB_BYTE = 75, PMIC1_SWB_SETTING_START = 0, PMIC1_SWB_SETTING_LEN = 7, PMIC1_SWB_RANGE_START = 7, PMIC1_SWB_RANGE_LEN = 1, - // Byte 56: PMIC1 SWC Volt - PMIC1_SWC_BYTE = 56, + // Byte 76: PMIC1 SWC Volt + PMIC1_SWC_BYTE = 76, PMIC1_SWC_SETTING_START = 0, PMIC1_SWC_SETTING_LEN = 7, PMIC1_SWC_RANGE_START = 7, PMIC1_SWC_RANGE_LEN = 1, - // Byte 57: PMIC1 SWD Volt - PMIC1_SWD_BYTE = 57, + // Byte 77: PMIC1 SWD Volt + PMIC1_SWD_BYTE = 77, PMIC1_SWD_SETTING_START = 0, PMIC1_SWD_SETTING_LEN = 7, PMIC1_SWD_RANGE_START = 7, @@ -458,54 +558,114 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> static constexpr field_t WR_VREF_DQ_RANGE{WR_VREF_DQ_BYTE, WR_VREF_DQ_RANGE_START, WR_VREF_DQ_RANGE_LEN}; static constexpr field_t WR_VREF_DQ_VALUE{WR_VREF_DQ_BYTE, WR_VREF_DQ_VALUE_START, WR_VREF_DQ_VALUE_LEN}; - // Byte 45: ODT WR Map CS Byte1 + // Byte 45: Host RD VREF DQ + static constexpr field_t PHY_VREF_PERCENT{RD_VREF_DQ_BYTE, PHY_VREF_PERCENT_START, PHY_VREF_PERCENT_LEN}; + + // Byte 46: ODT WR Map CS Byte1 static constexpr field_t ODT_WR_MAP_RANK3{ODT_WR_MAP1_BYTE, ODT_WR_MAP_RANK3_START, ODT_WR_MAP_RANK3_LEN}; static constexpr field_t ODT_WR_MAP_RANK2{ODT_WR_MAP1_BYTE, ODT_WR_MAP_RANK2_START, ODT_WR_MAP_RANK2_LEN}; - // Byte 46: ODT WR Map CS Byte0 + // Byte 47: ODT WR Map CS Byte0 static constexpr field_t ODT_WR_MAP_RANK1{ODT_WR_MAP0_BYTE, ODT_WR_MAP_RANK1_START, ODT_WR_MAP_RANK1_LEN}; static constexpr field_t ODT_WR_MAP_RANK0{ODT_WR_MAP0_BYTE, ODT_WR_MAP_RANK0_START, ODT_WR_MAP_RANK0_LEN}; - // Byte 47: ODT RD Map CS Byte1 + // Byte 48: ODT RD Map CS Byte1 static constexpr field_t ODT_RD_MAP_RANK3{ODT_RD_MAP1_BYTE, ODT_RD_MAP_RANK3_START, ODT_RD_MAP_RANK3_LEN}; static constexpr field_t ODT_RD_MAP_RANK2{ODT_RD_MAP1_BYTE, ODT_RD_MAP_RANK2_START, ODT_RD_MAP_RANK2_LEN}; - // Byte 48: ODT RD Map CS Byte0 + // Byte 49: ODT RD Map CS Byte0 static constexpr field_t ODT_RD_MAP_RANK1{ODT_RD_MAP0_BYTE, ODT_RD_MAP_RANK1_START, ODT_RD_MAP_RANK1_LEN}; static constexpr field_t ODT_RD_MAP_RANK0{ODT_RD_MAP0_BYTE, ODT_RD_MAP_RANK0_START, ODT_RD_MAP_RANK0_LEN}; - // Byte 49: Geardown during training + // Byte 50: Geardown during training static constexpr field_t GEARDOWN_DURING_TRAINING{GEARDOWN_DURING_TRAINING_BYTE, GEARDOWN_DURING_TRAINING_START, GEARDOWN_DURING_TRAINING_LEN}; - // Byte 50: PMIC0 SWA Volt + // Byte 51: BIST CAL Mode + static constexpr field_t BIST_CA_LATENCY_MODE{BIST_CA_LATENCY_MODE_BYTE, BIST_CA_LATENCY_MODE_START, BIST_CA_LATENCY_MODE_LEN}; + + // Byte 52: BIST CA Parity Latency Mode + static constexpr field_t BIST_CA_PL_MODE{BIST_CA_PL_MODE_BYTE, BIST_CA_PL_MODE_START, BIST_CA_PL_MODE_LEN}; + + // Byte 53: DFI Max RD Latency + static constexpr field_t DFIMRL_DDRCLK{DFI_MAX_RD_LATENCY_BYTE, DFIMRL_DDRCLK_START, DFIMRL_DDRCLK_LEN}; + + // Byte 54: CAC Delay A side Group 0 + static constexpr field_t CAC_DLY_A_0{CAC_DELAY_A_SIDE_GROUP_0_BYTE, CAC_DLY_A_0_START, CAC_DLY_A_0_LEN}; + + // Byte 55: CAC Delay A side Group 1 + static constexpr field_t CAC_DLY_A_1{CAC_DELAY_A_SIDE_GROUP_1_BYTE, CAC_DLY_A_1_START, CAC_DLY_A_1_LEN}; + + // Byte 56: CAC Delay A side Group 2 + static constexpr field_t CAC_DLY_A_2{CAC_DELAY_A_SIDE_GROUP_2_BYTE, CAC_DLY_A_2_START, CAC_DLY_A_2_LEN}; + + // Byte 57: CAC Delay A side Group 3 + static constexpr field_t CAC_DLY_A_3{CAC_DELAY_A_SIDE_GROUP_3_BYTE, CAC_DLY_A_3_START, CAC_DLY_A_3_LEN}; + + // Byte 58: CAC Delay A side Group 4 + static constexpr field_t CAC_DLY_A_4{CAC_DELAY_A_SIDE_GROUP_4_BYTE, CAC_DLY_A_4_START, CAC_DLY_A_4_LEN}; + + // Byte 59: CAC Delay A side Group 5 + static constexpr field_t CAC_DLY_A_5{CAC_DELAY_A_SIDE_GROUP_5_BYTE, CAC_DLY_A_5_START, CAC_DLY_A_5_LEN}; + + // Byte 60: CAC Delay A side Group 6 + static constexpr field_t CAC_DLY_A_6{CAC_DELAY_A_SIDE_GROUP_6_BYTE, CAC_DLY_A_6_START, CAC_DLY_A_6_LEN}; + + // Byte 61: CAC Delay A side Group 7 + static constexpr field_t CAC_DLY_A_7{CAC_DELAY_A_SIDE_GROUP_7_BYTE, CAC_DLY_A_7_START, CAC_DLY_A_7_LEN}; + + // Byte 62: CAC Delay B side Group 0 + static constexpr field_t CAC_DLY_B_0{CAC_DELAY_B_SIDE_GROUP_0_BYTE, CAC_DLY_B_0_START, CAC_DLY_B_0_LEN}; + + // Byte 63: CAC Delay B side Group 1 + static constexpr field_t CAC_DLY_B_1{CAC_DELAY_B_SIDE_GROUP_1_BYTE, CAC_DLY_B_1_START, CAC_DLY_B_1_LEN}; + + // Byte 64: CAC Delay B side Group 2 + static constexpr field_t CAC_DLY_B_2{CAC_DELAY_B_SIDE_GROUP_2_BYTE, CAC_DLY_B_2_START, CAC_DLY_B_2_LEN}; + + // Byte 65: CAC Delay B side Group 3 + static constexpr field_t CAC_DLY_B_3{CAC_DELAY_B_SIDE_GROUP_3_BYTE, CAC_DLY_B_3_START, CAC_DLY_B_3_LEN}; + + // Byte 66: CAC Delay B side Group 4 + static constexpr field_t CAC_DLY_B_4{CAC_DELAY_B_SIDE_GROUP_4_BYTE, CAC_DLY_B_4_START, CAC_DLY_B_4_LEN}; + + // Byte 67: CAC Delay B side Group 5 + static constexpr field_t CAC_DLY_B_5{CAC_DELAY_B_SIDE_GROUP_5_BYTE, CAC_DLY_B_5_START, CAC_DLY_B_5_LEN}; + + // Byte 68: CAC Delay B side Group 6 + static constexpr field_t CAC_DLY_B_6{CAC_DELAY_B_SIDE_GROUP_6_BYTE, CAC_DLY_B_6_START, CAC_DLY_B_6_LEN}; + + // Byte 69: CAC Delay B side Group 7 + static constexpr field_t CAC_DLY_B_7{CAC_DELAY_B_SIDE_GROUP_7_BYTE, CAC_DLY_B_7_START, CAC_DLY_B_7_LEN}; + + // Byte 70: PMIC0 SWA Volt static constexpr field_t PMIC0_SWA_SETTING{PMIC0_SWA_BYTE, PMIC0_SWA_SETTING_START, PMIC0_SWA_SETTING_LEN}; static constexpr field_t PMIC0_SWA_RANGE{PMIC0_SWA_BYTE, PMIC0_SWA_RANGE_START, PMIC0_SWA_RANGE_LEN}; - // Byte 51: PMIC0 SWB Volt + // Byte 71: PMIC0 SWB Volt static constexpr field_t PMIC0_SWB_SETTING{PMIC0_SWB_BYTE, PMIC0_SWB_SETTING_START, PMIC0_SWB_SETTING_LEN}; static constexpr field_t PMIC0_SWB_RANGE{PMIC0_SWB_BYTE, PMIC0_SWB_RANGE_START, PMIC0_SWB_RANGE_LEN}; - // Byte 52: PMIC0 SWC Volt + // Byte 72: PMIC0 SWC Volt static constexpr field_t PMIC0_SWC_SETTING{PMIC0_SWC_BYTE, PMIC0_SWC_SETTING_START, PMIC0_SWC_SETTING_LEN}; static constexpr field_t PMIC0_SWC_RANGE{PMIC0_SWC_BYTE, PMIC0_SWC_RANGE_START, PMIC0_SWC_RANGE_LEN}; - // Byte 53: PMIC0 SWD Volt + // Byte 73: PMIC0 SWD Volt static constexpr field_t PMIC0_SWD_SETTING{PMIC0_SWD_BYTE, PMIC0_SWD_SETTING_START, PMIC0_SWD_SETTING_LEN}; static constexpr field_t PMIC0_SWD_RANGE{PMIC0_SWD_BYTE, PMIC0_SWD_RANGE_START, PMIC0_SWD_RANGE_LEN}; - // Byte 54: PMIC1 SWA Volt + // Byte 74: PMIC1 SWA Volt static constexpr field_t PMIC1_SWA_SETTING{PMIC1_SWA_BYTE, PMIC1_SWA_SETTING_START, PMIC1_SWA_SETTING_LEN}; static constexpr field_t PMIC1_SWA_RANGE{PMIC1_SWA_BYTE, PMIC1_SWA_RANGE_START, PMIC1_SWA_RANGE_LEN}; - // Byte 55: PMIC1 SWB Volt + // Byte 75: PMIC1 SWB Volt static constexpr field_t PMIC1_SWB_SETTING{PMIC1_SWB_BYTE, PMIC1_SWB_SETTING_START, PMIC1_SWB_SETTING_LEN}; static constexpr field_t PMIC1_SWB_RANGE{PMIC1_SWB_BYTE, PMIC1_SWB_RANGE_START, PMIC1_SWB_RANGE_LEN}; - // Byte 56: PMIC1 SWC Volt + // Byte 76: PMIC1 SWC Volt static constexpr field_t PMIC1_SWC_SETTING{PMIC1_SWC_BYTE, PMIC1_SWC_SETTING_START, PMIC1_SWC_SETTING_LEN}; static constexpr field_t PMIC1_SWC_RANGE{PMIC1_SWC_BYTE, PMIC1_SWC_RANGE_START, PMIC1_SWC_RANGE_LEN}; - // Byte 57: PMIC1 SWD Volt + // Byte 77: PMIC1 SWD Volt static constexpr field_t PMIC1_SWD_SETTING{PMIC1_SWD_BYTE, PMIC1_SWD_SETTING_START, PMIC1_SWD_SETTING_LEN}; static constexpr field_t PMIC1_SWD_RANGE{PMIC1_SWD_BYTE, PMIC1_SWD_RANGE_START, PMIC1_SWD_RANGE_LEN}; }; diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H index b292d4180..215893dce 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H @@ -780,6 +780,25 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS /// @class readerTraits /// @brief trait structure to hold static SPD information /// @tparam R the revision of the SPD field +/// @note PHY_VREF_PERCENT field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::PHY_VREF_PERCENT, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x7f; + static constexpr const char* FIELD_STR = "Host RD VREF DQ"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field /// @note WR_VREF_DQ_VALUE field specialization /// @note valid for all revs /// @@ -966,6 +985,367 @@ class readerTraits template <typename T> using COMPARISON_OP = std::less_equal<T>; }; +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note BIST_CA_LATENCY_MODE field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits + < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::BIST_CA_LATENCY_MODE, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x08; + static constexpr const char* FIELD_STR = "BIST Command address Latency Mode"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note BIST_CA_PL_MODE field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::BIST_CA_PL_MODE, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x08; + static constexpr const char* FIELD_STR = "BIST CA Parity Latency Mode"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note DFIMRL_DDRCLK field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::DFIMRL_DDRCLK, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x0f; + static constexpr const char* FIELD_STR = "DFI Max RD Latency"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_0 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_0, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group 0"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_1 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_1, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group 1"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_2 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_2, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group 2"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_3 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_3, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group ."; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_4 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_4, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group 4"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_5 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_5, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group 5"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_6 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_6, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group 6"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_A_7 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_A_7, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay A side Group 7"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_0 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_0, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 0"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_1 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_1, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 1"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_2 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_2, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 2"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_3 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_3, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 3"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_4 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_4, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 4"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_5 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_5, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 5"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_6 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_6, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 6"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// +/// @class readerTraits +/// @brief trait structure to hold static SPD information +/// @tparam R the revision of the SPD field +/// @note CAC_DLY_B_7 field specialization +/// @note valid for all revs +/// +template< mss::spd::rev R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::CAC_DLY_B_7, R > +{ + public: + + static constexpr size_t COMPARISON_VAL = 0x1f; + static constexpr const char* FIELD_STR = "CAC Delay B side Group 7"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; /// /// @class readerTraits diff --git a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H index 6ac30ab0f..acd8f0e1c 100644 --- a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H +++ b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H @@ -504,6 +504,17 @@ class base_decoder } /// + /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_VALUE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay @@ -614,6 +625,215 @@ class base_decoder } /// + /// @brief Decodes BIST CAL Mode -> BIST_CA_LATENCY_MODE + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode bist_ca_latency_mode(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes BIST CA Parity Latency Mode -> BIST_CA_PL_MODE + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode bist_ca_pl_mode(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes DFI Max RD Latency -> DFIMRL_DDRCLK + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode dfimrl_ddrclk(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 0 -> CAC_DLY_A_0 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_0(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 1 -> CAC_DLY_A_1 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_1(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 2 -> CAC_DLY_A_2 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_2(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 3 -> CAC_DLY_A_3 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_3(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 4 -> CAC_DLY_A_4 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_4(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 5 -> CAC_DLY_A_5 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_5(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 6 -> CAC_DLY_A_6 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_6(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay A side Group 7 -> CAC_DLY_A_7 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_a_side_group_7(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 0 -> CAC_DLY_B_0 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_0(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 1 -> CAC_DLY_B_1 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_1(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 2 -> CAC_DLY_B_2 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_2(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 3 -> CAC_DLY_B_3 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_3(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 4 -> CAC_DLY_B_4 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_4(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 5 -> CAC_DLY_B_5 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_5(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 6 -> CAC_DLY_B_6 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_6(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes CAC Delay B side Group 7 -> CAC_DLY_B_7 + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// + virtual fapi2::ReturnCode cac_delay_b_side_group_7(uint8_t& o_output) const + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// /// @brief Decodes PMIC0 SWA Volt -> PMIC0_SWA_SETTING /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay diff --git a/src/import/generic/memory/lib/utils/find.H b/src/import/generic/memory/lib/utils/find.H index bfae8a1c5..ee2a5b8c1 100644 --- a/src/import/generic/memory/lib/utils/find.H +++ b/src/import/generic/memory/lib/utils/find.H @@ -38,6 +38,8 @@ #include <fapi2.H> #include <vector> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> namespace mss { @@ -460,6 +462,40 @@ bool find_value_from_key( const std::pair<T, OT> (&i_array)[N], return false; } +/// +/// @brief Mapping boilerplate check +/// @tparam T FAPI2 target type +/// @tparam IT map key type +/// @tparam OT map value type +/// @param[in] i_target the FAPI target +/// @param[in] i_map SPD to attribute data mapping +/// @param[in] i_ffdc_code FFDC function code +/// @param[in] i_key Key to query map +/// @param[out] o_output value from key +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< fapi2::TargetType T, typename IT, typename OT > +inline fapi2::ReturnCode lookup_table_check(const fapi2::Target<T>& i_target, + const std::vector<std::pair<IT, OT>>& i_map, + const generic_ffdc_codes i_ffdc_code, + const IT i_key, + OT& o_output) +{ + const bool l_is_val_found = mss::find_value_from_key(i_map, i_key, o_output); + + FAPI_ASSERT( l_is_val_found, + fapi2::MSS_LOOKUP_FAILED() + .set_KEY(i_key) + .set_DATA(o_output) + .set_FUNCTION(i_ffdc_code) + .set_TARGET(i_target), + "Failed to find a mapped value for %d on %s", + i_key, + mss::spd::c_str(i_target) ); +fapi_try_exit: + return fapi2::current_err; +} + }// mss #endif diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 0599a01c7..b77cbcd47 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -215,11 +215,17 @@ enum generic_ffdc_codes SET_PRIM_BUS_WIDTH = 0x1069, SET_PRIM_DIE_COUNT = 0x1070, SET_DRAM_DENSITY = 0x1071, + SET_SI_RD_VREF_DQ = 0x1075, + SET_CAC_DELAY_A = 0x1076, + SET_CAC_DELAY_B = 0x1077, + EFD_CA_LATENCY_MODE = 0x1080, + EFD_CA_PL_MODE = 0x1081, + // Power thermal functions POWER_LIMIT = 0x1072, - SLOPE = 1073, - INTERCEPT = 1074, + SLOPE = 0x1073, + INTERCEPT = 0x1074, }; /// |
