diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C | 13 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C | 10 |
2 files changed, 21 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C index 1f5942dfc..a864533fb 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C @@ -81,6 +81,8 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0 FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2)); uint64_t l_def_MC_EPSILON_CFG_T2 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 + literal_6) / literal_4); uint64_t l_def_ENABLE_MCBUSY = literal_1; + fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT1, l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM)); uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1; uint64_t l_def_MCICFG_REPLAY_DELAY = literal_1; fapi2::ATTR_MC_SYNC_MODE_Type l_TGT3_ATTR_MC_SYNC_MODE; @@ -273,6 +275,17 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0 l_scom_buffer.insert<27, 4, 60, uint64_t>(literal_0 ); } + if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF)) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON = 0x1; + l_scom_buffer.insert<43, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON ); + } + else if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON)) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF = 0x0; + l_scom_buffer.insert<43, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x501082bull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C index 132b4992a..9981b5fe4 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C @@ -67,7 +67,8 @@ fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0, uint64_t l_def_MCA_FREQ = l_TGT1_ATTR_FREQ_MCA_MHZ; uint64_t l_def_MN_FREQ_RATIO = ((literal_1000 * l_def_MCA_FREQ) / l_TGT1_ATTR_FREQ_PB_MHZ); uint64_t l_def_ENABLE_DYNAMIC_64_128B_READS = literal_0; - uint64_t l_def_ENABLE_ECRESP = literal_1; + fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT1, l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM)); uint64_t l_def_ENABLE_AMO_CACHING = literal_1; uint64_t l_def_ENABLE_HWFM = literal_1; uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1; @@ -199,7 +200,12 @@ fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0, l_scom_buffer.insert<9, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_64_128B_READ_OFF ); } - if ((l_def_ENABLE_ECRESP == literal_1)) + if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF)) + { + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF = 0x0; + l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF ); + } + else if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON)) { constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_ON = 0x1; l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_ON ); |
