diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/HBconfig | 5 | ||||
-rwxr-xr-x | src/build/simics/combined.simics | 12 | ||||
-rwxr-xr-x | src/build/simics/standalone.simics | 12 | ||||
-rw-r--r-- | src/include/arch/ppc.H | 15 | ||||
-rw-r--r-- | src/include/kernel/ppcconsts.S | 1 | ||||
-rw-r--r-- | src/include/kernel/ptmgr.H | 60 | ||||
-rw-r--r-- | src/include/kernel/vmmmgr.H | 13 | ||||
-rw-r--r-- | src/kernel/ptmgr.C | 2 | ||||
-rw-r--r-- | src/kernel/vmmmgr.C | 28 |
9 files changed, 114 insertions, 34 deletions
diff --git a/src/HBconfig b/src/HBconfig index 11ff10df5..e234dc1e9 100644 --- a/src/HBconfig +++ b/src/HBconfig @@ -13,3 +13,8 @@ config P9_SYSTEM default y help Compile with P9 configurations + +config P9_PAGE_TABLE + default y + help + Use the P9 version of the page table setup diff --git a/src/build/simics/combined.simics b/src/build/simics/combined.simics index 9d87c493c..72597f973 100755 --- a/src/build/simics/combined.simics +++ b/src/build/simics/combined.simics @@ -21,18 +21,6 @@ try { } } except { echo "ERROR: Failed to load tools in combined.simics." } -# Workaround to set the sim_ctrl1 reg to enable the -# old HPT SDR1 translation, not the new PTCR translation -# SIM_CTRL1_P9_SDR1 0x0010000000000000 -# @todo-RTC:126640 Remove with P9 page table support -system_cmp0.cpu0_0_00_0.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_1.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_2.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_3.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_0.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_1.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_2.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_3.write-reg sim_ctrl1 0x4230000000000000 system_cmp0.cpu0_0_00_0.disable diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics index 9a151d02a..c31435a8c 100755 --- a/src/build/simics/standalone.simics +++ b/src/build/simics/standalone.simics @@ -41,18 +41,6 @@ foreach $cc in (get-object-list p9_proc) { ($cc).proc_chip.invoke parallel_store STARTSBEREGS 0 "80000000" 32 } -# Workaround to set the sim_ctrl1 reg to enable the -# old HPT SDR1 translation, not the new PTCR translation -# SIM_CTRL1_P9_SDR1 0x0010000000000000 -# @todo-RTC:126640 Remove with P9 page table support -system_cmp0.cpu0_0_00_0.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_1.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_2.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_3.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_0.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_1.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_2.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_3.write-reg sim_ctrl1 0x4230000000000000 system_cmp0.cpu0_0_00_0.enable ################################### diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H index 54c9e8774..8402f743c 100644 --- a/src/include/arch/ppc.H +++ b/src/include/arch/ppc.H @@ -273,6 +273,21 @@ inline uint64_t getHRMOR() } ALWAYS_INLINE +inline uint64_t getPTCR() +{ + register uint64_t ptcr = 0; + asm volatile("mfspr %0, 464" : "=r" (ptcr)); + return ptcr; +} + +ALWAYS_INLINE +inline void setPTCR(uint64_t _ptcr) +{ + register uint64_t ptcr = _ptcr; + asm volatile("mtspr 464, %0; isync" :: "r" (ptcr)); +} + +ALWAYS_INLINE inline void setThreadPriorityLow() { asm volatile("or 1,1,1"); diff --git a/src/include/kernel/ppcconsts.S b/src/include/kernel/ppcconsts.S index 6da85a9b2..404fbc34d 100644 --- a/src/include/kernel/ppcconsts.S +++ b/src/include/kernel/ppcconsts.S @@ -164,6 +164,7 @@ .set HSRR0,314 .set HSRR1,315 .set HMER,336 + .set PTCR,464 .set HID0,1008 .set PIR, 1023 diff --git a/src/include/kernel/ptmgr.H b/src/include/kernel/ptmgr.H index 9837a2dea..d6e6be151 100644 --- a/src/include/kernel/ptmgr.H +++ b/src/include/kernel/ptmgr.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -26,6 +28,7 @@ #include <stdint.h> #include <util/lockfree/stack.H> #include <kernel/vmmmgr.H> +#include <config.h> /** * @class PageTableManager @@ -191,7 +194,52 @@ class PageTableManager */ char* ivTABLE; +#ifdef CONFIG_P9_PAGE_TABLE + /** + * Represents a single entry in the page table + */ + struct PageTableEntry + { + /** + * Dword0 + */ + union { + struct { /**< Dword0 Attributes */ + uint64_t rsv0:12; /**< 0:11 Reserved */ + uint64_t AVA:45; /**< 12:56 Abbrev VA, VA w/o bottom bits */ + uint64_t SW:1; /**< 57 =SW[0] - Reserved */ + uint64_t R2:1; /**< 58 =SW[1] - Shadow R bit */ + uint64_t LRU:2; /**< 59:60 =SW[2:3] Used for LRU algorithm */ + uint64_t L:1; /**< 61 Virtual page size */ + uint64_t H:1; /**< 62 Hash function identifier */ + uint64_t V:1; /**< 63 Entry valid */ + }; + uint64_t dword0; /**< Full Dword0 */ + }; + /** + * Dword1 + */ + union { + struct { /**< Dword1 Attributes */ + uint64_t pp0:1; /**< 0 Page Protection bit 0 */ + uint64_t TS:1; /**< 1 Tag Set bit */ + uint64_t key0_1:2; /**< 2:3 KEY bits 0:1 <unused> */ + uint64_t B:2; /**< 4:5 Segment Size */ + uint64_t rsv1:1; /**< 6 Reserved */ + uint64_t PN:45; /**< 7:51 Abbrev RPN + Large Page Size */ + uint64_t key2_4:3; /**< 52:54 KEY bits 2:4 <unused> */ + uint64_t R:1; /**< 55 Reference bit */ + uint64_t C:1; /**< 56 Change bit */ + uint64_t WIMG:4; /**< 57:60 Storage control bits */ + uint64_t N:1; /**< 61 No-execute page (N==1) */ + uint64_t pp1_2:2; /**< 62:63 Page Protection bits 1:2 */ + }; + uint64_t dword1; /**< Full Dword1 */ + }; + } PACKED; + enum { PTE_AVA_MASK = 0x1FFFFFFFFFFF }; +#else /** * Represents a single entry in the page table */ @@ -203,10 +251,10 @@ class PageTableManager union { struct { /**< Dword0 Attributes */ uint64_t B:2; /**< 0:1 Segment Size */ - uint64_t AVA:55; /**< 2:56 Abbreviated Virtual Address = VA w/o bottom 23 bits */ - uint64_t SW:1; /**< 57 =SW[] - Reserved */ + uint64_t AVA:55; /**< 2:56 Abbrev VA, VA w/o bottom 23 bits */ + uint64_t SW:1; /**< 57 =SW[0] - Reserved */ uint64_t R2:1; /**< 58 =SW[1] - Shadow R bit */ - uint64_t LRU:2; /**< 59:60 =SW[2:3] - Used for LRU algorithm */ + uint64_t LRU:2; /**< 59:60 =SW[2:3] Used for LRU algorithm */ uint64_t L:1; /**< 61 Virtual page size */ uint64_t H:1; /**< 62 Hash function identifier */ uint64_t V:1; /**< 63 Entry valid */ @@ -222,7 +270,7 @@ class PageTableManager uint64_t pp0:1; /**< 0 Page Protection bit 0 */ uint64_t rsv:1; /**< 1 Reserved */ uint64_t key0_1:2; /**< 2:3 KEY bits 0:1 <unused> */ - uint64_t PN:48; /**< 4:52 Abbreviated Real Page Number + Large page size selector */ + uint64_t PN:48; /**< 4:52 Abbrev RPN + Large Page Size */ uint64_t key2_4:3; /**< 53:54 KEY bits 2:4 <unused> */ uint64_t R:1; /**< 55 Reference bit */ uint64_t C:1; /**< 56 Change bit */ @@ -233,6 +281,8 @@ class PageTableManager uint64_t dword1; /**< Full Dword1 */ }; } PACKED; + enum { PTE_AVA_MASK = 0x7FFFFFFFFFFFFF }; +#endif /** * Internal Constants diff --git a/src/include/kernel/vmmmgr.H b/src/include/kernel/vmmmgr.H index 18897a6b5..9597aba57 100644 --- a/src/include/kernel/vmmmgr.H +++ b/src/include/kernel/vmmmgr.H @@ -58,8 +58,7 @@ class VmmManager /** We need to reserve a hole in heap memory for the page table, * etc. Use these constants to define the hole. */ FIRST_RESERVED_PAGE = INITIAL_PT_OFFSET, - END_RESERVED_PAGE = INITIAL_PT_OFFSET + - PTSIZE + MBOX_DMA_SIZE, + END_RESERVED_PAGE = INITIAL_PT_OFFSET + PTSIZE + MBOX_DMA_SIZE, // Tells processor to ignore HRMOR FORCE_PHYS_ADDR = 0x8000000000000000, @@ -226,9 +225,17 @@ class VmmManager static Spinlock* getLock(); private: + + // Partition Table + // 4K-aligned, each entry is 2 double words + // We only need one entry in the table + // So just use a 4K-aligned variable + static uint64_t g_patb[2] __attribute__ ((aligned (4096))); + Spinlock lock; void initPTEs(); + void initPartitionTable(); void initSDR1(); bool _pteMiss(task_t*, uint64_t, bool); @@ -236,7 +243,7 @@ class VmmManager /** See findPhysicalAddress */ uint64_t _findPhysicalAddress(uint64_t i_vaddr); - /* See mmSetPermission */ + /** See mmSetPermission */ int _mmSetPermission(void* i_va,uint64_t i_size, uint64_t i_access_type); /** See castOutPages */ diff --git a/src/kernel/ptmgr.C b/src/kernel/ptmgr.C index 959e0c7dd..85dc0e13f 100644 --- a/src/kernel/ptmgr.C +++ b/src/kernel/ptmgr.C @@ -345,7 +345,7 @@ void PageTableManager::invalidatePT( void ) uint64_t num_ptes = getSize() / sizeof(PageTableEntry); for( uint64_t x = 0; x < num_ptes; x++ ) { - pte->AVA = 0xFFFFFFFFFFFF; + pte->AVA = (uint64_t)PTE_AVA_MASK; pte->V = 0; pte++; } diff --git a/src/kernel/vmmmgr.C b/src/kernel/vmmmgr.C index 48675c398..8a55f56c7 100644 --- a/src/kernel/vmmmgr.C +++ b/src/kernel/vmmmgr.C @@ -32,9 +32,11 @@ #include <kernel/basesegment.H> #include <kernel/stacksegment.H> #include <kernel/devicesegment.H> +#include <config.h> extern void* data_load_address; +uint64_t VmmManager::g_patb[2]; VmmManager::VmmManager() : lock() { @@ -56,8 +58,12 @@ void VmmManager::init() SegmentManager::initSLB(); v.initPTEs(); - v.initSDR1(); +#ifdef CONFIG_P9_PAGE_TABLE + v.initPartitionTable(); +#else + v.initSDR1(); +#endif }; void VmmManager::init_slb() @@ -65,7 +71,11 @@ void VmmManager::init_slb() VmmManager& v = Singleton<VmmManager>::instance(); SegmentManager::initSLB(); +#ifdef CONFIG_P9_PAGE_TABLE + v.initPartitionTable(); +#else v.initSDR1(); +#endif } bool VmmManager::pteMiss(task_t* t, uint64_t effAddr, bool store) @@ -109,6 +119,22 @@ void VmmManager::initPTEs() // handler will add as-needed. } +void VmmManager::initPartitionTable() +{ + // Use SLB, not In-Memory Segment Tables (Process Table) + // Set LPCR[41] (UPRT) = 0 + setLPCR(getLPCR() & (~0x0000000000400000)); + + // Set the first partition table entry (PATE) + // HTABORG, HTABSIZE = 0 (11 bits, 256k table) + g_patb[0] = HTABORG(); + g_patb[1] = 0x0; + + // Init the PTCR reg + // PATB, PATS = 0 (4k table) + setPTCR( reinterpret_cast<uint64_t>(g_patb) ); +} + void VmmManager::initSDR1() { // HTABORG, HTABSIZE = 0 (11 bits, 256k table) |