diff options
Diffstat (limited to 'src')
6 files changed, 233 insertions, 60 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index cd8908218..8811b10e0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -94,7 +94,7 @@ const uint8_t DOORBELLS_COUNT = 4; // Reset function /// /// @brief Stop the CMEs and clear the CME FIRs, PPM Errors and their masks -/// for all functional and enabled EX chiplets +// for all functional and enabled EX chiplets /// /// @param[in] i_target Proc Chip target /// @param[in] i_cmeFirMask Mask value for CME FIR @@ -217,7 +217,7 @@ fapi2::ReturnCode pm_corequad_init( FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to reset CME Flags"); - auto l_exChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EX> + auto l_exChiplets = l_quad_chplt.getChildren<fapi2::TARGET_TYPE_EX> (fapi2::TARGET_STATE_FUNCTIONAL); // For each functional EX chiplet @@ -260,7 +260,7 @@ fapi2::ReturnCode pm_corequad_init( l_firMask), "ERROR: Failed to get local FIR Mask"); l_data64.flush<0>().insertFromRight<0, 32>(l_firMask); - l_address = EX_CME_SCOM_LFIRMASK_OR; + l_address = EX_CME_SCOM_LFIRMASK; FAPI_TRY(fapi2::putScom(l_ex_chplt, l_address, l_data64), "ERROR: Failed to restore the CME Local FIR"); @@ -415,7 +415,7 @@ fapi2::ReturnCode pm_corequad_reset( // Write parameter provided value to CME FIR MASK FAPI_INF(" Write Local CME FIR MASK "); l_data64.flush<0>().insertFromRight<0, 32>(i_cmeFirMask); - l_address = EX_CME_SCOM_LFIRMASK_OR; + l_address = EX_CME_SCOM_LFIRMASK; FAPI_TRY(fapi2::putScom(l_ex_chplt, l_address, l_data64), "ERROR: Failed to clear the Local CME FIR Mask"); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C index b556495b2..12e2f76eb 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C @@ -24,22 +24,35 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_pm_init.C -/// @brief Wrapper that calls underlying HWPs to perform a Power Management -/// init function when needing to initialize the OCC complex. +/// @brief Wrapper that initializes or resets the OCC complex. /// // *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> // *HWP HWP Backup Owner : // *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> // *HWP Team : PM -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : HS /// /// High-level procedure flow: /// /// @verbatim -/// Invoke the sub-functions to initialize the OCC (GPEs, FIRs, PPM, PPC405) -/// for the first time during boot. +/// +/// PM_INIT +/// Initialize Cores and Quads +/// Initialize OCB channels +/// Initialize PSS +/// Initialize PBA +/// Mask CME FIRs and Core-Quad Errors +/// Initialize Stop GPE +/// Initialize Pstate GPE +/// Start OCC PPC405 +/// Clear off pending Special Wakeup requests on all configured EX chiplets +/// +/// PM_RESET +/// Invoke "p9_pm_reset()" to reset the PM OCC complex (Cores, Quads, CMEs, +/// OCB channels, PBA bus, PSS, PPC405 and GPEs) +/// /// @endverbatim /// @@ -49,16 +62,28 @@ #include <p9_pm_init.H> // ----------------------------------------------------------------------------- -// Constant definitions +// Function prototypes // ----------------------------------------------------------------------------- -// ----------------------------------------------------------------------------- -// Global variables -// ----------------------------------------------------------------------------- +/// +/// @brief Call underlying unit procedures to initialize the PM complex. +/// +/// @param[in] i_target Chip target +/// +/// @return FAPI2_RC_SUCCESS on success, else error code. +/// +fapi2::ReturnCode pm_init( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); -// ----------------------------------------------------------------------------- -// Function prototypes -// ----------------------------------------------------------------------------- +/// +/// @brief Clears OCC special wake-up on all configured EX chiplets +/// +/// @param[in] i_target Chip target +/// +/// @return FAPI2_RC_SUCCESS on success, else error code. +/// +fapi2::ReturnCode clear_occ_special_wakeups( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); // ----------------------------------------------------------------------------- // Function definitions @@ -66,17 +91,23 @@ fapi2::ReturnCode p9_pm_init( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - p9pm::PM_FLOW_MODE i_mode) + const p9pm::PM_FLOW_MODE i_mode) { FAPI_INF("Entering p9_pm_init ..."); + fapi2::ReturnCode l_rc; + if (i_mode == p9pm::PM_INIT) { FAPI_DBG("Initialize the OCC Complex."); + FAPI_TRY(pm_init(i_target), + "ERROR: Failed to initialize OCC Complex"); } else if (i_mode == p9pm::PM_RESET) { FAPI_DBG("Reset the OCC Complex."); + FAPI_EXEC_HWP(l_rc, p9_pm_reset, i_target); + FAPI_TRY(l_rc, "ERROR: Failed to reset OCC complex"); } else { @@ -89,3 +120,137 @@ fapi_try_exit: FAPI_INF("Exiting p9_pm_init..."); return fapi2::current_err; } + +fapi2::ReturnCode pm_init( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + FAPI_INF("Entering pm_init..."); + + fapi2::ReturnCode l_rc; + + // ************************************************************************ + // Initialize Cores and Quads + // ************************************************************************ + FAPI_DBG("Executing p9_pm_corequad_init to initialize cores & quads"); + FAPI_EXEC_HWP(l_rc, p9_pm_corequad_init, + i_target, + p9pm::PM_INIT, + 0,//CME FIR MASK for reset + 0,//Core Error Mask for reset + 0 //Quad Error Mask for reset + ); + FAPI_TRY(l_rc, "ERROR: Failed to initialize cores & quads"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After cores & quads init")); + + // ************************************************************************ + // Issue init to OCB + // ************************************************************************ + FAPI_DBG("Executing p9_pm_ocb_init to initialize OCB channels"); + FAPI_EXEC_HWP(l_rc, p9_pm_ocb_init, + i_target, + p9pm::PM_INIT,// Channel setup type + p9ocb::OCB_CHAN1,// Channel + p9ocb:: OCB_TYPE_NULL,// Channel type + 0,// Channel base address + 0,// Push/Pull queue length + p9ocb::OCB_Q_OUFLOW_NULL,// Channel flow control + p9ocb::OCB_Q_ITPTYPE_NULL// Channel interrupt control + ); + FAPI_TRY(l_rc, + "ERROR: Failed to initialize channel 1"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After OCB channels init")); + + // ************************************************************************ + // Initializes P2S and HWC logic + // ************************************************************************ + FAPI_DBG("Executing p9_pm_pss_init to initialize P2S and HWC logic"); + FAPI_EXEC_HWP(l_rc, p9_pm_pss_init, i_target, p9pm::PM_INIT); + FAPI_TRY(l_rc, "ERROR: Failed to initialize PSS & HWC"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PSS & HWC init")); + + // ************************************************************************ + // Initializes PBA + // Note: This voids the channel used by the GPEs + // ************************************************************************ + FAPI_DBG("Executing p9_pm_pba_init to initialize PBA"); + FAPI_EXEC_HWP(l_rc, p9_pm_pba_init, i_target, p9pm::PM_INIT); + FAPI_TRY(l_rc, "ERROR: Failed to initialize PBA BUS"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PBA bus init")); + + // ************************************************************************ + // Mask the FIRs as errors can occur in what follows + // ************************************************************************ + FAPI_DBG("Executing p9_pm_firinit to mask errors/FIRs"); + FAPI_EXEC_HWP(l_rc, p9_pm_firinit, i_target, p9pm::PM_INIT); + FAPI_TRY(l_rc, "ERROR: Failed to mask OCC,PBA & CME FIRs/Errors."); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After masking FIRs and Errors")); + + // ************************************************************************ + // Initialize the STOP GPE Engine + // ************************************************************************ + FAPI_DBG("Executing p9_pm_stop_gpe_init to initialize SGPE"); + FAPI_EXEC_HWP(l_rc, p9_pm_stop_gpe_init, i_target, p9pm::PM_INIT); + FAPI_TRY(l_rc, "ERROR: Failed to initialize SGPE"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After SGPE initialization")); + + // ************************************************************************ + // Switch off OCC initiated special wakeup on EX to allowSTOP functionality + // ************************************************************************ + FAPI_DBG("Clear off the wakeup"); + FAPI_TRY(clear_occ_special_wakeups(i_target), + "ERROR: Failed to clear off the wakeup"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "EX targets off special wakeup")); + + // ************************************************************************ + // Initialize the PSTATE GPE Engine + // ************************************************************************ + /* TODO: RTC 157096: Enable pstate GPE initialization in PM_INIT phase + FAPI_DBG("Executing p9_pm_pstate_gpe_init to initialize PGPE"); + FAPI_EXEC_HWP(l_rc, p9_pm_pstate_gpe_init, i_target, p9pm::PM_INIT); + FAPI_TRY(l_rc, "ERROR: Failed to initialize PGPE"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PGPE initialization")); + */ + + // ************************************************************************ + // Start OCC PPC405 + // ************************************************************************ + FAPI_DBG("Executing p9_pm_occ_control to start OCC PPC405"); + FAPI_EXEC_HWP(l_rc, p9_pm_occ_control, i_target, + p9occ_ctrl::PPC405_START,// Operation on PPC405 + p9occ_ctrl::PPC405_BOOT_NULL // PPC405 boot location + ); + FAPI_TRY(l_rc, "ERROR: Failed to initialize OCC PPC405"); + FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After OCC PPC405 init")); + +fapi_try_exit: + + return fapi2::current_err; + +} + +fapi2::ReturnCode clear_occ_special_wakeups( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + FAPI_INF("Entering clear_occ_special_wakeups..."); + fapi2::buffer<uint64_t> l_data64; + + auto l_exChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EX> + (fapi2::TARGET_STATE_FUNCTIONAL); + + FAPI_DBG("No. of functional EX chiplets: %u ", l_exChiplets.size()); + + // Iterate through the EX chiplets + for (auto l_ex_chplt : l_exChiplets) + { + FAPI_DBG("Clear OCC special wakeup on ex chiplet 0x%08X", l_ex_chplt); + FAPI_TRY(fapi2::getScom(i_target, EX_PPM_SPWKUP_OCC, l_data64), + "ERROR: Failed to read OCC Spl wkup on EX 0x%08X", l_ex_chplt); + l_data64.clearBit<0>(); + FAPI_TRY(fapi2::putScom(i_target, EX_PPM_SPWKUP_OCC, l_data64), + "ERROR: Failed to clear OCC Spl wkup on EX 0x%08X", l_ex_chplt); + } + +fapi_try_exit: + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H index b2ee859f0..4757fbe64 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H @@ -24,28 +24,33 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_pm_init.H -/// @brief Wrapper that calls underlying HWPs to perform a Power Management -/// Init function when needing to initialize the OCC complex. +/// @brief Wrapper that initializes or resets the OCC complex. /// // *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> // *HWP HWP Backup Owner : // *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> // *HWP Team : PM -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : HS #ifndef _P9_PM_INIT_H #define _P9_PM_INIT_H // ----------------------------------------------------------------------------- -// Constant definitions -// ----------------------------------------------------------------------------- - -// ----------------------------------------------------------------------------- // Includes // ----------------------------------------------------------------------------- -#include <p9_pm.H> #include <fapi2.H> +#include <p9_pm.H> +#include <p9_pm_utils.H> +#include <p9_pm_corequad_init.H> +#include <p9_pm_ocb_init.H> +#include <p9_pm_pss_init.H> +#include <p9_pm_pba_init.H> +#include <p9_pm_firinit.H> +#include <p9_pm_stop_gpe_init.H> +#include <p9_pm_occ_control.H> +#include <p9_pm_reset.H> + // Function pointer defintion typedef fapi2::ReturnCode (*p9_pm_init_FP_t) ( @@ -56,12 +61,10 @@ extern "C" { //------------------------------------------------------------------------------ /// -/// @brief Call underlying unit procedures to perform readiness for -/// initialization of PM complex. +/// @brief Wrapper that initializes or resets the OCC complex. /// -/// @param[in] i_target Primary Chip target which will be passed -/// to all the procedures -/// @param[in] i_mode (PM_INIT / PM_RESET) +/// @param[in] i_target Chip target +/// @param[in] i_mode Mode of operation (PM_INIT/ PM_RESET) /// /// @return FAPI2_RC_SUCCESS on success, else error code. /// diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.mk index 347a6c9eb..2add8c512 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.mk @@ -23,4 +23,7 @@ # # IBM_PROLOG_END_TAG PROCEDURE=p9_pm_init +libp9_pm_init_DEPLIBS += p9_pm_utils p9_pm_corequad_init p9_pm_ocb_init p9_pm_pss_init p9_pm_pba_init p9_pm_firinit p9_pm_stop_gpe_init p9_pm_occ_control p9_pm_reset +$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib) +$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/common/pmlib/include/registers) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C index 9a51974fc..437a3e9cc 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C @@ -224,7 +224,7 @@ fapi2::ReturnCode p9_pm_ocb_init( // ------------------------------------------------------------------------- if (i_mode == p9pm::PM_INIT) { - FAPI_DBG("Functionality not yet defined for Channel Initialization."); + FAPI_DBG(" Channel initialization is a no-op."); } // ------------------------------------------------------------------------- // RESET mode: Change the OCB channel registers to scan-0 flush state @@ -482,80 +482,82 @@ fapi2::ReturnCode pm_ocb_reset( FAPI_IMP("p9_pm_ocb_reset Enter"); fapi2::buffer<uint64_t> l_buf64; - uint8_t i = 0; + // vector of reset channels + std::vector<uint8_t> v_reset_chan; + v_reset_chan.push_back(1); // ------------------------------------------------------------------------- // Loop over PIB Registers // ------------------------------------------------------------------------- - for (i = 0; i <= MAX_OCB_CHANNELS; i++) + for (auto chan : v_reset_chan) { fapi2::buffer<uint64_t> l_data64; // Clear out OCB Channel BAR registers - FAPI_TRY(fapi2::putScom(i_target, OCBARn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBARn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d BAR Register", i); + "Channel %d BAR Register", chan); // Clear out OCB Channel control and status registers l_data64.flush<1>(); - FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_CLEAR[i], l_data64), + FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_CLEAR[chan], l_data64), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Control & Status Register Clear", i); + "Channel %d Control & Status Register Clear", chan); // Put channels in Circular mode // - set bits 4,5 (circular mode) using OR l_data64.flush<0>().setBit<4>().setBit<5>(); - FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_OR[i], l_data64), + FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_OR[chan], l_data64), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Control & Status OR Register Set", i); + "Channel %d Control & Status OR Register Set", chan); // Clear out OCB Channel Error Status registers - FAPI_TRY(fapi2::putScom(i_target, OCBESRn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBESRn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Error Status Register", i); + "Channel %d Error Status Register", chan); } // ------------------------------------------------------------------------- // Loop over OCI Registers // ------------------------------------------------------------------------- - for (i = 0; i <= MAX_OCB_CHANNELS; i++) + for (auto chan : v_reset_chan) { fapi2::buffer<uint64_t> l_data64; // Clear out Pull Base - FAPI_TRY(fapi2::putScom(i_target, OCBSLBRn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBSLBRn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Pull Base Register", i); + "Channel %d Pull Base Register", chan); // Clear out Push Base - FAPI_TRY(fapi2::putScom(i_target, OCBSHBRn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBSHBRn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Push Base Register", i); + "Channel %d Push Base Register", chan); // Clear out Pull Control & Status - FAPI_TRY(fapi2::putScom(i_target, OCBSLCSn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBSLCSn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Pull Control & Status Register", i); + "Channel %d Pull Control & Status Register", chan); // Clear out Push Control & Status - FAPI_TRY(fapi2::putScom(i_target, OCBSHCSn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBSHCSn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Push Control & Status Register", i); + "Channel %d Push Control & Status Register", chan); // Clear out Stream Error Status - FAPI_TRY(fapi2::putScom(i_target, OCBSESn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBSESn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Stream Error Status Register", i); + "Channel %d Stream Error Status Register", chan); // Clear out Linear Window Control - FAPI_TRY(fapi2::putScom(i_target, OCBLWCRn[i], 0), + FAPI_TRY(fapi2::putScom(i_target, OCBLWCRn[chan], 0), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Linear Window Control Register", i); + "Channel %d Linear Window Control Register", chan); // Clear out Linear Window Base // - set bits 3:9 l_data64.setBit<3, 7>(); - FAPI_TRY(fapi2::putScom(i_target, OCBLWSBRn[i], l_data64), + FAPI_TRY(fapi2::putScom(i_target, OCBLWSBRn[chan], l_data64), "**** ERROR : Unexpected error encountered in write to OCB " - "Channel %d Linear Window Base Register", i); + "Channel %d Linear Window Base Register", chan); } // Set Interrupt Source Mask Registers 0 & 1 diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C index f054409fe..57fbf3e6f 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C @@ -616,7 +616,7 @@ pba_slave_setup_boot_phase( l_data64 = ps.value; FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL0_SCOM, l_data64), - "Failed to set Slave 3 control register"); + "Failed to set Slave 0 control register"); FAPI_INF("Skipping PBA Slave 1 ..."); // Slave 1 is not used during Boot phase @@ -711,7 +711,7 @@ pba_slave_setup_runtime_phase( l_data64 = ps.value; FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL0_SCOM, l_data64), - "Failed to set Slave 3 control register"); + "Failed to set Slave 0 control register"); FAPI_INF("Initialize PBA Slave 1 for SGPE 24x7 use..."); // Slave 1 (SGPE 24x7). This is a read/write slave. Write gethering is @@ -732,8 +732,8 @@ pba_slave_setup_runtime_phase( l_data64 = ps.value; - FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL2_SCOM, l_data64), - "Failed to set Slave 2 control register"); + FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL1_SCOM, l_data64), + "Failed to set Slave 1 control register"); FAPI_INF("Disabling PBA Slave 2 ... To be enabled/setup by OCC Firmware"); |