diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/HBconfig | 5 | ||||
| -rwxr-xr-x | src/build/citest/etc/workarounds.presimsetup | 40 | ||||
| -rwxr-xr-x | src/build/simics/hb-simdebug.py | 6 | ||||
| -rwxr-xr-x | src/build/simics/standalone.simics | 101 | ||||
| -rwxr-xr-x | src/build/simics/startup.simics | 42 | ||||
| -rw-r--r-- | src/include/arch/ppc.H | 5 | ||||
| -rw-r--r-- | src/include/sys/misc.h | 8 | ||||
| -rw-r--r-- | src/include/usr/vmmconst.h | 5 | ||||
| -rw-r--r-- | src/kernel/basesegment.C | 6 | ||||
| -rw-r--r-- | src/kernel/cpuid.C | 10 | ||||
| -rw-r--r-- | src/kernel/cpumgr.C | 7 | ||||
| -rw-r--r-- | src/kernel/exception.C | 2 | ||||
| -rw-r--r-- | src/kernel/misc.C | 8 | ||||
| -rw-r--r-- | src/lib/syscall_misc.C | 8 | ||||
| -rw-r--r-- | src/lib/syscall_mmio.C | 3 | ||||
| -rw-r--r-- | src/usr/errl/errlmanager.C | 5 | ||||
| -rw-r--r-- | src/usr/pnor/pnorrp.C | 4 | ||||
| -rw-r--r-- | src/usr/secureboot/base/purge.C | 10 | ||||
| -rw-r--r-- | src/usr/secureboot/base/securerom.C | 3 | ||||
| -rw-r--r-- | src/usr/targeting/targetservicestart.C | 16 | ||||
| -rw-r--r-- | src/usr/xscom/xscom.C | 6 | ||||
| -rw-r--r-- | src/usr/xscom/xscom.H | 8 |
22 files changed, 224 insertions, 84 deletions
diff --git a/src/HBconfig b/src/HBconfig index 8796bfcc9..b1d1f332e 100644 --- a/src/HBconfig +++ b/src/HBconfig @@ -8,3 +8,8 @@ config BMC_AST2400 default n help Compile hostboot support for AST2400 based BMC + +config P9_SYSTEM + default n + help + Compile with P9 configurations
\ No newline at end of file diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup index 6c1e84378..2b1321ffc 100755 --- a/src/build/citest/etc/workarounds.presimsetup +++ b/src/build/citest/etc/workarounds.presimsetup @@ -6,7 +6,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2014 +# Contributors Listed Below - COPYRIGHT 2011,2015 # [+] International Business Machines Corp. # # @@ -50,5 +50,43 @@ grep -v "GFW_P8_HB_UNSECURE_OFFSET" \ echo "SETENV GFW_P8_HB_UNSECURE_OFFSET 58720256" >> \ $sb/simu/configs/P8_VENICE.config +echo "+++ Patching P9_NIMBUS.config with L3_MB_SIZE." +egrep -v "GFW_P9_NIMBUS_L3_MB_SIZE|GFW_P9_NIMBUS_HB_BASE_IMG_USE_PNOR|GFW_P9_NIMBUS_HB_BASE_IMG_WITH_ECC" \ + $BACKING_BUILD/src/simu/configs/P9_NIMBUS.config > \ + $sb/simu/configs/P9_NIMBUS.config +echo "SETENV GFW_P9_NIMBUS_L3_MB_SIZE 10 +SETENV GFW_P9_NIMBUS_HB_BASE_IMG_USE_PNOR no +SETENV GFW_P9_NIMBUS_HB_BASE_IMG_WITH_ECC no +SETENV XSCOM_BASE_ADDR 0x0006010000000000" >> \ + $sb/simu/configs/P9_NIMBUS.config +echo "+++ Patching simicsInfo with new POWER9 FIPSLEVEL." +mkdir -p $sb/simu/data +grep -v "WSALIAS POWER9 FIPSLEVEL" \ + $BACKING_BUILD/src/simu/data/simicsInfo > \ + $sb/simu/data/simicsInfo +echo "WSALIAS POWER9 FIPSLEVEL env/sima/simics-4.8.0/simics-4.8.87/fips/fld36/fi150615g900.48" >> \ + $sb/simu/data/simicsInfo +echo "+++ Creating p9.act with SBE start action." +mkdir -p $sb/simu/data/cec-chip +echo \ +"CAUSE_EFFECT { + LABEL=[Master SBE Start Part One - c4t0] + WATCH=[STARTSBEREGS(0x0)] + CAUSE: TARGET=[STARTSBEREGS(0x0)] OP=[BIT,ON] BIT=[0] + EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 0)] OP=[MODULECALL] # jlo_181 + EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 1)] OP=[MODULECALL] # jlo_181 + EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 2)] OP=[MODULECALL] # jlo_181 + EFFECT: TARGET=[MODULE(enterMaintenanceMode, 0, 3)] OP=[MODULECALL] # jlo_181 + EFFECT: TARGET=[MODULE(sbeStart, FSIMBOX(0x3A), LOGIC(0xFF0CC004), 0)] OP=[MODULECALL] #dds129 + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[0] #Signal Centaur 0 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[1] #Signal Centaur 1 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[2] #Signal Centaur 2 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[3] #Signal Centaur 3 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[4] #Signal Centaur 4 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[5] #Signal Centaur 5 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[6] #Signal Centaur 6 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x1)] OP=[BIT,ON] BIT=[7] #Signal Centaur 7 to flush regs + EFFECT: TARGET=[STARTSBEREGS(0x0)] OP=[BIT,OFF] BIT=[0] #reset to 0 so subsequent SBE starts will trigger this action again +}" > $sb/simu/data/cec-chip/p9.act diff --git a/src/build/simics/hb-simdebug.py b/src/build/simics/hb-simdebug.py index 74347e8a0..fedb0780f 100755 --- a/src/build/simics/hb-simdebug.py +++ b/src/build/simics/hb-simdebug.py @@ -5,7 +5,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2011,2014 +# Contributors Listed Below - COPYRIGHT 2011,2015 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -197,7 +199,7 @@ def hb_get_objects_by_class(classname): def hb_getallregs(regname): proc_list=[] - proc_list=hb_get_objects_by_class("ppc-power8-mambo-core") + proc_list=hb_get_objects_by_class("ppc-power9-mambo-core") for proc in proc_list: output = run_command("%s.read-reg %s"%(proc.name,regname)) print ">> %s : " %(proc.name) + "%x" %output diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics index a992bca92..15b4ad6ac 100755 --- a/src/build/simics/standalone.simics +++ b/src/build/simics/standalone.simics @@ -4,63 +4,84 @@ ($hb_masterproc).proc_fsi2host_mbox->responder_enable=1 +# @todo-RTC:127341 Standalaone VPD support # Preload VPD in PNOR -foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) { - try { - run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py) - ($pnor).sfc_master_mem.load-file ./sysmvpd.dat.ecc 0x1C5000 - ($pnor).sfc_master_mem.load-file ./sysspd.dat.ecc 0x17D000 - ($pnor).sfc_master_mem.load-file ./syscvpd.dat.ecc 0x255000 - } except { echo "ERROR: Failed to preload VPD into PNOR." } -} +#foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) { +# try { +# run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py) +# ($pnor).sfc_master_mem.load-file ./sysmvpd.dat.ecc 0x1C5000 +# ($pnor).sfc_master_mem.load-file ./sysspd.dat.ecc 0x17D000 +# ($pnor).sfc_master_mem.load-file ./syscvpd.dat.ecc 0x255000 +# } except { echo "ERROR: Failed to preload VPD into PNOR." } +#} +# Uncomment when PNOR is supported +# @todo-RTC:130182 Enable PNOR access #Write the PNOR MMIO addr into Scratch 2, 0x283A #($hb_masterproc).proc_lbus_map.write 0x28e8 0xFFF78000 #HB PNOR addr -foreach $cc in (get-object-list p8_proc) { - ($cc).proc_lbus_map.write 0x28e8 0xFFF78000 -} +#foreach $cc in (get-object-list p9_proc) { +# ($cc).proc_lbus_map.write 0x28e8 0xFFF78000 +#} # Loop through every processor chip -foreach $cc in (get-object-list p8_proc) { +foreach $cc in (get-object-list p9_proc) { echo $cc #Trigger a power on to cec-chip - echo "-Trigger power on" + #echo "-Trigger power on" @mp="%s.proc_chip"%simenv.cc - @SIM_get_interface(SIM_get_object(mp),"signal").signal_raise(SIM_get_object(mp)) + @SIM_get_interface(SIM_get_object(mp),"signal").signal_raise() + # @todo-RTC:130184 Add real SBE behavior #Trigger the flush, load, and SBE start - echo "-Trigger SBE" - ($cc).proc_lbus_map.write 0x28E0 0x0000F3FF #NonFunc EX (only 4,5 is good) - ($cc).proc_lbus_map.write 0x2848 0x00000FFF #GP3 0x2812 (flush) - ($cc).proc_lbus_map.write 0x2870 0xB0000000 #SBE Vital 0x281C (load) - ($cc).proc_lbus_map.write 0x2870 0x30000000 #SBE Vital 0x281C (start) + #echo "-Trigger SBE" + #($cc).proc_lbus_map.write 0x28E0 0x0000F3FF #NonFunc EX (only 4,5 is good) + #($cc).proc_lbus_map.write 0x2848 0x00000FFF #GP3 0x2812 (flush) + #($cc).proc_lbus_map.write 0x2870 0xB0000000 #SBE Vital 0x281C (load) + #($cc).proc_lbus_map.write 0x2870 0x30000000 #SBE Vital 0x281C (start) + # workaround to trigger sbe start + ($cc).proc_chip.invoke parallel_store STARTSBEREGS 0 "80000000" 32 } +# Workaround to load hb image into memory +# @todo-RTC:130182 Remove when PNOR access enabled +system_cmp0.phys_mem.load-file $hb_script_location+"/hbicore.bin" 0x0 + +# Workaround to set the sim_ctrl1 reg to enable the +# old HPT SDR1 translation, not the new PTCR translation +# SIM_CTRL1_P9_SDR1 0x0010000000000000 +# @todo-RTC:126640 Remove with P9 page table support +system_cmp0.cpu0_0_00_0.write-reg sim_ctrl1 0x4230000000000000 + +# Workaround to set the hrmor +# @todo-RTC:130184 Remove with real SBE behavior +system_cmp0.cpu0_0_00_0.write-reg hrmor 0x0000008000000 + +# @todo-RTC:130182 Update when PNOR is supported ################################### #Configure SFC (mimmic FSP Setup) ################################### -echo "Configure SFC" - -foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) { - echo $pnor - #Direct Read window config - ($pnor).sfc_master->regs_OADRNB = 0xC000000 - ($pnor).sfc_master->regs_ADRCBF = 0x0 - ($pnor).sfc_master->regs_ADRCMF = 0xF - - #Direct Access Cache Disable - ($pnor).sfc_master->regs_CONF = 0x00000002 - - #Small Erase op code - ($pnor).sfc_master->regs_CONF4 = 0x00000020 - #Erase Size - ($pnor).sfc_master->regs_CONF5 = 0x1000 - - #Enable 4 byte address mode - must write via memory to trigger - #model behavior - ($pnor).fsi_local_lbus_map.write 0xC40 0x00006E00 -} +#echo "Configure SFC" + +#foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) { +# echo $pnor +# #Direct Read window config +# ($pnor).sfc_master->regs_OADRNB = 0xC000000 +# ($pnor).sfc_master->regs_ADRCBF = 0x0 +# ($pnor).sfc_master->regs_ADRCMF = 0xF + +# #Direct Access Cache Disable +# ($pnor).sfc_master->regs_CONF = 0x00000002 + +# #Small Erase op code +# ($pnor).sfc_master->regs_CONF4 = 0x00000020 +# #Erase Size +# ($pnor).sfc_master->regs_CONF5 = 0x1000 + +# #Enable 4 byte address mode - must write via memory to trigger +# #model behavior +# ($pnor).fsi_local_lbus_map.write 0xC40 0x00006E00 +#} ################################### #Enable the IPMI Responder diff --git a/src/build/simics/startup.simics b/src/build/simics/startup.simics index bd7db5b3d..794530703 100755 --- a/src/build/simics/startup.simics +++ b/src/build/simics/startup.simics @@ -3,7 +3,7 @@ $hb_startup_path = (lookup-file hbfw/startup.simics) $hb_script_location = (python "''.join(map('/'.__add__,\""+$hb_startup_path+"\"[1:].split('/')[0:-1]))") python "os.environ['HB_TOOLPATH'] = \""+$hb_script_location+"\"" -$hb_machine = (shell "env | grep 'GFW_P8_.*_PROC_EC' | sed 's/GFW_P8_\\(.*\\)_PROC_EC.*/\\1/'") +$hb_machine = (shell "env | grep 'GFW_P9_.*_PROC_EC' | sed 's/GFW_P9_\\(.*\\)_PROC_EC.*/\\1/'") $hb_machine = (python "\""+$hb_machine+"\".lower()") python "os.environ['HB_MACHINE'] = \""+$hb_machine+"\"" @@ -13,31 +13,33 @@ $hb_masterproc = "" @simenv.hb_masterproc = quiet_run_command("get-master-proc")[0] echo "Master Proc is: "+$hb_masterproc -$hb_pnor = "" -@simenv.hb_pnor = quiet_run_command("get-master-pnor")[0] -try { - @SIM_get_object(simenv.hb_pnor[0]) -} except { - try { - # Attempt to use the Brazos name - @SIM_get_object("cecdrawer0_fpga0") - $hb_pnor = "cecdrawer0_fpga0" - } except { - # Default to Tuleta/Orlena name - $hb_pnor = "fpga0" - } -} -echo "Master PNOR is: "+$hb_pnor +# Uncomment when PNOR is supported +# @todo-RTC:130182 Enable PNOR access +#$hb_pnor = "" +#@simenv.hb_pnor = quiet_run_command("get-master-pnor")[0] +#try { +# @SIM_get_object(simenv.hb_pnor[0]) +#} except { +# try { +# # Attempt to use the Brazos name +# @SIM_get_object("cecdrawer0_fpga0") +# $hb_pnor = "cecdrawer0_fpga0" +# } except { +# # Default to Tuleta/Orlena name +# $hb_pnor = "fpga0" +# } +#} +#echo "Master PNOR is: "+$hb_pnor # Choose a default core to start with -$hb_cpu = "system_cmp0.cpu0_0_04_0" +$hb_cpu = "system_cmp0.cpu0_0_00_0" echo "Defaulting to CPU "+$hb_cpu+" for Hostboot tools" # Prevent SBE Updates from happening on an IPL echo "Altering SBE SEEPROM Versions to disable Update in IPL" -foreach $cc in (get-object-list p8_proc) { - ($cc).procSBEPrimary_eeprom_image.set 0x300 0x5A5A5A5A 8 -l - ($cc).procSBEBackup_eeprom_image.set 0x300 0x5A5A5A5A 8 -l +foreach $cc in (get-object-list p9_proc) { + ($cc).procSBE0Primary_eeprom_image.set 0x300 0x5A5A5A5A 8 -l + ($cc).procSBE0Backup_eeprom_image.set 0x300 0x5A5A5A5A 8 -l } # Load HB debug tools. diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H index 8d22c0790..54c9e8774 100644 --- a/src/include/arch/ppc.H +++ b/src/include/arch/ppc.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2015 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -322,7 +322,8 @@ inline void icbi(void* _ptr) ALWAYS_INLINE inline void nap() { - asm volatile("nap"); + // @todo-RTC:130186 Add new stop command support + //asm volatile("nap"); } ALWAYS_INLINE diff --git a/src/include/sys/misc.h b/src/include/sys/misc.h index f3388e9a4..625b1a78b 100644 --- a/src/include/sys/misc.h +++ b/src/include/sys/misc.h @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -117,6 +119,10 @@ enum ProcessorCoreType CORE_POWER8_VENICE, /** Power8 "Naples" core */ CORE_POWER8_NAPLES, + /** Power9 "NIMBUS" (scale-out) core */ + CORE_POWER9_NIMBUS, + /** Power9 "CUMULUS" (scale-up) core */ + CORE_POWER9_CUMULUS, CORE_UNKNOWN, }; diff --git a/src/include/usr/vmmconst.h b/src/include/usr/vmmconst.h index b78c675b8..0079e0e4f 100644 --- a/src/include/usr/vmmconst.h +++ b/src/include/usr/vmmconst.h @@ -31,6 +31,7 @@ */ #include <limits.h> +#include <config.h> /** * Segments @@ -60,7 +61,11 @@ #define VMM_ADDR_BASE_BLOCK 0 /** Base Segment Base Block size */ +#ifdef CONFIG_P9_SYSTEM +#define VMM_BASE_BLOCK_SIZE (10*MEGABYTE) +#else #define VMM_BASE_BLOCK_SIZE (8*MEGABYTE) +#endif /** Base Segment Extended Memory Block Base Address */ #define VMM_ADDR_EXTEND_BLOCK (VMM_ADDR_BASE_BLOCK + VMM_BASE_BLOCK_SIZE) diff --git a/src/kernel/basesegment.C b/src/kernel/basesegment.C index bde57a0e4..ea5846a46 100644 --- a/src/kernel/basesegment.C +++ b/src/kernel/basesegment.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -55,6 +57,8 @@ void BaseSegment::_init() case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: default: iv_physMemSize = VMM_BASE_BLOCK_SIZE; break; diff --git a/src/kernel/cpuid.C b/src/kernel/cpuid.C index 638942438..576c74043 100644 --- a/src/kernel/cpuid.C +++ b/src/kernel/cpuid.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -51,6 +53,12 @@ namespace CpuID case 0x004D0000: return CORE_POWER8_VENICE; + case 0x004E0000: + return CORE_POWER9_NIMBUS; + + case 0x004F0000: + return CORE_POWER9_CUMULUS; + default: return CORE_UNKNOWN; } diff --git a/src/kernel/cpumgr.C b/src/kernel/cpumgr.C index 44f61a173..1aef65650 100644 --- a/src/kernel/cpumgr.C +++ b/src/kernel/cpumgr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2010,2014 */ +/* Contributors Listed Below - COPYRIGHT 2010,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -450,6 +450,11 @@ size_t CpuManager::getThreadCount() threads = 8; break; + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: + threads = 4; + break; + case CORE_UNKNOWN: default: kassert(false); diff --git a/src/kernel/exception.C b/src/kernel/exception.C index 1ac76c09a..5c16d46cd 100644 --- a/src/kernel/exception.C +++ b/src/kernel/exception.C @@ -282,6 +282,8 @@ void kernel_execute_softpatch() case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: case CORE_UNKNOWN: p8_softpatch_denorm_assist(t->fp_context); break; diff --git a/src/kernel/misc.C b/src/kernel/misc.C index 69e235ba0..a4b438ceb 100644 --- a/src/kernel/misc.C +++ b/src/kernel/misc.C @@ -442,6 +442,8 @@ namespace KernelMisc case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: cache_columns = 4; break; @@ -486,10 +488,12 @@ namespace KernelMisc case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: startAddr = reinterpret_cast<uint64_t*> ( VmmManager::INITIAL_MEM_SIZE ) ; endAddr = - reinterpret_cast<uint64_t*>(8 * MEGABYTE); + reinterpret_cast<uint64_t*>(VMM_BASE_BLOCK_SIZE); break; default: @@ -542,6 +546,8 @@ namespace KernelMisc case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: case CORE_UNKNOWN: l_scratch_addr = l_scratch_addr + 0x40; break; diff --git a/src/lib/syscall_misc.C b/src/lib/syscall_misc.C index 9d86bf937..285fb6091 100644 --- a/src/lib/syscall_misc.C +++ b/src/lib/syscall_misc.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -64,6 +66,10 @@ size_t cpu_thread_count() case CORE_POWER8_NAPLES: threads = 8; break; + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: + threads = 4; + break; default: break; diff --git a/src/lib/syscall_mmio.C b/src/lib/syscall_mmio.C index 535e22d39..1a0de8a9f 100644 --- a/src/lib/syscall_mmio.C +++ b/src/lib/syscall_mmio.C @@ -66,12 +66,15 @@ void mmio_hmer_write(uint64_t value) */ static uint64_t mmio_scratch_base() { + // @todo-RTC:130438 Verify value for P9 ProcessorCoreType cpuType = CpuID::getCpuType(); switch (cpuType) { case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: case CORE_UNKNOWN: default: return 0x40; diff --git a/src/usr/errl/errlmanager.C b/src/usr/errl/errlmanager.C index 3b8b206d3..ff0e62304 100644 --- a/src/usr/errl/errlmanager.C +++ b/src/usr/errl/errlmanager.C @@ -249,9 +249,10 @@ void ErrlManager::errlogMsgHndlr () case ERRLOG_ACCESS_PNOR_TYPE: { // PNOR is up and running now. - +// @todo-RTC:127337 Fake PNOR support +#if (0) setupPnorInfo(); - +#endif //We are done with the msg msg_free(theMsg); diff --git a/src/usr/pnor/pnorrp.C b/src/usr/pnor/pnorrp.C index a887e8a98..d2f739819 100644 --- a/src/usr/pnor/pnorrp.C +++ b/src/usr/pnor/pnorrp.C @@ -280,6 +280,8 @@ void PnorRP::initDaemon() INITSERVICE::registerBlock(reinterpret_cast<void*>(BASE_VADDR), TOTAL_SIZE,PNOR_PRIORITY); +// @todo-RTC:127337 Fake PNOR support +#if (0) //Find and read the TOC in the PNOR to compute the sections and set //their correct permissions l_errhdl = findTOC(); @@ -305,7 +307,7 @@ void PnorRP::initDaemon() // start task to wait on the queue task_create( wait_for_message, NULL ); - +#endif } while(0); if( l_errhdl ) diff --git a/src/usr/secureboot/base/purge.C b/src/usr/secureboot/base/purge.C index 4c5793c39..5d9b7b624 100644 --- a/src/usr/secureboot/base/purge.C +++ b/src/usr/secureboot/base/purge.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -32,6 +34,9 @@ namespace SECUREBOOT { errlHndl_t issueBlindPurge() { + errlHndl_t l_errl = NULL; +// @todo-RTC:118832 Remove with purge update +#if (0) static const uint64_t PURGE_REG = 0x1001080e; // Bits : Value @@ -47,7 +52,6 @@ namespace SECUREBOOT static const size_t RETRY_COUNT = 100; static const size_t RETRY_WAIT_NS = ONE_CTX_SWITCH_NS; - errlHndl_t l_errl = NULL; do { size_t coreId = (task_getcpuid() / 8) & 0xF; @@ -152,7 +156,7 @@ namespace SECUREBOOT } } while(0); - +#endif return l_errl; } diff --git a/src/usr/secureboot/base/securerom.C b/src/usr/secureboot/base/securerom.C index 8b2946210..28bb22983 100644 --- a/src/usr/secureboot/base/securerom.C +++ b/src/usr/secureboot/base/securerom.C @@ -101,6 +101,7 @@ errlHndl_t SecureROM::initialize() TRACDCOMP(g_trac_secure,ENTER_MRK"SecureROM::initialize()"); errlHndl_t l_errl = NULL; +#if (0) bool l_cleanup = false; uint32_t l_rc = 0; @@ -279,7 +280,7 @@ errlHndl_t SecureROM::initialize() TRACDCOMP(g_trac_secure,EXIT_MRK"SecureROM::initialize() - %s", ((NULL == l_errl) ? "No Error" : "With Error") ); - +#endif return l_errl; } diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C index 4252ca32b..203468510 100644 --- a/src/usr/targeting/targetservicestart.C +++ b/src/usr/targeting/targetservicestart.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -86,7 +86,7 @@ static void checkProcessorTargeting(TargetService& i_targetService); /** * @brief Entry point for initialization service to initialize the targeting * code - * + * * @param[in] io_pError * Error log handle; returns NULL on success, !NULL otherwise * @@ -178,6 +178,18 @@ static void checkProcessorTargeting(TargetService& i_targetService) l_haveOneCorrectProcessor = true; } break; + case MODEL_NIMBUS: + if(l_coreType == CORE_POWER9_NIMBUS) + { + l_haveOneCorrectProcessor = true; + } + break; + case MODEL_CUMULUS: + if(l_coreType == CORE_POWER9_CUMULUS) + { + l_haveOneCorrectProcessor = true; + } + break; default: break; diff --git a/src/usr/xscom/xscom.C b/src/usr/xscom/xscom.C index bfc4df2e6..3291ce476 100644 --- a/src/usr/xscom/xscom.C +++ b/src/usr/xscom/xscom.C @@ -201,6 +201,8 @@ uint8_t getMaxChipsPerNode() case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + case CORE_POWER9_NIMBUS: + case CORE_POWER9_CUMULUS: case CORE_UNKNOWN: default: l_numOfChips = 8; @@ -662,6 +664,8 @@ void collectXscomFFDC(TARGETING::Target* i_target, uint64_t* i_virtAddr, errlHndl_t& io_errl) { +// @todo-RTC:128077 XSCOM support for P9 +#if (0) errlHndl_t l_err = NULL; HMER l_hmer; uint64_t io_buffer = 0; @@ -728,7 +732,7 @@ void collectXscomFFDC(TARGETING::Target* i_target, // Add the register FFDC to the errorlog passed in. l_logReg.addToLog(io_errl); - +#endif return; } diff --git a/src/usr/xscom/xscom.H b/src/usr/xscom/xscom.H index 372361b53..df49b1ac0 100644 --- a/src/usr/xscom/xscom.H +++ b/src/usr/xscom/xscom.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -38,8 +40,8 @@ /** * @brief The (fixed) base address value for master proc */ -//@todo - Verify this value for HW -#define MASTER_PROC_XSCOM_BASE_ADDR 0x0003FC0000000000 +// @todo-RTC:128077 XSCOM support for P9 +#define MASTER_PROC_XSCOM_BASE_ADDR 0x0006010000000000 /** * @brief Type definition for XSCom address and Chip ID |
