diff options
Diffstat (limited to 'src')
18 files changed, 2176 insertions, 1946 deletions
diff --git a/src/import/chips/centaur/utils/imageProcs/cen_ringId.C b/src/import/chips/centaur/utils/imageProcs/cen_ringId.C index f6184af42..2f2f050b0 100644 --- a/src/import/chips/centaur/utils/imageProcs/cen_ringId.C +++ b/src/import/chips/centaur/utils/imageProcs/cen_ringId.C @@ -28,24 +28,196 @@ namespace CEN_RID { + #include "cen_ringId.H" + +namespace CEN +{ + +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"tcm_perv_cmsk", 0x00, 0x01, 0x01, CEN_RING, 0x0303400a}, + {"tcm_perv_lbst", 0x01, 0x01, 0x01, CEN_RING, 0x03034004}, + {"tcm_perv_gptr", 0x02, 0x01, 0x01, CEN_RING, 0x03034002}, + {"tcm_perv_func", 0x03, 0x01, 0x01, CEN_RING, 0x03034000}, + {"tcm_perv_time", 0x04, 0x01, 0x01, CEN_RING, 0x03034007}, + {"tcm_perv_abst", 0x05, 0x01, 0x01, CEN_RING, 0x03034005}, + {"tcm_perv_repr", 0x06, 0x01, 0x01, CEN_RING, 0x03034006}, + {"tcm_perv_FARR", 0x07, 0x01, 0x01, CEN_RING, 0x03034009}, + {"tcm_memn_time", 0x08, 0x01, 0x01, CEN_RING, 0x03032007}, + {"tcm_memn_regf", 0x09, 0x01, 0x01, CEN_RING, 0x03032003}, + {"tcm_memn_gptr", 0x0a, 0x01, 0x01, CEN_RING, 0x03032002}, + {"tcm_memn_func", 0x0b, 0x01, 0x01, CEN_RING, 0x03032000}, + {"tcm_memn_lbst", 0x0c, 0x01, 0x01, CEN_RING, 0x03032004}, + {"tcm_memn_cmsk", 0x0d, 0x01, 0x01, CEN_RING, 0x0303200a}, + {"tcm_memn_abst", 0x0e, 0x01, 0x01, CEN_RING, 0x03032005}, + {"tcm_memn_repr", 0x0f, 0x01, 0x01, CEN_RING, 0x03032006}, + {"tcm_memn_FARR", 0x10, 0x01, 0x01, CEN_RING, 0x03032009}, + {"tcm_mems_time", 0x11, 0x01, 0x01, CEN_RING, 0x03031007}, + {"tcm_mems_regf", 0x12, 0x01, 0x01, CEN_RING, 0x03031003}, + {"tcm_mems_gptr", 0x13, 0x01, 0x01, CEN_RING, 0x03031002}, + {"tcm_mems_func", 0x14, 0x01, 0x01, CEN_RING, 0x03031000}, + {"tcm_mems_lbst", 0x15, 0x01, 0x01, CEN_RING, 0x03031004}, + {"tcm_mems_cmsk", 0x16, 0x01, 0x01, CEN_RING, 0x0303100a}, + {"tcm_mems_bndy", 0x17, 0x01, 0x01, CEN_RING, 0x03031008}, + {"tcm_mems_abst", 0x18, 0x01, 0x01, CEN_RING, 0x03031005}, + {"tcm_mems_repr", 0x19, 0x01, 0x01, CEN_RING, 0x03031006}, + {"tcm_mems_FARR", 0x1a, 0x01, 0x01, CEN_RING, 0x03031009}, + {"tcm_ddrn_bndy", 0x1b, 0x01, 0x01, CEN_RING, 0x03030408}, + {"tcm_ddrn_gptr", 0x1c, 0x01, 0x01, CEN_RING, 0x03030402}, + {"tcm_ddrn_func", 0x1d, 0x01, 0x01, CEN_RING, 0x03030400}, + {"tcm_ddrn_cmsk", 0x1e, 0x01, 0x01, CEN_RING, 0x0303040a}, + {"tcm_ddrn_lbst", 0x1f, 0x01, 0x01, CEN_RING, 0x03030404}, + {"tcm_ddrs_bndy", 0x20, 0x01, 0x01, CEN_RING, 0x03030208}, + {"tcm_ddrs_gptr", 0x21, 0x01, 0x01, CEN_RING, 0x03030202}, + {"tcm_ddrs_func", 0x22, 0x01, 0x01, CEN_RING, 0x03030200}, + {"tcm_ddrs_lbst", 0x23, 0x01, 0x01, CEN_RING, 0x03030204}, + {"tcm_ddrs_cmsk", 0x24, 0x01, 0x01, CEN_RING, 0x0303020a}, + {"tcn_perv_cmsk", 0x25, 0x01, 0x01, CEN_RING, 0x0203400a}, + {"tcn_perv_lbst", 0x26, 0x01, 0x01, CEN_RING, 0x02034004}, + {"tcn_perv_gptr", 0x27, 0x01, 0x01, CEN_RING, 0x02034002}, + {"tcn_perv_func", 0x28, 0x01, 0x01, CEN_RING, 0x02034000}, + {"tcn_perv_time", 0x29, 0x01, 0x01, CEN_RING, 0x02034007}, + {"tcn_perv_FARR", 0x2a, 0x01, 0x01, CEN_RING, 0x02034009}, + {"tcn_perv_abst", 0x2b, 0x01, 0x01, CEN_RING, 0x02034005}, + {"tcn_mbi_FARR" , 0x2c, 0x01, 0x01, CEN_RING, 0x02032009}, + {"tcn_mbi_time" , 0x2d, 0x01, 0x01, CEN_RING, 0x02032007}, + {"tcn_mbi_repr" , 0x2e, 0x01, 0x01, CEN_RING, 0x02032006}, + {"tcn_mbi_abst" , 0x2f, 0x01, 0x01, CEN_RING, 0x02032005}, + {"tcn_mbi_regf" , 0x30, 0x01, 0x01, CEN_RING, 0x02032003}, + {"tcn_mbi_gptr" , 0x31, 0x01, 0x01, CEN_RING, 0x02032002}, + {"tcn_mbi_func" , 0x32, 0x01, 0x01, CEN_RING, 0x02032000}, + {"tcn_mbi_cmsk" , 0x33, 0x01, 0x01, CEN_RING, 0x0203200a}, + {"tcn_mbi_lbst" , 0x34, 0x01, 0x01, CEN_RING, 0x02032004}, + {"tcn_dmi_bndy" , 0x35, 0x01, 0x01, CEN_RING, 0x02031008}, + {"tcn_dmi_gptr" , 0x36, 0x01, 0x01, CEN_RING, 0x02031002}, + {"tcn_dmi_func" , 0x37, 0x01, 0x01, CEN_RING, 0x02031000}, + {"tcn_dmi_cmsk" , 0x38, 0x01, 0x01, CEN_RING, 0x0203100a}, + {"tcn_dmi_lbst" , 0x39, 0x01, 0x01, CEN_RING, 0x02031004}, + {"tcn_msc_gptr" , 0x3a, 0x01, 0x01, CEN_RING, 0x02030802}, + {"tcn_msc_func" , 0x3b, 0x01, 0x01, CEN_RING, 0x02030800}, + {"tcn_mbs_FARR" , 0x3c, 0x01, 0x01, CEN_RING, 0x02030409}, + {"tcn_mbs_time" , 0x3d, 0x01, 0x01, CEN_RING, 0x02030407}, + {"tcn_mbs_repr" , 0x3e, 0x01, 0x01, CEN_RING, 0x02030406}, + {"tcn_mbs_abst" , 0x3f, 0x01, 0x01, CEN_RING, 0x02030405}, + {"tcn_mbs_regf" , 0x40, 0x01, 0x01, CEN_RING, 0x02030403}, + {"tcn_mbs_gptr" , 0x41, 0x01, 0x01, CEN_RING, 0x02030402}, + {"tcn_mbs_func" , 0x42, 0x01, 0x01, CEN_RING, 0x02030400}, + {"tcn_mbs_lbst" , 0x43, 0x01, 0x01, CEN_RING, 0x02030404}, + {"tcn_mbs_cmsk" , 0x44, 0x01, 0x01, CEN_RING, 0x0203040a}, + {"tcn_refr_cmsk", 0x45, 0x01, 0x01, CEN_RING, 0x0203010a}, + {"tcn_refr_FARR", 0x46, 0x01, 0x01, CEN_RING, 0x02030109}, + {"tcn_refr_time", 0x47, 0x01, 0x01, CEN_RING, 0x02030107}, + {"tcn_refr_repr", 0x48, 0x01, 0x01, CEN_RING, 0x02030106}, + {"tcn_refr_abst", 0x49, 0x01, 0x01, CEN_RING, 0x02030105}, + {"tcn_refr_lbst", 0x4a, 0x01, 0x01, CEN_RING, 0x02030104}, + {"tcn_refr_regf", 0x4b, 0x01, 0x01, CEN_RING, 0x02030103}, + {"tcn_refr_gptr", 0x4c, 0x01, 0x01, CEN_RING, 0x02030102}, + {"tcn_refr_func", 0x4d, 0x01, 0x01, CEN_RING, 0x02030100}, + {"tcn_perv_repr", 0x4e, 0x01, 0x01, CEN_RING, 0x02034006}, + {"tp_perv_func" , 0x4f, 0x01, 0x01, CEN_RING, 0x01034000}, + {"tp_perv_gptr" , 0x50, 0x01, 0x01, CEN_RING, 0x01034002}, + {"tp_perv_mode" , 0x51, 0x01, 0x01, CEN_RING, 0x01034001}, + {"tp_perv_regf" , 0x52, 0x01, 0x01, CEN_RING, 0x01034003}, + {"tp_perv_lbst" , 0x53, 0x01, 0x01, CEN_RING, 0x01034004}, + {"tp_perv_abst" , 0x54, 0x01, 0x01, CEN_RING, 0x01034005}, + {"tp_perv_repr" , 0x55, 0x01, 0x01, CEN_RING, 0x01034006}, + {"tp_perv_time" , 0x56, 0x01, 0x01, CEN_RING, 0x01034007}, + {"tp_perv_bndy" , 0x57, 0x01, 0x01, CEN_RING, 0x01034008}, + {"tp_perv_farr" , 0x58, 0x01, 0x01, CEN_RING, 0x01034009}, + {"tp_perv_cmsk" , 0x59, 0x01, 0x01, CEN_RING, 0x0103400a}, + {"tp_pll_func" , 0x5a, 0x01, 0x01, CEN_RING, 0x01030080}, + {"tp_pll_gptr" , 0x5b, 0x01, 0x01, CEN_RING, 0x01030082}, + {"tp_net_func" , 0x5c, 0x01, 0x01, CEN_RING, 0x00032000}, + {"tp_net_gptr" , 0x5d, 0x01, 0x01, CEN_RING, 0x00032002}, + {"tp_net_abst" , 0x5e, 0x01, 0x01, CEN_RING, 0x00032005}, + {"tp_pib_func" , 0x5f, 0x01, 0x01, CEN_RING, 0x00031000}, + {"tp_pib_fuse" , 0x60, 0x01, 0x01, CEN_RING, 0x00031005}, + {"tp_pib_gptr" , 0x61, 0x01, 0x01, CEN_RING, 0x00031002}, + {"tp_pll_bndy" , 0x62, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_1", 0x63, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_2", 0x64, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_3", 0x65, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_4", 0x66, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_5", 0x67, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_6", 0x68, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_7", 0x69, 0x01, 0x01, CEN_RING, 0x01030088}, + {"tp_pll_bndy_bucket_8", 0x6a, 0x01, 0x01, CEN_RING, 0x01030088}, }; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; + +}; // namespace CEN + +}; // namespace CEN_RID + using namespace CEN_RID; +ChipletType_t CEN_RID::ringid_get_chiplet(RingId_t i_ringId) +{ + return RING_PROPERTIES[i_ringId].iv_type; +} + void CEN_RID::ringid_get_chiplet_properties( ChipletType_t i_chipletType, - ChipletData_t** o_chipletData) + ChipletData_t** o_cpltData, + GenRingIdList** o_ringComm, + GenRingIdList** o_ringInst, + RingVariantOrder** o_varOrder, + uint8_t* o_numVariants) { switch (i_chipletType) { case CEN_TYPE : - *o_chipletData = (ChipletData_t*)&CEN::g_chipletData; + *o_cpltData = (ChipletData_t*) &CEN::g_chipletData; + *o_ringComm = (GenRingIdList*) CEN::RING_ID_LIST_COMMON; + *o_ringInst = NULL; + *o_varOrder = (RingVariantOrder*) CEN::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; default : - *o_chipletData = NULL; + *o_cpltData = NULL; + *o_ringComm = NULL; + *o_ringInst = NULL; + *o_varOrder = NULL; + *o_numVariants = 0; break; } } + +GenRingIdList* CEN_RID::_ringid_get_ring_list(RingId_t i_ringId) +{ + ChipletData_t* l_cpltData; + GenRingIdList* l_ringList[2]; // 0: common, 1: instance + RingVariantOrder* l_varOrder; + uint8_t l_numVariants;; + int i, j, n; + + CEN_RID::ringid_get_chiplet_properties( + CEN_RID::ringid_get_chiplet(i_ringId), + &l_cpltData, &l_ringList[0], &l_ringList[1], &l_varOrder, &l_numVariants); + + if (!l_ringList[0]) + { + return NULL; + } + + for (j = 0; j < 2; j++) // 0: common, 1: instance + { + n = (j ? l_cpltData->iv_num_instance_rings + : l_cpltData->iv_num_common_rings); + + for (i = 0; i < n; i++) + { + if (!strcmp(l_ringList[j][i].ringName, + RING_PROPERTIES[i_ringId].iv_name)) + { + return &(l_ringList[j][i]); + } + } + } + + return NULL; +} diff --git a/src/import/chips/centaur/utils/imageProcs/cen_ringId.H b/src/import/chips/centaur/utils/imageProcs/cen_ringId.H index bf097d194..6ddd397e2 100644 --- a/src/import/chips/centaur/utils/imageProcs/cen_ringId.H +++ b/src/import/chips/centaur/utils/imageProcs/cen_ringId.H @@ -31,14 +31,16 @@ #include <common_ringId.H> #include <cen_ring_id.h> -enum Chiplets +enum CHIPLET_TYPE { CEN_TYPE, - CEN_NUM_CHIPLETS + CEN_NOOF_CHIPLETS }; namespace CEN { +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; enum RingOffset { @@ -156,145 +158,264 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x01, // Base chiplet/instance ID - 1, // Number of chiplet instances + 0x01, // Centaur chiplet ID NUM_RING_IDS, // Num of common rings for Centaur chiplet 0, // Num of instance rings for Centaur chiplet 0, 2, // Num of ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // namespace CEN #ifndef __PPE__ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { - { "tcm_perv_cmsk", 0x0303400a, CEN::tcm_perv_cmsk, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_perv_lbst", 0x03034004, CEN::tcm_perv_lbst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_perv_gptr", 0x03034002, CEN::tcm_perv_gptr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_perv_func", 0x03034000, CEN::tcm_perv_func, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_perv_time", 0x03034007, CEN::tcm_perv_time, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_perv_abst", 0x03034005, CEN::tcm_perv_abst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_perv_repr", 0x03034006, CEN::tcm_perv_repr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_perv_FARR", 0x03034009, CEN::tcm_perv_FARR, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_time", 0x03032007, CEN::tcm_memn_time, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_regf", 0x03032003, CEN::tcm_memn_regf, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_gptr", 0x03032002, CEN::tcm_memn_gptr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_func", 0x03032000, CEN::tcm_memn_func, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_lbst", 0x03032004, CEN::tcm_memn_lbst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_cmsk", 0x0303200a, CEN::tcm_memn_cmsk, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_abst", 0x03032005, CEN::tcm_memn_abst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_repr", 0x03032006, CEN::tcm_memn_repr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_memn_FARR", 0x03032009, CEN::tcm_memn_FARR, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_time", 0x03031007, CEN::tcm_mems_time, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_regf", 0x03031003, CEN::tcm_mems_regf, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_gptr", 0x03031002, CEN::tcm_mems_gptr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_func", 0x03031000, CEN::tcm_mems_func, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_lbst", 0x03031004, CEN::tcm_mems_lbst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_cmsk", 0x0303100a, CEN::tcm_mems_cmsk, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_bndy", 0x03031008, CEN::tcm_mems_bndy, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_abst", 0x03031005, CEN::tcm_mems_abst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_repr", 0x03031006, CEN::tcm_mems_repr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_mems_FARR", 0x03031009, CEN::tcm_mems_FARR, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrn_bndy", 0x03030408, CEN::tcm_ddrn_bndy, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrn_gptr", 0x03030402, CEN::tcm_ddrn_gptr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrn_func", 0x03030400, CEN::tcm_ddrn_func, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrn_cmsk", 0x0303040a, CEN::tcm_ddrn_cmsk, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrn_lbst", 0x03030404, CEN::tcm_ddrn_lbst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrs_bndy", 0x03030208, CEN::tcm_ddrs_bndy, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrs_gptr", 0x03030202, CEN::tcm_ddrs_gptr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrs_func", 0x03030200, CEN::tcm_ddrs_func, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrs_lbst", 0x03030204, CEN::tcm_ddrs_lbst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcm_ddrs_cmsk", 0x0303020a, CEN::tcm_ddrs_cmsk, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_cmsk", 0x0203400a, CEN::tcn_perv_cmsk, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_lbst", 0x02034004, CEN::tcn_perv_lbst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_gptr", 0x02034002, CEN::tcn_perv_gptr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_func", 0x02034000, CEN::tcn_perv_func, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_time", 0x02034007, CEN::tcn_perv_time, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_FARR", 0x02034009, CEN::tcn_perv_FARR, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_abst", 0x02034005, CEN::tcn_perv_abst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_FARR" , 0x02032009, CEN::tcn_mbi_FARR , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_time" , 0x02032007, CEN::tcn_mbi_time , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_repr" , 0x02032006, CEN::tcn_mbi_repr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_abst" , 0x02032005, CEN::tcn_mbi_abst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_regf" , 0x02032003, CEN::tcn_mbi_regf , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_gptr" , 0x02032002, CEN::tcn_mbi_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_func" , 0x02032000, CEN::tcn_mbi_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_cmsk" , 0x0203200a, CEN::tcn_mbi_cmsk , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbi_lbst" , 0x02032004, CEN::tcn_mbi_lbst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_dmi_bndy" , 0x02031008, CEN::tcn_dmi_bndy , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_dmi_gptr" , 0x02031002, CEN::tcn_dmi_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_dmi_func" , 0x02031000, CEN::tcn_dmi_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_dmi_cmsk" , 0x0203100a, CEN::tcn_dmi_cmsk , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_dmi_lbst" , 0x02031004, CEN::tcn_dmi_lbst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_msc_gptr" , 0x02030802, CEN::tcn_msc_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_msc_func" , 0x02030800, CEN::tcn_msc_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_FARR" , 0x02030409, CEN::tcn_mbs_FARR , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_time" , 0x02030407, CEN::tcn_mbs_time , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_repr" , 0x02030406, CEN::tcn_mbs_repr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_abst" , 0x02030405, CEN::tcn_mbs_abst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_regf" , 0x02030403, CEN::tcn_mbs_regf , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_gptr" , 0x02030402, CEN::tcn_mbs_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_func" , 0x02030400, CEN::tcn_mbs_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_lbst" , 0x02030404, CEN::tcn_mbs_lbst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_mbs_cmsk" , 0x0203040a, CEN::tcn_mbs_cmsk , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_cmsk", 0x0203010a, CEN::tcn_refr_cmsk, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_FARR", 0x02030109, CEN::tcn_refr_FARR, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_time", 0x02030107, CEN::tcn_refr_time, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_repr", 0x02030106, CEN::tcn_refr_repr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_abst", 0x02030105, CEN::tcn_refr_abst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_lbst", 0x02030104, CEN::tcn_refr_lbst, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_regf", 0x02030103, CEN::tcn_refr_regf, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_gptr", 0x02030102, CEN::tcn_refr_gptr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_refr_func", 0x02030100, CEN::tcn_refr_func, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tcn_perv_repr", 0x02034006, CEN::tcn_perv_repr, CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_func" , 0x01034000, CEN::tp_perv_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_gptr" , 0x01034002, CEN::tp_perv_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_mode" , 0x01034001, CEN::tp_perv_mode , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_regf" , 0x01034003, CEN::tp_perv_regf , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_lbst" , 0x01034004, CEN::tp_perv_lbst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_abst" , 0x01034005, CEN::tp_perv_abst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_repr" , 0x01034006, CEN::tp_perv_repr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_time" , 0x01034007, CEN::tp_perv_time , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_bndy" , 0x01034008, CEN::tp_perv_bndy , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_farr" , 0x01034009, CEN::tp_perv_farr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_perv_cmsk" , 0x0103400a, CEN::tp_perv_cmsk , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_pll_func" , 0x01030080, CEN::tp_pll_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_pll_gptr" , 0x01030082, CEN::tp_pll_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_net_func" , 0x00032000, CEN::tp_net_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_net_gptr" , 0x00032002, CEN::tp_net_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_net_abst" , 0x00032005, CEN::tp_net_abst , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_pib_func" , 0x00031000, CEN::tp_pib_func , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_pib_fuse" , 0x00031005, CEN::tp_pib_fuse , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_pib_gptr" , 0x00031002, CEN::tp_pib_gptr , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_pll_bndy" , 0x01030088, CEN::tp_pll_bndy , CEN_TYPE, RCLS_ROOT_RING | RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_1", 0x01030088, CEN::tp_pll_bndy_bucket_1, CEN_TYPE, RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_2", 0x01030088, CEN::tp_pll_bndy_bucket_2, CEN_TYPE, RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_3", 0x01030088, CEN::tp_pll_bndy_bucket_3, CEN_TYPE, RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_4", 0x01030088, CEN::tp_pll_bndy_bucket_4, CEN_TYPE, RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_5", 0x01030088, CEN::tp_pll_bndy_bucket_5, CEN_TYPE, RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_6", 0x01030088, CEN::tp_pll_bndy_bucket_6, CEN_TYPE, RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_7", 0x01030088, CEN::tp_pll_bndy_bucket_7, CEN_TYPE, RCLS_EKB_CEN_RING }, - { "tp_pll_bndy_bucket_8", 0x01030088, CEN::tp_pll_bndy_bucket_8, CEN_TYPE, RCLS_EKB_CEN_RING } + { CEN::tcm_perv_cmsk, "tcm_perv_cmsk", CEN_TYPE }, + { CEN::tcm_perv_lbst, "tcm_perv_lbst", CEN_TYPE }, + { CEN::tcm_perv_gptr, "tcm_perv_gptr", CEN_TYPE }, + { CEN::tcm_perv_func, "tcm_perv_func", CEN_TYPE }, + { CEN::tcm_perv_time, "tcm_perv_time", CEN_TYPE }, + { CEN::tcm_perv_abst, "tcm_perv_abst", CEN_TYPE }, + { CEN::tcm_perv_repr, "tcm_perv_repr", CEN_TYPE }, + { CEN::tcm_perv_FARR, "tcm_perv_FARR", CEN_TYPE }, + { CEN::tcm_memn_time, "tcm_memn_time", CEN_TYPE }, + { CEN::tcm_memn_regf, "tcm_memn_regf", CEN_TYPE }, + { CEN::tcm_memn_gptr, "tcm_memn_gptr", CEN_TYPE }, + { CEN::tcm_memn_func, "tcm_memn_func", CEN_TYPE }, + { CEN::tcm_memn_lbst, "tcm_memn_lbst", CEN_TYPE }, + { CEN::tcm_memn_cmsk, "tcm_memn_cmsk", CEN_TYPE }, + { CEN::tcm_memn_abst, "tcm_memn_abst", CEN_TYPE }, + { CEN::tcm_memn_repr, "tcm_memn_repr", CEN_TYPE }, + { CEN::tcm_memn_FARR, "tcm_memn_FARR", CEN_TYPE }, + { CEN::tcm_mems_time, "tcm_mems_time", CEN_TYPE }, + { CEN::tcm_mems_regf, "tcm_mems_regf", CEN_TYPE }, + { CEN::tcm_mems_gptr, "tcm_mems_gptr", CEN_TYPE }, + { CEN::tcm_mems_func, "tcm_mems_func", CEN_TYPE }, + { CEN::tcm_mems_lbst, "tcm_mems_lbst", CEN_TYPE }, + { CEN::tcm_mems_cmsk, "tcm_mems_cmsk", CEN_TYPE }, + { CEN::tcm_mems_bndy, "tcm_mems_bndy", CEN_TYPE }, + { CEN::tcm_mems_abst, "tcm_mems_abst", CEN_TYPE }, + { CEN::tcm_mems_repr, "tcm_mems_repr", CEN_TYPE }, + { CEN::tcm_mems_FARR, "tcm_mems_FARR", CEN_TYPE }, + { CEN::tcm_ddrn_bndy, "tcm_ddrn_bndy", CEN_TYPE }, + { CEN::tcm_ddrn_gptr, "tcm_ddrn_gptr", CEN_TYPE }, + { CEN::tcm_ddrn_func, "tcm_ddrn_func", CEN_TYPE }, + { CEN::tcm_ddrn_cmsk, "tcm_ddrn_cmsk", CEN_TYPE }, + { CEN::tcm_ddrn_lbst, "tcm_ddrn_lbst", CEN_TYPE }, + { CEN::tcm_ddrs_bndy, "tcm_ddrs_bndy", CEN_TYPE }, + { CEN::tcm_ddrs_gptr, "tcm_ddrs_gptr", CEN_TYPE }, + { CEN::tcm_ddrs_func, "tcm_ddrs_func", CEN_TYPE }, + { CEN::tcm_ddrs_lbst, "tcm_ddrs_lbst", CEN_TYPE }, + { CEN::tcm_ddrs_cmsk, "tcm_ddrs_cmsk", CEN_TYPE }, + { CEN::tcn_perv_cmsk, "tcn_perv_cmsk", CEN_TYPE }, + { CEN::tcn_perv_lbst, "tcn_perv_lbst", CEN_TYPE }, + { CEN::tcn_perv_gptr, "tcn_perv_gptr", CEN_TYPE }, + { CEN::tcn_perv_func, "tcn_perv_func", CEN_TYPE }, + { CEN::tcn_perv_time, "tcn_perv_time", CEN_TYPE }, + { CEN::tcn_perv_FARR, "tcn_perv_FARR", CEN_TYPE }, + { CEN::tcn_perv_abst, "tcn_perv_abst", CEN_TYPE }, + { CEN::tcn_mbi_FARR , "tcn_mbi_FARR" , CEN_TYPE }, + { CEN::tcn_mbi_time , "tcn_mbi_time" , CEN_TYPE }, + { CEN::tcn_mbi_repr , "tcn_mbi_repr" , CEN_TYPE }, + { CEN::tcn_mbi_abst , "tcn_mbi_abst" , CEN_TYPE }, + { CEN::tcn_mbi_regf , "tcn_mbi_regf" , CEN_TYPE }, + { CEN::tcn_mbi_gptr , "tcn_mbi_gptr" , CEN_TYPE }, + { CEN::tcn_mbi_func , "tcn_mbi_func" , CEN_TYPE }, + { CEN::tcn_mbi_cmsk , "tcn_mbi_cmsk" , CEN_TYPE }, + { CEN::tcn_mbi_lbst , "tcn_mbi_lbst" , CEN_TYPE }, + { CEN::tcn_dmi_bndy , "tcn_dmi_bndy" , CEN_TYPE }, + { CEN::tcn_dmi_gptr , "tcn_dmi_gptr" , CEN_TYPE }, + { CEN::tcn_dmi_func , "tcn_dmi_func" , CEN_TYPE }, + { CEN::tcn_dmi_cmsk , "tcn_dmi_cmsk" , CEN_TYPE }, + { CEN::tcn_dmi_lbst , "tcn_dmi_lbst" , CEN_TYPE }, + { CEN::tcn_msc_gptr , "tcn_msc_gptr" , CEN_TYPE }, + { CEN::tcn_msc_func , "tcn_msc_func" , CEN_TYPE }, + { CEN::tcn_mbs_FARR , "tcn_mbs_FARR" , CEN_TYPE }, + { CEN::tcn_mbs_time , "tcn_mbs_time" , CEN_TYPE }, + { CEN::tcn_mbs_repr , "tcn_mbs_repr" , CEN_TYPE }, + { CEN::tcn_mbs_abst , "tcn_mbs_abst" , CEN_TYPE }, + { CEN::tcn_mbs_regf , "tcn_mbs_regf" , CEN_TYPE }, + { CEN::tcn_mbs_gptr , "tcn_mbs_gptr" , CEN_TYPE }, + { CEN::tcn_mbs_func , "tcn_mbs_func" , CEN_TYPE }, + { CEN::tcn_mbs_lbst , "tcn_mbs_lbst" , CEN_TYPE }, + { CEN::tcn_mbs_cmsk , "tcn_mbs_cmsk" , CEN_TYPE }, + { CEN::tcn_refr_cmsk, "tcn_refr_cmsk", CEN_TYPE }, + { CEN::tcn_refr_FARR, "tcn_refr_FARR", CEN_TYPE }, + { CEN::tcn_refr_time, "tcn_refr_time", CEN_TYPE }, + { CEN::tcn_refr_repr, "tcn_refr_repr", CEN_TYPE }, + { CEN::tcn_refr_abst, "tcn_refr_abst", CEN_TYPE }, + { CEN::tcn_refr_lbst, "tcn_refr_lbst", CEN_TYPE }, + { CEN::tcn_refr_regf, "tcn_refr_regf", CEN_TYPE }, + { CEN::tcn_refr_gptr, "tcn_refr_gptr", CEN_TYPE }, + { CEN::tcn_refr_func, "tcn_refr_func", CEN_TYPE }, + { CEN::tcn_perv_repr, "tcn_perv_repr", CEN_TYPE }, + { CEN::tp_perv_func , "tp_perv_func" , CEN_TYPE }, + { CEN::tp_perv_gptr , "tp_perv_gptr" , CEN_TYPE }, + { CEN::tp_perv_mode , "tp_perv_mode" , CEN_TYPE }, + { CEN::tp_perv_regf , "tp_perv_regf" , CEN_TYPE }, + { CEN::tp_perv_lbst , "tp_perv_lbst" , CEN_TYPE }, + { CEN::tp_perv_abst , "tp_perv_abst" , CEN_TYPE }, + { CEN::tp_perv_repr , "tp_perv_repr" , CEN_TYPE }, + { CEN::tp_perv_time , "tp_perv_time" , CEN_TYPE }, + { CEN::tp_perv_bndy , "tp_perv_bndy" , CEN_TYPE }, + { CEN::tp_perv_farr , "tp_perv_farr" , CEN_TYPE }, + { CEN::tp_perv_cmsk , "tp_perv_cmsk" , CEN_TYPE }, + { CEN::tp_pll_func , "tp_pll_func" , CEN_TYPE }, + { CEN::tp_pll_gptr , "tp_pll_gptr" , CEN_TYPE }, + { CEN::tp_net_func , "tp_net_func" , CEN_TYPE }, + { CEN::tp_net_gptr , "tp_net_gptr" , CEN_TYPE }, + { CEN::tp_net_abst , "tp_net_abst" , CEN_TYPE }, + { CEN::tp_pib_func , "tp_pib_func" , CEN_TYPE }, + { CEN::tp_pib_fuse , "tp_pib_fuse" , CEN_TYPE }, + { CEN::tp_pib_gptr , "tp_pib_gptr" , CEN_TYPE }, + { CEN::tp_pll_bndy , "tp_pll_bndy" , CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_1, "tp_pll_bndy_bucket_1", CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_2, "tp_pll_bndy_bucket_2", CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_3, "tp_pll_bndy_bucket_3", CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_4, "tp_pll_bndy_bucket_4", CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_5, "tp_pll_bndy_bucket_5", CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_6, "tp_pll_bndy_bucket_6", CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_7, "tp_pll_bndy_bucket_7", CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_8, "tp_pll_bndy_bucket_8", CEN_TYPE } }; #else static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { - // Not needed in SBE code + { CEN::tcm_perv_cmsk, CEN_TYPE }, + { CEN::tcm_perv_lbst, CEN_TYPE }, + { CEN::tcm_perv_gptr, CEN_TYPE }, + { CEN::tcm_perv_func, CEN_TYPE }, + { CEN::tcm_perv_time, CEN_TYPE }, + { CEN::tcm_perv_abst, CEN_TYPE }, + { CEN::tcm_perv_repr, CEN_TYPE }, + { CEN::tcm_perv_FARR, CEN_TYPE }, + { CEN::tcm_memn_time, CEN_TYPE }, + { CEN::tcm_memn_regf, CEN_TYPE }, + { CEN::tcm_memn_gptr, CEN_TYPE }, + { CEN::tcm_memn_func, CEN_TYPE }, + { CEN::tcm_memn_lbst, CEN_TYPE }, + { CEN::tcm_memn_cmsk, CEN_TYPE }, + { CEN::tcm_memn_abst, CEN_TYPE }, + { CEN::tcm_memn_repr, CEN_TYPE }, + { CEN::tcm_memn_FARR, CEN_TYPE }, + { CEN::tcm_mems_time, CEN_TYPE }, + { CEN::tcm_mems_regf, CEN_TYPE }, + { CEN::tcm_mems_gptr, CEN_TYPE }, + { CEN::tcm_mems_func, CEN_TYPE }, + { CEN::tcm_mems_lbst, CEN_TYPE }, + { CEN::tcm_mems_cmsk, CEN_TYPE }, + { CEN::tcm_mems_bndy, CEN_TYPE }, + { CEN::tcm_mems_abst, CEN_TYPE }, + { CEN::tcm_mems_repr, CEN_TYPE }, + { CEN::tcm_mems_FARR, CEN_TYPE }, + { CEN::tcm_ddrn_bndy, CEN_TYPE }, + { CEN::tcm_ddrn_gptr, CEN_TYPE }, + { CEN::tcm_ddrn_func, CEN_TYPE }, + { CEN::tcm_ddrn_cmsk, CEN_TYPE }, + { CEN::tcm_ddrn_lbst, CEN_TYPE }, + { CEN::tcm_ddrs_bndy, CEN_TYPE }, + { CEN::tcm_ddrs_gptr, CEN_TYPE }, + { CEN::tcm_ddrs_func, CEN_TYPE }, + { CEN::tcm_ddrs_lbst, CEN_TYPE }, + { CEN::tcm_ddrs_cmsk, CEN_TYPE }, + { CEN::tcn_perv_cmsk, CEN_TYPE }, + { CEN::tcn_perv_lbst, CEN_TYPE }, + { CEN::tcn_perv_gptr, CEN_TYPE }, + { CEN::tcn_perv_func, CEN_TYPE }, + { CEN::tcn_perv_time, CEN_TYPE }, + { CEN::tcn_perv_FARR, CEN_TYPE }, + { CEN::tcn_perv_abst, CEN_TYPE }, + { CEN::tcn_mbi_FARR , CEN_TYPE }, + { CEN::tcn_mbi_time , CEN_TYPE }, + { CEN::tcn_mbi_repr , CEN_TYPE }, + { CEN::tcn_mbi_abst , CEN_TYPE }, + { CEN::tcn_mbi_regf , CEN_TYPE }, + { CEN::tcn_mbi_gptr , CEN_TYPE }, + { CEN::tcn_mbi_func , CEN_TYPE }, + { CEN::tcn_mbi_cmsk , CEN_TYPE }, + { CEN::tcn_mbi_lbst , CEN_TYPE }, + { CEN::tcn_dmi_bndy , CEN_TYPE }, + { CEN::tcn_dmi_gptr , CEN_TYPE }, + { CEN::tcn_dmi_func , CEN_TYPE }, + { CEN::tcn_dmi_cmsk , CEN_TYPE }, + { CEN::tcn_dmi_lbst , CEN_TYPE }, + { CEN::tcn_msc_gptr , CEN_TYPE }, + { CEN::tcn_msc_func , CEN_TYPE }, + { CEN::tcn_mbs_FARR , CEN_TYPE }, + { CEN::tcn_mbs_time , CEN_TYPE }, + { CEN::tcn_mbs_repr , CEN_TYPE }, + { CEN::tcn_mbs_abst , CEN_TYPE }, + { CEN::tcn_mbs_regf , CEN_TYPE }, + { CEN::tcn_mbs_gptr , CEN_TYPE }, + { CEN::tcn_mbs_func , CEN_TYPE }, + { CEN::tcn_mbs_lbst , CEN_TYPE }, + { CEN::tcn_mbs_cmsk , CEN_TYPE }, + { CEN::tcn_refr_cmsk, CEN_TYPE }, + { CEN::tcn_refr_FARR, CEN_TYPE }, + { CEN::tcn_refr_time, CEN_TYPE }, + { CEN::tcn_refr_repr, CEN_TYPE }, + { CEN::tcn_refr_abst, CEN_TYPE }, + { CEN::tcn_refr_lbst, CEN_TYPE }, + { CEN::tcn_refr_regf, CEN_TYPE }, + { CEN::tcn_refr_gptr, CEN_TYPE }, + { CEN::tcn_refr_func, CEN_TYPE }, + { CEN::tcn_perv_repr, CEN_TYPE }, + { CEN::tp_perv_func , CEN_TYPE }, + { CEN::tp_perv_gptr , CEN_TYPE }, + { CEN::tp_perv_mode , CEN_TYPE }, + { CEN::tp_perv_regf , CEN_TYPE }, + { CEN::tp_perv_lbst , CEN_TYPE }, + { CEN::tp_perv_abst , CEN_TYPE }, + { CEN::tp_perv_repr , CEN_TYPE }, + { CEN::tp_perv_time , CEN_TYPE }, + { CEN::tp_perv_bndy , CEN_TYPE }, + { CEN::tp_perv_farr , CEN_TYPE }, + { CEN::tp_perv_cmsk , CEN_TYPE }, + { CEN::tp_pll_func , CEN_TYPE }, + { CEN::tp_pll_gptr , CEN_TYPE }, + { CEN::tp_net_func , CEN_TYPE }, + { CEN::tp_net_gptr , CEN_TYPE }, + { CEN::tp_net_abst , CEN_TYPE }, + { CEN::tp_pib_func , CEN_TYPE }, + { CEN::tp_pib_fuse , CEN_TYPE }, + { CEN::tp_pib_gptr , CEN_TYPE }, + { CEN::tp_pll_bndy , CEN_TYPE }, + { CEN::tp_pib_repr , CEN_TYPE }, + { CEN::tp_vitl , CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_1, CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_2, CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_3, CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_4, CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_5, CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_6, CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_7, CEN_TYPE }, + { CEN::tp_pll_bndy_bucket_8, CEN_TYPE } }; #endif // __PPE__ -// Returns data structures associated with chipletType + +// returns our own chiplet enum value for this ringId +ChipletType_t +ringid_get_chiplet(RingId_t i_ringId); + +// returns data structures defined for chiplet type +// as determined by ringId void ringid_get_chiplet_properties( ChipletType_t i_chipletType, - ChipletData_t** o_chipletData); + ChipletData_t** o_cpltData, + GenRingIdList** o_ringComm, + GenRingIdList** o_ringInst, + RingVariantOrder** o_varOrder, + uint8_t* o_numVariants); + +// returns properties of a ring as determined by ringId +GenRingIdList* +_ringid_get_ring_list(RingId_t i_ringId); #endif // _CEN_RINGID_H_ diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.C b/src/import/chips/common/utils/imageProcs/common_ringId.C index d52c92072..c568468f8 100644 --- a/src/import/chips/common/utils/imageProcs/common_ringId.C +++ b/src/import/chips/common/utils/imageProcs/common_ringId.C @@ -34,7 +34,6 @@ namespace CEN_RID }; #include <p9_infrastruct_help.H> - // These strings must adhere precisely to the enum of PpeType. const char* ppeTypeName[] = { "SBE", "CME", @@ -76,7 +75,7 @@ static int get_ipl_ring_path_param( RingVariant_t i_ringVariant, char*& o_ringPa if (o_ringPath == NULL) { - MY_ERR("get_ipl_ring_path_param(): IPL env parm for ringVariant=%d not set\n", + MY_ERR("get_ipl_ring_path_param(): IPL env parm for ringVariant=0x%x not set.\n", i_ringVariant); return INFRASTRUCT_RC_ENV_ERROR; } @@ -119,7 +118,7 @@ static int get_runtime_ring_path_param( RingVariant_t i_ringVariant, char*& o_ri if (o_ringPath == NULL) { - MY_ERR("get_runtime_ring_path_param(): RUNTIME env parm for ringVariant(=%d) not set\n", + MY_ERR("get_runtime_ring_path_param(): RUNTIME env parm for ringVariant=0x%x not set.\n", i_ringVariant); return INFRASTRUCT_RC_ENV_ERROR; } @@ -155,7 +154,8 @@ int ringid_get_raw_ring_file_path( uint32_t i_magic, } else { - MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n", i_ringVariant, i_magic); + MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n", + i_ringVariant, i_magic); rc = TOR_INVALID_VARIANT; } @@ -186,7 +186,8 @@ int ringid_get_raw_ring_file_path( uint32_t i_magic, } else { - MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n", i_ringVariant, i_magic); + MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n", + i_ringVariant, i_magic); rc = TOR_INVALID_VARIANT; } @@ -207,7 +208,8 @@ int ringid_get_raw_ring_file_path( uint32_t i_magic, } else { - MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n", i_ringVariant, i_magic); + MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n", + i_ringVariant, i_magic); rc = TOR_INVALID_VARIANT; } @@ -226,7 +228,7 @@ int ringid_get_raw_ring_file_path( uint32_t i_magic, } else { - MY_ERR("Unsupported value of TOR magic(=0x%08x)\n", i_magic); + MY_ERR("Unsupported value of TOR magic(=0x%X)\n", i_magic); rc = TOR_INVALID_MAGIC_NUMBER; } @@ -239,26 +241,27 @@ int ringid_get_raw_ring_file_path( uint32_t i_magic, #endif // End of ifndef __HOSTBOOT_MODULE -int ringid_get_num_ring_ids( ChipId_t i_chipId, - RingId_t* o_numRingIds ) +int ringid_get_noof_ring_ids( ChipType_t i_chipType, + RingId_t* o_numRingIds) { int rc = INFRASTRUCT_RC_SUCCESS; - switch (i_chipId) + switch (i_chipType) { - case CID_P9N: - case CID_P9C: - case CID_P9A: + case CT_P9N: + case CT_P9C: + case CT_P9A: *o_numRingIds = P9_RID::NUM_RING_IDS; break; - case CID_CEN: + case CT_CEN: *o_numRingIds = CEN_RID::NUM_RING_IDS; break; default: - MY_ERR("ringid_get_num_ring_ids(): Unsupported chipId(=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; + MY_ERR("ringid_get_noof_ring_ids(): Unsupported chipType (=%d) supplied", + i_chipType); + rc = TOR_INVALID_CHIPTYPE; break; } @@ -266,108 +269,116 @@ int ringid_get_num_ring_ids( ChipId_t i_chipId, } -int ringid_get_num_chiplets( ChipId_t i_chipId, - uint32_t i_torMagic, - uint8_t* o_numChiplets ) +int ringid_get_ring_list( ChipType_t i_chipType, + RingId_t i_ringId, + GenRingIdList** o_ringIdList) { - switch (i_chipId) + int rc = INFRASTRUCT_RC_SUCCESS; + + switch (i_chipType) { - case CID_P9N: - case CID_P9C: - case CID_P9A: + case CT_P9N: + case CT_P9C: + case CT_P9A: + *o_ringIdList = P9_RID::_ringid_get_ring_list(i_ringId); + break; + + case CT_CEN: + *o_ringIdList = CEN_RID::_ringid_get_ring_list(i_ringId); + break; + + default: + MY_ERR("ringid_get_ring_list(): Unsupported chipType (=%d) supplied", + i_chipType); + rc = TOR_INVALID_CHIPTYPE; + break; + } + + return rc; +} + + +int ringid_get_noof_chiplets( ChipType_t i_chipType, + uint32_t i_torMagic, + uint8_t* o_numChiplets ) +{ + switch (i_chipType) + { + case CT_P9N: + case CT_P9C: + case CT_P9A: if ( i_torMagic == TOR_MAGIC_SBE || i_torMagic == TOR_MAGIC_OVRD || i_torMagic == TOR_MAGIC_OVLY ) { - *o_numChiplets = P9_RID::SBE_NUM_CHIPLETS; + *o_numChiplets = P9_RID::SBE_NOOF_CHIPLETS; } else if ( i_torMagic == TOR_MAGIC_CME ) { - *o_numChiplets = P9_RID::CME_NUM_CHIPLETS; + *o_numChiplets = P9_RID::CME_NOOF_CHIPLETS; } else if ( i_torMagic == TOR_MAGIC_SGPE ) { - *o_numChiplets = P9_RID::SGPE_NUM_CHIPLETS; + *o_numChiplets = P9_RID::SGPE_NOOF_CHIPLETS; } else { - MY_ERR("ringid_get_num_chiplets(): Invalid torMagic(=0x%08x) for chipId(=CID_P9x=%d)\n", i_torMagic, i_chipId); + MY_ERR("Invalid torMagic (=0x%08x) for chipType (=CT_P9x=%d)\n", i_torMagic, i_chipType); return TOR_INVALID_MAGIC_NUMBER; } break; - case CID_CEN: + case CT_CEN: if ( i_torMagic == TOR_MAGIC_CEN || i_torMagic == TOR_MAGIC_OVRD ) { - *o_numChiplets = CEN_RID::CEN_NUM_CHIPLETS; + *o_numChiplets = CEN_RID::CEN_NOOF_CHIPLETS; } else { - MY_ERR("Invalid torMagic(=0x%08x) for chipId(=CID_CEN)\n", i_torMagic); + MY_ERR("Invalid torMagic (=0x%08x) for chipType (=CT_CEN)\n", i_torMagic); return TOR_INVALID_MAGIC_NUMBER; } break; default: - MY_ERR("Invalid chipId(=%d)\n", i_chipId); - return TOR_INVALID_CHIP_ID; + MY_ERR("Invalid chipType (=0x%02x)\n", i_chipType); + return TOR_INVALID_CHIPTYPE; } return TOR_SUCCESS; } -int ringid_get_ringProps( ChipId_t i_chipId, - RingProperties_t** o_ringProps ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - *o_ringProps = (RingProperties_t*)&P9_RID::RING_PROPERTIES; - break; - - case CID_CEN: - *o_ringProps = (RingProperties_t*)&CEN_RID::RING_PROPERTIES; - break; - - default: - MY_ERR("ringid_get_ringProps(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - return rc; -} - - -int ringid_get_chipletProps( ChipId_t i_chipId, - uint32_t i_torMagic, - uint8_t i_torVersion, - ChipletType_t i_chipletType, - ChipletData_t** o_chipletData, - uint8_t* o_numVariants ) +int ringid_get_properties( ChipType_t i_chipType, + uint32_t i_torMagic, + uint8_t i_torVersion, + ChipletType_t i_chipletType, + ChipletData_t** o_chipletData, + GenRingIdList** o_ringIdListCommon, + GenRingIdList** o_ringIdListInstance, + RingVariantOrder** o_ringVariantOrder, + RingProperties_t** o_ringProps, + uint8_t* o_numVariants ) { - switch (i_chipId) + switch (i_chipType) { - case CID_P9N: - case CID_P9C: - case CID_P9A: + case CT_P9N: + case CT_P9C: + case CT_P9A: if ( i_torMagic == TOR_MAGIC_SBE || i_torMagic == TOR_MAGIC_OVRD || i_torMagic == TOR_MAGIC_OVLY ) { P9_RID::ringid_get_chiplet_properties( i_chipletType, - o_chipletData); - - *o_numVariants = (*o_chipletData)->numCommonRingVariants; + o_chipletData, + o_ringIdListCommon, + o_ringIdListInstance, + o_ringVariantOrder, + o_numVariants); if ( i_torVersion < 7 && (i_chipletType == P9_RID::EQ_TYPE || i_chipletType == P9_RID::EC_TYPE) ) @@ -384,7 +395,10 @@ int ringid_get_chipletProps( ChipId_t i_chipId, else if ( i_torMagic == TOR_MAGIC_CME ) { *o_chipletData = (ChipletData_t*)&P9_RID::EC::g_chipletData; - *o_numVariants = (*o_chipletData)->numCommonRingVariants; + *o_ringIdListCommon = (GenRingIdList*)P9_RID::EC::RING_ID_LIST_COMMON; + *o_ringIdListInstance = (GenRingIdList*)P9_RID::EC::RING_ID_LIST_INSTANCE; + *o_ringVariantOrder = (RingVariantOrder*)P9_RID::EC::RING_VARIANT_ORDER; + *o_numVariants = P9_RID::EC::g_chipletData.iv_num_common_ring_variants; if (i_torVersion < 7) { @@ -394,7 +408,10 @@ int ringid_get_chipletProps( ChipId_t i_chipId, else if ( i_torMagic == TOR_MAGIC_SGPE ) { *o_chipletData = (ChipletData_t*)&P9_RID::EQ::g_chipletData; - *o_numVariants = (*o_chipletData)->numCommonRingVariants; + *o_ringIdListCommon = (GenRingIdList*)P9_RID::EQ::RING_ID_LIST_COMMON; + *o_ringIdListInstance = (GenRingIdList*)P9_RID::EQ::RING_ID_LIST_INSTANCE; + *o_ringVariantOrder = (RingVariantOrder*)P9_RID::EQ::RING_VARIANT_ORDER; + *o_numVariants = P9_RID::EQ::g_chipletData.iv_num_common_ring_variants; if (i_torVersion < 7) { @@ -403,21 +420,25 @@ int ringid_get_chipletProps( ChipId_t i_chipId, } else { - MY_ERR("Invalid torMagic(=0x%08x) for chipId=CID_P9x=%d\n", i_torMagic, i_chipId); + MY_ERR("Invalid torMagic (=0x%08x) for chipType=CT_P9x=%d\n", i_torMagic, i_chipType); return TOR_INVALID_MAGIC_NUMBER; } + *o_ringProps = (RingProperties_t*)P9_RID::RING_PROPERTIES; + break; - case CID_CEN: + case CT_CEN: if ( i_torMagic == TOR_MAGIC_CEN || i_torMagic == TOR_MAGIC_OVRD ) { CEN_RID::ringid_get_chiplet_properties( i_chipletType, - o_chipletData); - - *o_numVariants = (*o_chipletData)->numCommonRingVariants; + o_chipletData, + o_ringIdListCommon, + o_ringIdListInstance, + o_ringVariantOrder, + o_numVariants); if ( i_torMagic == TOR_MAGIC_OVRD) { @@ -426,650 +447,19 @@ int ringid_get_chipletProps( ChipId_t i_chipId, } else { - MY_ERR("Invalid torMagic(=0x%08x) for chipId=CID_CEN\n", i_torMagic); - return TOR_INVALID_MAGIC_NUMBER; - } - - break; - - default: - MY_ERR("Invalid chipId(=%d)\n", i_chipId); - return TOR_INVALID_CHIP_ID; - - } - - return TOR_SUCCESS; -} - - -int ringid_get_scanScomAddr( ChipId_t i_chipId, - RingId_t i_ringId, - uint32_t* o_scanScomAddr ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - uint32_t l_scanScomAddr = UNDEFINED_SCOM_ADDR; - - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - if (i_ringId >= P9_RID::NUM_RING_IDS) - { - MY_ERR("ringid_get_scanScomAddr(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not" - " allowed\n", - i_ringId, P9_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - l_scanScomAddr = P9_RID::RING_PROPERTIES[i_ringId].scanScomAddr; - break; - - case CID_CEN: - if (i_ringId >= CEN_RID::NUM_RING_IDS) - { - MY_ERR("ringid_get_scanScomAddr(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not" - " allowed\n", - i_ringId, CEN_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - l_scanScomAddr = CEN_RID::RING_PROPERTIES[i_ringId].scanScomAddr; - break; - - default: - MY_ERR("ringid_get_scanScomAddr(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - *o_scanScomAddr = l_scanScomAddr; - - return rc; -} - - -int ringid_get_ringClass( ChipId_t i_chipId, - RingId_t i_ringId, - RingClass_t* o_ringClass ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - RingClass_t l_ringClass = UNDEFINED_RING_CLASS; - - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - if (i_ringId >= P9_RID::NUM_RING_IDS) - { - MY_ERR("ringid_get_ringClass(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n", - i_ringId, P9_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - l_ringClass = P9_RID::RING_PROPERTIES[i_ringId].ringClass; - break; - - case CID_CEN: - if (i_ringId >= CEN_RID::NUM_RING_IDS) - { - MY_ERR("ringid_get_ringClass(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n", - i_ringId, CEN_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - l_ringClass = CEN_RID::RING_PROPERTIES[i_ringId].ringClass; - break; - - default: - MY_ERR("ringid_get_ringClass(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - *o_ringClass = l_ringClass; - - return rc; -} - - -int ringid_check_ringId( ChipId_t i_chipId, - RingId_t i_ringId ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - if ( i_ringId >= P9_RID::NUM_RING_IDS && i_ringId != UNDEFINED_RING_ID ) - { - MY_ERR("ringid_check_ringId(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n", - i_ringId, P9_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - break; - - case CID_CEN: - if ( i_ringId >= CEN_RID::NUM_RING_IDS && i_ringId != UNDEFINED_RING_ID ) - { - MY_ERR("ringid_check_ringId(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n", - i_ringId, CEN_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - break; - - default: - MY_ERR("ringid_check_ringId(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - return rc; -} - - -int ringid_get_chipletIndex( ChipId_t i_chipId, - uint32_t i_torMagic, - ChipletType_t i_chipletType, - ChipletType_t* o_chipletIndex ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - if ( i_torMagic == TOR_MAGIC_SBE || - i_torMagic == TOR_MAGIC_OVRD || - i_torMagic == TOR_MAGIC_OVLY ) - { - if ( i_chipletType < P9_RID::SBE_NUM_CHIPLETS ) - { - *o_chipletIndex = i_chipletType; - } - else - { - rc = TOR_INVALID_CHIPLET_TYPE; - } - } - else if ( i_torMagic == TOR_MAGIC_CME ) - { - if ( i_chipletType == P9_RID::EC_TYPE ) - { - *o_chipletIndex = 0; - } - else - { - rc = TOR_INVALID_CHIPLET_TYPE; - } - } - else if ( i_torMagic == TOR_MAGIC_SGPE ) - { - if ( i_chipletType == P9_RID::EQ_TYPE ) - { - *o_chipletIndex = 0; - } - else - { - rc = TOR_INVALID_CHIPLET_TYPE; - } - } - else - { - MY_ERR("Invalid torMagic(=0x%08x) for chipId=CID_P9x=%d\n", i_torMagic, i_chipId); - return TOR_INVALID_MAGIC_NUMBER; - } - - break; - - case CID_CEN: - if ( i_torMagic == TOR_MAGIC_CEN || - i_torMagic == TOR_MAGIC_OVRD ) - { - if ( i_chipletType < CEN_RID::CEN_NUM_CHIPLETS ) - { - *o_chipletIndex = i_chipletType; - } - else - { - rc = TOR_INVALID_CHIPLET_TYPE; - } - } - else - { - MY_ERR("Invalid torMagic(=0x%08x) for chipId=CID_CEN\n", i_torMagic); + MY_ERR("Invalid torMagic (=0x%08x) for chipType=CT_CEN\n", i_torMagic); return TOR_INVALID_MAGIC_NUMBER; } - break; - - default: - MY_ERR("ringid_get_chipletIndex(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - return rc; -} - - -#if !defined(__PPE__) && !defined(NO_STD_LIB_IN_PPE) && !defined(__HOSTBOOT_MODULE) && !defined(FIPSODE) - -// The following defines are needed by the initCompiler and so it's practical to use C++ -// features. - -// ** Important ** -// If updates are made to the below three maps, corresponding updates to the two -// maps in ./tools/ifCompiler/initCompiler/initCompiler.y may also have to be made. -// @TODO: RTC192378 -// For P10 we should have just the two maps from initCompiler.y. And they should -// be located in central place like ./chips/common/utils/imageProcs/infrastructure. - -// Mapping from our [InfraStructure's} chipId to the chipType name -std::map <ChipId_t, std::string> chipIdIsMap -{ - { UNDEFINED_CHIP_ID, "" }, - { (ChipId_t)CID_CEN, "cen" }, - { (ChipId_t)CID_P9N, "p9n" }, - { (ChipId_t)CID_P9C, "p9c" }, - { (ChipId_t)CID_P9A, "p9a" } -}; - -// Mapping from chipType name to our [InfraStructure's} chipId (revers of above map) -std::map <std::string, ChipId_t> chipTypeIsMap -{ - { "", UNDEFINED_CHIP_ID }, - { "cen", (ChipId_t)CID_CEN }, - { "p9n", (ChipId_t)CID_P9N }, - { "p9c", (ChipId_t)CID_P9C }, - { "p9a", (ChipId_t)CID_P9A } -}; - -// Mapping from InitCompiler's chipId to InfraStructure's chipId -std::map <uint8_t, ChipId_t> chipIdIcToIsMap -{ - { 0x0, UNDEFINED_CHIP_ID }, - { 0x3, (ChipId_t)CID_CEN }, - { 0x5, (ChipId_t)CID_P9N }, - { 0x6, (ChipId_t)CID_P9C }, - { 0x7, (ChipId_t)CID_P9A } -}; - -int ringidGetRootRingId( ChipId_t i_chipId, - uint32_t i_scanScomAddr, - RingId_t& o_ringId, - bool i_bTest ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - RingProperties_t* ringProps = NULL; - RingId_t numRingIds = UNDEFINED_RING_ID; - RingId_t iRingId = UNDEFINED_RING_ID; // ringId loop counter - RingId_t l_ringId = UNDEFINED_RING_ID; - bool bFound = false; + *o_ringProps = (RingProperties_t*)CEN_RID::RING_PROPERTIES; - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - ringProps = (RingProperties_t*)&P9_RID::RING_PROPERTIES; - numRingIds = P9_RID::NUM_RING_IDS; - break; - - case CID_CEN: - ringProps = (RingProperties_t*)&CEN_RID::RING_PROPERTIES; - numRingIds = CEN_RID::NUM_RING_IDS; break; default: - MY_ERR("ringidGetRootRingId(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } + MY_ERR("Invalid chipType (=0x%02x)\n", i_chipType); + return TOR_INVALID_CHIPTYPE; - if (!rc) - { - for ( iRingId = 0; iRingId < numRingIds; iRingId++ ) - { - if ( ringProps[iRingId].scanScomAddr == i_scanScomAddr ) - { - if ( ringProps[iRingId].ringClass & RCLS_ROOT_RING ) - { - if (bFound) - { - MY_ERR("ringidGetRootRingId(): Two rings w/same addr cannot both be" - " ROOT_RING. Fix RING_PROPERTIES list for chipId=%d at ringId=0x%x" - " and ringId=0x%x\n", - i_chipId, l_ringId, iRingId); - rc = INFRASTRUCT_RC_CODE_BUG; - l_ringId = UNDEFINED_RING_ID; - break; - } - else - { - l_ringId = iRingId; - bFound = true; - - if (!i_bTest) - { - // Stop testing and break out of ringId loop - break; - } - - // Continue testing to see if duplicate root rings found - } - } - } - } } - if (!rc && !bFound) - { - MY_DBG("ringidGetRootRingId(): Did not find match for scanScomAddr=0x%08x for chipId=%d." - " (Note, l_ringId=0x%x better be equal to UNDEFINED_RING_ID=0x%x)\n", - i_scanScomAddr, i_chipId, l_ringId, UNDEFINED_RING_ID); - rc = TOR_SCOM_ADDR_NOT_FOUND; - } - - o_ringId = l_ringId; - - return rc; -} - - -int ringidGetRingId1( ChipId_t i_chipId, - std::string i_ringName, - RingId_t& o_ringId, - bool i_bTest ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - RingProperties_t* ringProps = NULL; - RingId_t numRingIds = UNDEFINED_RING_ID; - RingId_t iRingId = UNDEFINED_RING_ID; // ringId loop counter - RingId_t l_ringId = UNDEFINED_RING_ID; - bool bFound = false; - - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - ringProps = (RingProperties_t*)&P9_RID::RING_PROPERTIES; - numRingIds = P9_RID::NUM_RING_IDS; - break; - - case CID_CEN: - ringProps = (RingProperties_t*)&CEN_RID::RING_PROPERTIES; - numRingIds = CEN_RID::NUM_RING_IDS; - break; - - default: - MY_ERR("ringidGetRingId1(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - if (!rc) - { - for ( iRingId = 0; iRingId < numRingIds; iRingId++ ) - { - if ( !(i_ringName.compare(ringProps[iRingId].ringName)) ) - { - if (bFound) - { - MY_ERR("ringidGetRingId1(): Two rings cannot have the same ringName=%s. Fix" - " RING_PROPERTIES list for chipId=%d at ringId=0x%x and ringId=0x%x\n", - i_ringName.c_str(), i_chipId, l_ringId, iRingId); - rc = INFRASTRUCT_RC_CODE_BUG; - l_ringId = UNDEFINED_RING_ID; - break; - } - else - { - l_ringId = iRingId; - bFound = true; - - if (!i_bTest) - { - // Stop testing and break our of ringId loop - break; - } - - // Continue testing to see if duplicate ringNames found - } - } - } - } - - if (!rc && !bFound) - { - MY_DBG("ringidGetRingId1(): Did not find match to ringName=%s for chipId=%d." - " (Note, l_ringId=0x%x better be equal to UNDEFINED_RING_ID=0x%x)\n", - i_ringName.c_str(), i_chipId, l_ringId, UNDEFINED_RING_ID); - rc = TOR_RING_NAME_NOT_FOUND; - } - - o_ringId = l_ringId; - - return rc; -} - - -int ringidGetRingId2( ChipId_t i_chipId, - uint32_t i_torMagic, - ChipletType_t i_chipletType, // Ignored if only one chiplet in torMagic - uint8_t i_idxRing, // The effective ring index within chiplet's - // common or instance ring section - MyBool_t i_bInstCase, - RingId_t& o_ringId, - bool i_bTest ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - ChipletType_t l_chipletType = UNDEFINED_CHIPLET_TYPE; - RingProperties_t* ringProps = NULL; - RingId_t numRingIds = UNDEFINED_RING_ID; - RingId_t iRingId = UNDEFINED_RING_ID; // ringId loop counter - RingId_t l_ringId = UNDEFINED_RING_ID; - uint8_t l_idxRing = INVALID_RING_OFFSET; - bool bFound = false; - bool bOverlap = false; - - // First, select the main ring list we need (P9's or Centaur's). And while we're at it, - // convert input chipletType, which can be ignored for ring sections (i.e. torMagic) - // with only one chiplet, to a valid chipletType - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - ringProps = (RingProperties_t*)&P9_RID::RING_PROPERTIES; - numRingIds = P9_RID::NUM_RING_IDS; - - if ( i_torMagic == TOR_MAGIC_SBE || - i_torMagic == TOR_MAGIC_OVRD || - i_torMagic == TOR_MAGIC_OVLY ) - { - l_chipletType = i_chipletType; - } - else if ( i_torMagic == TOR_MAGIC_CME ) - { - l_chipletType = P9_RID::EC_TYPE; - } - else if ( i_torMagic == TOR_MAGIC_SGPE ) - { - l_chipletType = P9_RID::EQ_TYPE; - } - else - { - MY_ERR("Invalid torMagic(=0x%08x) for chipId=CID_P9x=%d\n", i_torMagic, i_chipId); - return TOR_INVALID_MAGIC_NUMBER; - } - - break; - - case CID_CEN: - ringProps = (RingProperties_t*)&CEN_RID::RING_PROPERTIES; - numRingIds = CEN_RID::NUM_RING_IDS; - - if ( i_torMagic == TOR_MAGIC_CEN || - i_torMagic == TOR_MAGIC_OVRD ) - { - l_chipletType = CEN_RID::CEN_TYPE; - } - else - { - MY_ERR("Invalid torMagic(=0x%08x) for chipId=CID_CEN\n", i_torMagic); - return TOR_INVALID_MAGIC_NUMBER; - } - - break; - - default: - MY_ERR("ringidGetRingId2(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - // Second, convert effective input ring index (which has no instance marker) to the - // common/instance specific index - l_idxRing = i_bInstCase ? - i_idxRing | INSTANCE_RING_MARK : - i_idxRing; - - if (!rc) - { - for ( iRingId = 0; iRingId < numRingIds; iRingId++ ) - { - if ( ringProps[iRingId].chipletType == l_chipletType && - ringProps[iRingId].idxRing == l_idxRing ) - { - if (bFound) - { - // Allow ring index overlap between a root and a non-root ring - // and let the non-root (i.e., the bucket ring) "win" - if ( !bOverlap && - ( (ringProps[iRingId].ringClass & RCLS_ROOT_RING) != - (ringProps[l_ringId].ringClass & RCLS_ROOT_RING) ) ) - { - if ( (ringProps[iRingId].ringClass & RCLS_ROOT_RING) != RCLS_ROOT_RING ) - { - l_ringId = iRingId; - } - else - { - // Keep l_ringId as is since it must already be the non-root ring - } - - bOverlap = true; // Indicate we found an overlap match - - if (!i_bTest) - { - // Stop testing and break our of ringId loop - break; - } - } - else - { - MY_ERR("ringidGetRingId2(): Two root, or two non-root, rings within a" - " chiplet (chipletType=%d) cannot have the same ring index" - " (idxRing=%d, bInst=%d). Fix RING_PROPERTIES list for chipId=%d" - " at ringId=0x%x and ringId=0x%x\n", - l_chipletType, i_idxRing, i_bInstCase, i_chipId, l_ringId, iRingId); - rc = INFRASTRUCT_RC_CODE_BUG; - l_ringId = UNDEFINED_RING_ID; - break; - } - } - else - { - l_ringId = iRingId; - bFound = true; // Indicate we found a first match - - // Continue searching for ring index overlap due to bucket ring or code bug - } - } - } - } - - if (!rc && !bFound) - { - MY_ERR("ringidGetRingId2(): Could not find a match for (chipId,chipletType,idxRing,bInst) =" - " (%d, %d, %d, %d). Fix RING_PROPERTIES list for chipId=%d (Note, l_ringId=0x%x" - " better be equal to UNDEFINED_RING_ID=0x%x)\n", - i_chipId, l_chipletType, i_idxRing, i_bInstCase, - i_chipId, l_ringId, UNDEFINED_RING_ID); - rc = INFRASTRUCT_RC_CODE_BUG; - } - - o_ringId = l_ringId; - - return rc; -} - - -int ringidGetRingName( ChipId_t i_chipId, - RingId_t i_ringId, - std::string& o_ringName ) -{ - int rc = INFRASTRUCT_RC_SUCCESS; - std::string l_ringName; - - switch (i_chipId) - { - case CID_P9N: - case CID_P9C: - case CID_P9A: - if (i_ringId >= P9_RID::NUM_RING_IDS) - { - MY_ERR("ringidGetRingName(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n", - i_ringId, P9_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - l_ringName = (std::string)P9_RID::RING_PROPERTIES[i_ringId].ringName; - break; - - case CID_CEN: - if (i_ringId >= CEN_RID::NUM_RING_IDS) - { - MY_ERR("ringidGetRingName(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n", - i_ringId, CEN_RID::NUM_RING_IDS); - rc = TOR_INVALID_RING_ID; - break; - } - - l_ringName = (std::string)CEN_RID::RING_PROPERTIES[i_ringId].ringName; - break; - - default: - MY_ERR("ringidGetRingName(): Unsupported chipId (=%d) supplied\n", i_chipId); - rc = TOR_INVALID_CHIP_ID; - break; - } - - o_ringName = l_ringName; - - return rc; -} - -int ringidGetRingClass( ChipId_t i_chipId, - RingId_t i_ringId, - RingClass_t& o_ringClass ) -{ - return (ringid_get_ringClass(i_chipId, i_ringId, &o_ringClass)); + return TOR_SUCCESS; } - -#endif // __PPE__ && NO_STD_LIB_IN_PPE diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.H b/src/import/chips/common/utils/imageProcs/common_ringId.H index de23bea0a..bef223357 100644 --- a/src/import/chips/common/utils/imageProcs/common_ringId.H +++ b/src/import/chips/common/utils/imageProcs/common_ringId.H @@ -42,24 +42,21 @@ // INFRASTRUCT TEAM. (These defs affect packing assumptions // of ring structures that go into the image ringSections.) typedef uint16_t RingId_t; // Type for RingID enum -typedef uint16_t RingClass_t; // Type for RingClass enum vectors used in non-SBE -typedef uint8_t ChipletType_t; // Type for Chiplets enum -typedef uint8_t PpeType_t; // Type for PpeType enum -typedef uint8_t ChipId_t; // Type for ChipId enum +typedef uint8_t ChipletType_t; // Type for CHIPLET_TYPE enum +typedef uint8_t PpeType_t; // Type for PpeType +typedef uint8_t ChipType_t; // Type for ChipType enum typedef uint8_t RingType_t; // Type for RingType enum typedef uint8_t RingVariant_t; // Type for RingVariant enum typedef uint8_t RingBlockType_t; // Type for RingBlockType enum, e.g. GET_SINGLE_RING typedef uint32_t TorCpltOffset_t; // Type for offset value to chiplet's CMN or INST section typedef uint8_t MyBool_t; // false:0, true:1, undefined:UNDEFINED_BOOLEAN -#define UNDEFINED_RING_ID (RingId_t)0xffff -#define UNDEFINED_SCOM_ADDR (uint32_t)0xffffffff -#define UNDEFINED_RING_CLASS (RingClass_t)0xffff -#define UNDEFINED_CHIPLET_TYPE (ChipletType_t)0xff -#define UNDEFINED_PPE_TYPE (PpeType_t)0xff -#define UNDEFINED_CHIP_ID (ChipId_t)0xff -#define INVALID_RING_TYPE (RingType_t)0xff -#define UNDEFINED_RING_VARIANT (RingVariant_t)0xff +#define UNDEFINED_RING_ID (RingId_t)0xffff +#define UNDEFINED_CHIPLET_TYPE (ChipletType_t)0xff +#define UNDEFINED_PPE_TYPE (PpeType_t)0xff +#define UNDEFINED_CHIP_TYPE (ChipType_t)0xff +#define INVALID_RING_TYPE (RingType_t)0xff +#define UNDEFINED_RING_VARIANT (RingVariant_t)0xff #define UNDEFINED_RING_BLOCK_TYPE (RingBlockType_t)0xff; #define UNDEFINED_DD_LEVEL (uint8_t)0xff @@ -85,12 +82,12 @@ typedef uint8_t MyBool_t; // false:0, true:1, undefined:UNDEFINED_BOOL // typedef struct { - uint32_t magic; // =TOR_MAGIC_xyz - uint8_t version; // =TOR_VERSION - ChipId_t chipId; // Value from ChipId enum - uint8_t ddLevel; // Actual DD level of ringSection - uint8_t undefined; - uint32_t size; // Size of ringSection. + uint32_t magic; // =TOR_MAGIC_xyz + uint8_t version; // =TOR version + ChipType_t chipType; // Value from ChipType enum + uint8_t ddLevel; // Actual DD level of ringSection + uint8_t undefined; + uint32_t size; // Size of ringSection. } TorHeader_t; // @@ -148,39 +145,57 @@ enum TorMagicNum // // Chip types and List to represent p9n, p9c, p9a, cen (centaur) // -enum ChipId +enum ChipType { - CID_P9N, - CID_P9C, - CID_P9A, - CID_CEN, - NUM_CHIP_IDS = 4 + CT_P9N, + CT_P9C, + CT_P9A, + CT_CEN, + NUM_CHIP_TYPES }; +typedef struct +{ + const char* name; + ChipType_t type; +} ChipTypeList_t; + +static const ChipTypeList_t CHIP_TYPE_LIST[] = +{ + {"p9n", CT_P9N}, + {"p9c", CT_P9C}, + {"p9a", CT_P9A}, + {"cen", CT_CEN}, +}; + + // -// Ring classes -// - Specified whether root ring: ROOT (only applied in RING_PROPERTIES list) -// - Specifies origination repo: EKB or MVPD -// - Specifies chip ID: P9 or Centaur -// - Specifies MVPD subclass: #G or #R -// - Specifies flush status assumption: Flushed or non-flushed (prev scanned) -// - Specifies various special ring classes: FSM, OVLY, STUMPED, CMSK +// Ring related data structs and types // -enum RingClass +typedef enum RingClass { - RCLS_ROOT_RING = 0b0000000000000001, // ENGD root ring marker bit - RCLS_FLUSH_RING = 0b0000000000000010, // Flush-scan marker bit - RCLS_NONFLUSH_RING = 0b0000000000000100, // Nonflush-scan marker bit - RCLS_EKB_FLUSH_RING = 0b0000000000001010, // EKB P9 ring. Flush-scanned - RCLS_EKB_NONFLUSH_RING = 0b0000000000001100, // EKB P9 ring. Nonflush-scanned - RCLS_MVPD_PDG_RING = 0b0000000000010010, // MVPD #G P9 ring. Flush-scanned - RCLS_MVPD_PDR_RING = 0b0000000000100010, // MVPD #R P9 ring. Flush-scanned - RCLS_EKB_CEN_RING = 0b0000000001000010, // EKB Cen ring. Flush-scanned - RCLS_EKB_FSM_RING = 0b0000000010000110, // EKB P9 ring for eq_ana_bndy. Mixed-scanned - RCLS_EKB_OVLY_RING = 0b0000000100010010, // EKB P9 ovly for MVPD GPTR ring. Flush-scanned - RCLS_EKB_STUMPED_RING = 0b0000001000000010, // EKB P9 CMSK stump ring. Flush-scanned - RCLS_EKB_CMSK_RING = 0b0000010000000010, // EKB P9 CMSK ring. Flush-scanned -}; + EKB_RING, + EKB_FSM_RING, + EKB_STUMPED_RING, + EKB_CMSK_RING, + EKB_NONFLUSH_RING, + VPD_RING, + CEN_RING, + NUM_RING_CLASSES +} RingClass_t; + +// +// General Ring ID list structure +// +typedef struct +{ + const char* ringName; + RingId_t ringId; + uint8_t instanceIdMin; + uint8_t instanceIdMax; + RingClass_t ringClass; + uint32_t scanScomAddress; +} GenRingIdList; // PPE types supported. // - This enum also reflects the order with which they appear in the HW image's .rings section. @@ -208,6 +223,16 @@ enum RingVariant NUM_RING_VARIANTS = 0x07, }; +extern const char* ppeTypeName[]; +extern const char* ringVariantName[]; + +// Variant order for Common rings +typedef struct +{ + RingVariant_t variant[NUM_RING_VARIANTS]; +} RingVariantOrder; + + // Ring types supported. // - This enum also reflects the order with which they appear in various images' .rings section. // - Do NOT make changes to the values or order of this enum. @@ -225,53 +250,44 @@ enum RingBlockType PUT_SINGLE_RING = 0x02 }; -extern const char* ppeTypeName[]; -extern const char* ringVariantName[]; - - -// -// Main ring properties structure -// - This structure is the basis for the RING_PROPERTIES list (further below) which, through the -// enumerated ringId index, associates (ringId, ringName, scanScomAddr, torOffset, chipletType) -// - For PPE we omit the ringName and scanScomAddr to save space in the SBE h-code. -// typedef struct { -#ifndef __PPE__ - char ringName[MAX_RING_NAME_LENGTH]; - uint32_t scanScomAddr; -#endif - uint8_t idxRing; - ChipletType_t chipletType; -#ifndef __PPE__ - RingClass_t ringClass; -#endif -} RingProperties_t; + // Chiplet ID of the first instance of the Chiplet + uint8_t iv_base_chiplet_number; -// -// Main chiplet properties structure -// -typedef struct -{ - // This is the instance ID range of the chiplet. - uint8_t chipletBaseId; // This is also the chiplet base ID for the COMMON rings in the chiplet - uint8_t numChipletInstances; // Num of chiplet instances - uint8_t numCommonRings; // Num of common rings - uint8_t numInstanceRings; // Num of instance rings (w/different ringId values) - uint8_t numInstanceRingsScanAddr; // Num of instance rings for (w/diff ringId && diff scanAddrs) - uint8_t numCommonRingVariants; // Num of Common rings variants. Only one for Instance rings - RingVariant_t ringVariantOrder[NUM_RING_VARIANTS]; // Order of ring variants in ring section + // Number of common rings for the Chiplet + uint8_t iv_num_common_rings; + + // Number of instance rings for the Chiplet (w/different ringId values) + uint8_t iv_num_instance_rings; + + // Number of instance rings for the Chiplet (w/different ringId values + // AND different scanAddress values) + uint8_t iv_num_instance_rings_scan_addrs; + + // Number of variants for common rings (instance rings only have BASE variant) + uint8_t iv_num_common_ring_variants; } ChipletData_t; // This is used to Set (Mark) the left-most bit #define INSTANCE_RING_MARK (uint8_t)0x80 // -// This is used to Clear the left-most bit +// This is used to Set (Mark) the left-most bit #define INSTANCE_RING_MASK (uint8_t)0x7F // This is used to mark an invalid ring in the ring properties list #define INVALID_RING_OFFSET (uint8_t)0xFF +// This structure is needed for mapping a RingID to it's corresponding name. +// The names will be used by the build scripts when generating the TOR. +typedef struct +{ + uint8_t iv_torOffSet; +#ifndef __PPE__ + char iv_name[MAX_RING_NAME_LENGTH]; +#endif + ChipletType_t iv_type; +} RingProperties_t; // @@ -291,32 +307,28 @@ typedef struct #define TOR_CODE_BUG INFRASTRUCT_RC_CODE_BUG #define TOR_USER_ERROR INFRASTRUCT_RC_USER_ERROR #define TOR_INVALID_MAGIC_NUMBER INFRASTRUCT_RC_NOOF_CODES + 1 -#define TOR_INVALID_CHIP_ID INFRASTRUCT_RC_NOOF_CODES + 3 -#define TOR_INVALID_CHIPLET_TYPE INFRASTRUCT_RC_NOOF_CODES + 4 +#define TOR_INVALID_CHIPTYPE INFRASTRUCT_RC_NOOF_CODES + 3 +#define TOR_INVALID_CHIPLET INFRASTRUCT_RC_NOOF_CODES + 4 #define TOR_INVALID_VARIANT INFRASTRUCT_RC_NOOF_CODES + 5 #define TOR_INVALID_RING_ID INFRASTRUCT_RC_NOOF_CODES + 6 #define TOR_INVALID_INSTANCE_ID INFRASTRUCT_RC_NOOF_CODES + 7 #define TOR_INVALID_RING_BLOCK_TYPE INFRASTRUCT_RC_NOOF_CODES + 8 #define TOR_UNSUPPORTED_RING_SECTION INFRASTRUCT_RC_NOOF_CODES + 9 -#define TOR_RING_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 10 // to be phased out -#define TOR_RING_IS_EMPTY INFRASTRUCT_RC_NOOF_CODES + 10 // non-fatal replace -#define TOR_RING_IS_POPULATED INFRASTRUCT_RC_NOOF_CODES + 11 -#define TOR_RING_HAS_NO_TOR_SLOT INFRASTRUCT_RC_NOOF_CODES + 12 // fatal replace -#define TOR_AMBIGUOUS_API_PARMS INFRASTRUCT_RC_NOOF_CODES + 13 -#define TOR_SECTION_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 14 -#define TOR_DD_LEVEL_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 15 -#define TOR_OP_BUFFER_INVALID INFRASTRUCT_RC_NOOF_CODES + 16 -#define TOR_OP_BUFFER_SIZE_EXCEEDED INFRASTRUCT_RC_NOOF_CODES + 17 -#define TOR_IMAGE_DOES_NOT_SUPPORT_CME INFRASTRUCT_RC_NOOF_CODES + 18 -#define TOR_IMAGE_DOES_NOT_SUPPORT_SGPE INFRASTRUCT_RC_NOOF_CODES + 19 -#define TOR_IMAGE_DOES_NOT_SUPPORT_DD_LEVEL INFRASTRUCT_RC_NOOF_CODES + 20 -#define TOR_IMAGE_DOES_NOT_SUPPORT_PPE_LEVEL INFRASTRUCT_RC_NOOF_CODES + 21 -#define TOR_BUFFER_TOO_SMALL INFRASTRUCT_RC_NOOF_CODES + 22 -#define TOR_TOO_MANY_DD_LEVELS INFRASTRUCT_RC_NOOF_CODES + 23 -#define TOR_OFFSET_TOO_BIG INFRASTRUCT_RC_NOOF_CODES + 24 -#define TOR_NO_RINGS_FOR_VARIANT INFRASTRUCT_RC_NOOF_CODES + 25 -#define TOR_SCOM_ADDR_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 26 -#define TOR_RING_NAME_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 27 +#define TOR_RING_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 10 +#define TOR_AMBIGUOUS_API_PARMS INFRASTRUCT_RC_NOOF_CODES + 11 +#define TOR_SECTION_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 12 +#define TOR_DD_LEVEL_NOT_FOUND INFRASTRUCT_RC_NOOF_CODES + 13 +#define TOR_OP_BUFFER_INVALID INFRASTRUCT_RC_NOOF_CODES + 14 +#define TOR_OP_BUFFER_SIZE_EXCEEDED INFRASTRUCT_RC_NOOF_CODES + 15 +#define TOR_IMAGE_DOES_NOT_SUPPORT_CME INFRASTRUCT_RC_NOOF_CODES + 16 +#define TOR_IMAGE_DOES_NOT_SUPPORT_SGPE INFRASTRUCT_RC_NOOF_CODES + 17 +#define TOR_IMAGE_DOES_NOT_SUPPORT_DD_LEVEL INFRASTRUCT_RC_NOOF_CODES + 18 +#define TOR_IMAGE_DOES_NOT_SUPPORT_PPE_LEVEL INFRASTRUCT_RC_NOOF_CODES + 19 +#define TOR_RING_AVAILABLE_IN_RINGSECTION INFRASTRUCT_RC_NOOF_CODES + 20 +#define TOR_BUFFER_TOO_SMALL INFRASTRUCT_RC_NOOF_CODES + 21 +#define TOR_TOO_MANY_DD_LEVELS INFRASTRUCT_RC_NOOF_CODES + 22 +#define TOR_OFFSET_TOO_BIG INFRASTRUCT_RC_NOOF_CODES + 23 +#define TOR_NO_RINGS_FOR_VARIANT INFRASTRUCT_RC_NOOF_CODES + 24 #ifndef __HOSTBOOT_MODULE // Only needed by ring_apply in EKB int ringid_get_raw_ring_file_path( uint32_t i_magic, @@ -324,100 +336,27 @@ int ringid_get_raw_ring_file_path( uint32_t i_magic, char* io_directory ); #endif -// This function returns the main ring properties list associated w/the chip ID. -int ringid_get_ringProps( ChipId_t i_chipId, - RingProperties_t** o_ringProps ); - -int ringid_get_chipletProps( ChipId_t i_chipId, - uint32_t i_torMagic, - uint8_t i_torVersion, - ChipletType_t i_chipletType, // Ignored if one chiplet in torMagic - ChipletData_t** o_chipletData, - uint8_t* o_numVariants); - -int ringid_get_num_ring_ids( ChipId_t i_chipId, - RingId_t* o_numRingIds); - -int ringid_get_num_chiplets( ChipId_t i_chipId, - uint32_t i_torMagic, - uint8_t* o_numChiplets ); - -// This function returns the scanScomAddr associated with the ringId. -int ringid_get_scanScomAddr( ChipId_t i_chipId, - RingId_t i_ringId, - uint32_t* o_scanScomAddr ); - -// This fumction returns the ringClass associated with the ringId. -int ringid_get_ringClass( ChipId_t i_chipId, - RingId_t i_ringId, - RingClass_t* o_ringClass ); - -// Check for valid chip ID and ring ID. -int ringid_check_ringId( ChipId_t i_chipId, - RingId_t i_ringId ); - -// Check and resolve the effective chipletType's index in a given TOR magic ring section -int ringid_get_chipletIndex( ChipId_t i_chipId, - uint32_t i_torMagic, - ChipletType_t i_chipletType, - ChipletType_t* o_chipletIndex ); - -#if !defined(__PPE__) && !defined(NO_STD_LIB_IN_PPE) && !defined(__HOSTBOOT_MODULE) && !defined(FIPSODE) - -// The following prototypes are needed by the initCompiler and so it's practical to use C++ -// features. - -#include <map> -#include <string> - -extern std::map <ChipId_t, std::string> chipIdIsMap; -extern std::map <std::string, ChipId_t> chipTypeIsMap; -extern std::map <uint8_t, ChipId_t> chipIdIcToIsMap; - -// This function returns the root ringId of a given scanScomAddr. -// Notes: -// - The "root" ringId is the ringId which has a ringName identical to that associated with the -// scanScomAddr in the engineering data (engd). -// - In IS's ring list, we can have multiple ringId for the same scanScomAddr since a ring may have -// multiple variations of itself, e.g. due to different frequency, filter or FSM settings, and -// which are identified through an "_bucket" extension on their ringName. All those rings, -// however, are non-ROOT_RINGs. -// - If the fully "qualified" unique ringId is required, then use ringidGetRingId1() and supply -// the ringName instead of the scanScomAddr. -// -int ringidGetRootRingId( ChipId_t i_chipId, - uint32_t i_scanScomAddr, - RingId_t& o_ringId, - bool i_bTest = false ); - -// This function returns the ringId associated with the ringName. -int ringidGetRingId1( ChipId_t i_chipId, - std::string i_ringName, - RingId_t& o_ringId, - bool i_bTest = false ); - -// This function returns the ringId associated with the effective ring index within a chiplet. -// (Note that "effective" means the index is void of the instance marker bit.) -int ringidGetRingId2( ChipId_t i_chipId, - uint32_t i_torMagic, - ChipletType_t i_chipletType, // Ignored if only one chiplet in torMagic - uint8_t i_idxRing, // The eEffective ring index within chiplet's - // common or instance ring section - MyBool_t i_bInstCase, // =0 common ring, =1 instance ring - RingId_t& o_ringId, - bool i_bTest = false ); - -// This function returns the ringName associated with the ringId. -int ringidGetRingName( ChipId_t i_chipId, - RingId_t i_ringId, - std::string& o_ringName ); - -// This fumction returns the ringClass associated with the ringId. -int ringidGetRingClass( ChipId_t i_chipId, - RingId_t i_ringId, - RingClass_t& o_ringClass ); - -#endif // __PPE__ && NO_STD_LIB_IN_PPE +int ringid_get_noof_ring_ids( ChipType_t i_chipType, + RingId_t* o_numRingIds); + +int ringid_get_noof_chiplets( ChipType_t i_chipType, + uint32_t i_torMagic, + uint8_t* o_numChiplets ); + +int ringid_get_ring_list( ChipType_t i_chipType, + RingId_t i_ringId, + GenRingIdList** o_ringIdList); + +int ringid_get_properties( ChipType_t i_chipType, + uint32_t i_torMagic, + uint8_t i_torVersion, + ChipletType_t i_chipletType, + ChipletData_t** o_chipletData, + GenRingIdList** o_ringIdListCommon, + GenRingIdList** o_ringIdListInstance, + RingVariantOrder** o_ringVariantOrder, + RingProperties_t** o_ringProps, + uint8_t* o_numVariants); #endif // _COMMON_RINGID_H_ diff --git a/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C b/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C index 8b136040d..851e66dd1 100644 --- a/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C +++ b/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C @@ -424,6 +424,7 @@ extern "C" return fapi2::current_err; } + // Returns a matching MVPD ring in RS4 format at given buffer address, // NULL otherwise. // Adjusts buffer pointer and remaining length for the consumed portion diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C index 4bd11906e..18a10c5b5 100644 --- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C +++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C @@ -308,7 +308,7 @@ fapi2::ReturnCode get_overlays_ring( io_ringBuf2, //Has RS4 Gptr overlay ring on return l_ringBlockSize); - if (l_rc == TOR_SUCCESS) + if (l_rc == INFRASTRUCT_RC_SUCCESS) { FAPI_DBG("Successfully found Gptr ringId=0x%x of iv_size=%d bytes", i_ringId, be16toh(((CompressedScanData*)(*io_ringBuf2))->iv_size)); @@ -342,7 +342,7 @@ fapi2::ReturnCode get_overlays_ring( } else { - FAPI_ASSERT( l_rc == TOR_RING_IS_EMPTY, + FAPI_ASSERT( l_rc == TOR_RING_NOT_FOUND, fapi2::XIPC_GPTR_GET_SINGLE_RING_ERROR(). set_CHIP_TARGET(i_procTarget). set_RING_ID(i_ringId). @@ -560,7 +560,8 @@ fapi2::ReturnCode process_gptr_rings( RingId_t l_vpdRingId = (RingId_t)be16toh(((CompressedScanData*)io_vpdRing)->iv_ringId); uint32_t l_vpdScanAddr = be32toh(((CompressedScanData*)io_vpdRing)->iv_scanAddr); - FAPI_DBG("process_gptr_rings(): Processing ringId=0x%x", l_vpdRingId); + FAPI_DBG("Entering process_gptr_rings"); + FAPI_DBG("Processing GPTR ringId=0x%x", l_vpdRingId); // Used for getting Gptr ring from overlays section void* l_ovlyRs4Ring = io_ringBuf2; //This content will be destroyed later in this function! @@ -692,6 +693,8 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings( fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; int l_rc = 0; + FAPI_DBG("Entering _fetch_and_insert_vpd_ring"); + FAPI_INF("_fetch_and_insert_vpd_ring: (ringId,chipletId) = (0x%02X,0x%02x)", i_ring.ringId, i_chipletId); @@ -918,8 +921,8 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings( set_TOR_RC(l_rc). set_RING_ID(i_ring.ringId). set_OCCURRENCE(1), - "tor_append_ring() failed in sysPhase=%d w/rc=%d for ringId=0x%x", - i_sysPhase, l_rc, i_ring.ringId ); + "tor_append_ring() failed in phase %d w/l_rc=%d for ringId=0x%x", + l_ppeType, l_rc, i_ring.ringId ); FAPI_INF("Successfully added VPD ring: (ringId,evenOdd,chipletId)=(0x%02X,0x%X,0x%02X)", i_ring.ringId, i_evenOdd, i_chipletId); @@ -1876,7 +1879,8 @@ ReturnCode p9_xip_customize ( MyBool_t l_bDdSupport = UNDEFINED_BOOLEAN; - FAPI_IMP ("Entering p9_xip_customize w/sysPhase=%d...", i_sysPhase); + + FAPI_DBG ("Entering p9_xip_customize w/sysPhase=%d...", i_sysPhase); // Make copy of the requested bootCoreMask @@ -1885,7 +1889,7 @@ ReturnCode p9_xip_customize ( //------------------------------------------- // Check some input buffer parameters: - // - sysPhase is checked later + // - sysPhase, modeBuild are checked later // - log the initial image size // - more buffer size checks in big switch() //------------------------------------------- @@ -2596,6 +2600,7 @@ ReturnCode p9_xip_customize ( l_rc = tor_get_block_of_rings( l_hwRingsSection, attrDdLevel, l_ppeType, + UNDEFINED_RING_VARIANT, &io_ringSectionBuf, io_ringSectionBufSize ); diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H index 3771af093..06490cb17 100644 --- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H +++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,19 +28,6 @@ #ifndef WIN32 #include <fapi2.H> -#define NUM_OF_CORES (uint8_t)24 -#define NUM_OF_CMES (uint8_t)12 -#define NUM_OF_QUADS (uint8_t) 6 -#define CORES_PER_QUAD (NUM_OF_CORES/NUM_OF_QUADS) - -enum SYSPHASE -{ - SYSPHASE_HB_SBE = 0, - SYSPHASE_RT_CME = 1, - SYSPHASE_RT_SGPE = 2, - NOOF_SYSPHASES = 3, -}; - typedef fapi2::ReturnCode (*p9_xip_customize_FP_t) ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target, void* i_hwImage, @@ -96,7 +83,7 @@ extern "C" /// In: >=MAX_SBE_SEEPROM_SIZE /// Out: Final size /// @param[in] i_sysPhase => ={HB_SBE, RT_CME, RT_SGPE} -/// @param[in] i_modeBuild => ={IPL, REBUILD} - Not used in P9 +/// @param[in] i_modeBuild => ={IPL, REBUILD} /// @param[in] i_ringBuf1 => Caller supplied in-memory buffer /// for VPD rings /// @param[in] i_ringBufSize1 => Max size of VPD ring buffer diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 1388a077c..0e3d59a29 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -63,8 +63,8 @@ namespace p9_hcodeImageBuild * @brief returns maximum quad common rings that enter HOMER. */ -#define MAX_HOMER_QUAD_CMN_RINGS (uint32_t)(EQ::g_chipletData.numCommonRings - 4) -#define MAX_HOMER_CORE_CMN_RINGS (uint32_t)(EC::g_chipletData.numCommonRings - 2) +#define MAX_HOMER_QUAD_CMN_RINGS (uint32_t)(EQ::g_chipletData.iv_num_common_rings - 4) +#define MAX_HOMER_CORE_CMN_RINGS (uint32_t)(EC::g_chipletData.iv_num_common_rings - 2) /** * @brief models QPMR header in HOMER diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 36c5d3903..fa0340fac 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -1975,7 +1975,7 @@ uint32_t getPpeScanRings( void* const i_pHwImage, i_ringData.iv_pRingBuffer, i_ringData.iv_ringBufSize, (i_ppeType == PLAT_CME) ? SYSPHASE_RT_CME : SYSPHASE_RT_SGPE, - 0, // Was MODEBUILD_IPL=0 but not used in P9 + MODEBUILD_IPL, i_ringData.iv_pWorkBuf1, i_ringData.iv_sizeWorkBuf1, i_ringData.iv_pWorkBuf2, @@ -2066,7 +2066,7 @@ uint32_t getPpeScanRings( void* const i_pHwImage, tempBufSize, i_debugMode ); - if( TOR_RING_IS_EMPTY == rc ) + if( TOR_RING_NOT_FOUND == rc ) { tempBufSize = 0; continue; @@ -2558,9 +2558,9 @@ fapi2::ReturnCode layoutCmnRingsForCme( Homerlayout_t* i_pHomer, ringSize, i_debugMode ); - if( TOR_RING_IS_EMPTY == rc ) + if( TOR_RING_NOT_FOUND == rc ) { - FAPI_INF( "Core common ring %s has no content", + FAPI_INF( "Did not find core common ring %s ", io_cmeRings.getRingName( coreCmnRingId ) ); ringSize = 0; continue; @@ -2675,7 +2675,7 @@ fapi2::ReturnCode layoutInstRingsForCme( Homerlayout_t* i_pHomer, tempSize, i_debugMode ); - if( TOR_RING_IS_EMPTY == rc ) + if( TOR_RING_NOT_FOUND == rc ) { FAPI_DBG( "could not determine size of ring id %d of core %d", io_cmeRings.getInstRingId(0), ((2 * exId) + coreId) ); @@ -2739,9 +2739,9 @@ fapi2::ReturnCode layoutInstRingsForCme( Homerlayout_t* i_pHomer, tempSize, i_debugMode ); - if( TOR_RING_IS_EMPTY == rc ) + if( TOR_RING_NOT_FOUND == rc ) { - FAPI_INF("Instance ring Id %d has no content for EX %d core %d", + FAPI_INF("Instance ring Id %d not found for EX %d core %d", io_cmeRings.getInstRingId(0), exId, coreId ); tempSize = 0; continue; @@ -2849,7 +2849,7 @@ fapi2::ReturnCode layoutCmeScanOverride( Homerlayout_t* i_pHomer, tempBufSize, i_debugMode ); - if( TOR_RING_IS_EMPTY == rc ) + if( TOR_RING_NOT_FOUND == rc ) { tempBufSize = 0; continue; @@ -3218,9 +3218,9 @@ fapi2::ReturnCode layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, i_debugMode ); - if( TOR_RING_IS_EMPTY == rc ) + if( TOR_RING_NOT_FOUND == rc ) { - FAPI_INF( "Quad common ring %s has no content", + FAPI_INF( "did not find quad common ring %s", io_sgpeRings.getRingName( torRingId ) ); tempBufSize = 0; continue; @@ -3317,7 +3317,7 @@ fapi2::ReturnCode layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, uint32_t tempBufSize = 0; uint32_t tempLength = 0; - for( uint32_t ringIndex = 0; ringIndex < EQ::g_chipletData.numInstanceRingsScanAddr; + for( uint32_t ringIndex = 0; ringIndex < EQ::g_chipletData.iv_num_instance_rings_scan_addrs; ringIndex++ ) { tempBufSize = i_ringData.iv_sizeWorkBuf1; @@ -3334,9 +3334,9 @@ fapi2::ReturnCode layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, tempBufSize, i_debugMode ); - if( TOR_RING_IS_EMPTY == rc ) + if( TOR_RING_NOT_FOUND == rc ) { - FAPI_DBG( "Quad spec ring %s has no content for cache Inst %d", + FAPI_DBG( "did not find quad spec ring %s for cache Inst %d", io_sgpeRings.getRingName( quadSpecRingId ), cacheInst ); tempBufSize = 0; continue; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C index 81ad2ad05..def3c096b 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C @@ -271,7 +271,7 @@ RingBucket::RingBucket( PlatId i_plat, uint8_t* i_pRingStart, RingDebugMode_t i_ iv_cmnRingMap[ringIndex] = l_quadCmnRings[ringIndex]; } - for( ringIndex = 0; ringIndex < ( EQ::g_chipletData.numInstanceRingsScanAddr * MAX_QUADS_PER_CHIP ); + for( ringIndex = 0; ringIndex < ( EQ::g_chipletData.iv_num_instance_rings_scan_addrs * MAX_QUADS_PER_CHIP ); ringIndex++ ) { iv_instRingMap[ringIndex] = l_quadSpecRings[ringIndex]; @@ -643,12 +643,12 @@ void RingBucket::dumpRings( ) if( iv_plat == PLAT_CME ) { FAPI_INF("---------------------------------CME Rings---------------------------------------"); - chipletNo = EC::g_chipletData.numInstanceRingsScanAddr; + chipletNo = EC::g_chipletData.iv_num_instance_rings_scan_addrs; } else if( iv_plat == PLAT_SGPE ) { FAPI_INF("---------------------------------SGPE Rings--------------------------------------"); - chipletNo = EQ::g_chipletData.numInstanceRingsScanAddr; + chipletNo = EQ::g_chipletData.iv_num_instance_rings_scan_addrs; } else { diff --git a/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H b/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H index b644996e3..736f6025b 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H +++ b/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -52,9 +52,30 @@ const uint32_t MAX_HBBL_SIZE = 20 * 1024; // Max hbbl section siz const uint32_t MAX_NOOF_DD_LEVELS_IN_IMAGE = 20; +//@FIXME: CMO: Aren't these defined somewhere else? +#define NUM_OF_CORES (uint8_t)24 +#define NUM_OF_CMES (uint8_t)12 +#define NUM_OF_QUADS (uint8_t) 6 +#define CORES_PER_QUAD (NUM_OF_CORES/NUM_OF_QUADS) + #define INSTANCE_ID_MIN (uint8_t)0x01 #define INSTANCE_ID_MAX (uint8_t)0x37 +enum SYSPHASE +{ + SYSPHASE_HB_SBE = 0, + SYSPHASE_RT_CME = 1, + SYSPHASE_RT_SGPE = 2, + NOOF_SYSPHASES = 3, +}; + +enum MODEBUILD +{ + MODEBUILD_IPL = 0, + MODEBUILD_REBUILD = 1, + NOOF_MODEBUILDS = 2, +}; + #if defined(__FAPI) #include <fapi2.H> #define MY_INF(_fmt_, _args_...) FAPI_INF(_fmt_, ##_args_) diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.C b/src/import/chips/p9/utils/imageProcs/p9_ringId.C index fb81d8c67..3d188e340 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.C +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.C @@ -28,84 +28,642 @@ namespace P9_RID { + #include "p9_ringId.H" + + +namespace PERV +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"perv_fure" , 0x00, 0x01, 0x01, EKB_RING , 0x0103400F}, + {"perv_gptr" , 0x01, 0x01, 0x01, EKB_RING , 0x01034002}, + {"perv_time" , 0x02, 0x01, 0x01, VPD_RING , 0x01034007}, + {"occ_fure" , 0x03, 0x01, 0x01, EKB_RING , 0x0103080F}, + {"occ_gptr" , 0x04, 0x01, 0x01, EKB_RING , 0x01030802}, + {"occ_time" , 0x05, 0x01, 0x01, VPD_RING , 0x01030807}, + {"perv_ana_func" , 0x06, 0x01, 0x01, EKB_RING , 0x01030400}, + {"perv_ana_gptr" , 0x07, 0x01, 0x01, EKB_RING , 0x01030402}, + {"perv_pll_gptr" , 0x08, 0x01, 0x01, EKB_RING , 0x01030012}, + {"perv_pll_bndy_bucket_1", 0x09, 0x01, 0x01, EKB_RING , 0x01030018}, + {"perv_pll_bndy_bucket_2", 0x0a, 0x01, 0x01, EKB_RING , 0x01030018}, + {"perv_pll_bndy_bucket_3", 0x0b, 0x01, 0x01, EKB_RING , 0x01030018}, + {"perv_pll_bndy_bucket_4", 0x0c, 0x01, 0x01, EKB_RING , 0x01030018}, + {"perv_pll_bndy_bucket_5", 0x0d, 0x01, 0x01, EKB_RING , 0x01030018}, + {"perv_pll_func" , 0x0e, 0x01, 0x01, EKB_RING , 0x01030010}, + {"perv_pll_bndy_flt_1" , 0x0f, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, + {"perv_pll_bndy_flt_2" , 0x10, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, + {"perv_pll_bndy_flt_3" , 0x11, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, + {"perv_pll_bndy_flt_4" , 0x12, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, + {"sbe_fure" , 0x13, 0x01, 0x01, EKB_RING , 0x0103020F}, + {"sbe_gptr" , 0x14, 0x01, 0x01, EKB_RING , 0x01030202}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"perv_repr" , 0x15, 0x01, 0x01, VPD_RING , 0x01034006}, + {"occ_repr" , 0x16, 0x01, 0x01, VPD_RING , 0x01030806}, + {"sbe_repr" , 0x17, 0x01, 0x01, VPD_RING , 0x01030206}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; }; +namespace N0 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"n0_fure" , 0x00, 0x02, 0x02, EKB_RING , 0x02034E0F}, + {"n0_gptr" , 0x01, 0x02, 0x02, EKB_RING , 0x02034E02}, + {"n0_time" , 0x02, 0x02, 0x02, VPD_RING , 0x02034E07}, + {"n0_nx_fure" , 0x03, 0x02, 0x02, EKB_RING , 0x0203200F}, + {"n0_nx_gptr" , 0x04, 0x02, 0x02, EKB_RING , 0x02032002}, + {"n0_nx_time" , 0x05, 0x02, 0x02, VPD_RING , 0x02032007}, + {"n0_cxa0_fure" , 0x06, 0x02, 0x02, EKB_RING , 0x0203100F}, + {"n0_cxa0_gptr" , 0x07, 0x02, 0x02, EKB_RING , 0x02031002}, + {"n0_cxa0_time" , 0x08, 0x02, 0x02, VPD_RING , 0x02031007}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"n0_repr" , 0x09, 0x02, 0x02, VPD_RING , 0x02034E06}, + {"n0_nx_repr" , 0x0a, 0x02, 0x02, VPD_RING , 0x02032006}, + {"n0_cxa0_repr" , 0x0b, 0x02, 0x02, VPD_RING , 0x02031006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace N1 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"n1_fure" , 0x00, 0x03, 0x03, EKB_RING , 0x0303700F}, + {"n1_gptr" , 0x01, 0x03, 0x03, EKB_RING , 0x03037002}, + {"n1_time" , 0x02, 0x03, 0x03, VPD_RING , 0x03037007}, + {"n1_ioo0_fure" , 0x03, 0x03, 0x03, EKB_RING , 0x0303080F}, + {"n1_ioo0_gptr" , 0x04, 0x03, 0x03, EKB_RING , 0x03030802}, + {"n1_ioo0_time" , 0x05, 0x03, 0x03, VPD_RING , 0x03030807}, + {"n1_ioo1_fure" , 0x06, 0x03, 0x03, EKB_RING , 0x0303040F}, + {"n1_ioo1_gptr" , 0x07, 0x03, 0x03, EKB_RING , 0x03030402}, + {"n1_ioo1_time" , 0x08, 0x03, 0x03, VPD_RING , 0x03030407}, + {"n1_mcs23_fure" , 0x09, 0x03, 0x03, EKB_RING , 0x0303020F}, + {"n1_mcs23_gptr" , 0x0a, 0x03, 0x03, EKB_RING , 0x03030202}, + {"n1_mcs23_time" , 0x0b, 0x03, 0x03, VPD_RING , 0x03030207}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"n1_repr" , 0x0c, 0x03, 0x03, VPD_RING , 0x03037006}, + {"n1_ioo0_repr" , 0x0d, 0x03, 0x03, VPD_RING , 0x03030806}, + {"n1_ioo1_repr" , 0x0e, 0x03, 0x03, VPD_RING , 0x03030406}, + {"n1_mcs23_repr" , 0x0f, 0x03, 0x03, VPD_RING , 0x03030206}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace N2 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"n2_fure" , 0x00, 0x04, 0x04, EKB_RING , 0x04035C0F}, + {"n2_gptr" , 0x01, 0x04, 0x04, EKB_RING , 0x04035C02}, + {"n2_time" , 0x02, 0x04, 0x04, VPD_RING , 0x04035C07}, + {"n2_cxa1_fure" , 0x03, 0x04, 0x04, EKB_RING , 0x0403200F}, + {"n2_cxa1_gptr" , 0x04, 0x04, 0x04, EKB_RING , 0x04032002}, + {"n2_cxa1_time" , 0x05, 0x04, 0x04, VPD_RING , 0x04032007}, + {"n2_psi_fure" , 0x06, 0x04, 0x04, EKB_RING , 0x0403020F}, + {"n2_psi_gptr" , 0x07, 0x04, 0x04, EKB_RING , 0x04030202}, + {"n2_psi_time" , 0x08, 0x04, 0x04, VPD_RING , 0x04030207}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"n2_repr" , 0x09, 0x04, 0x04, VPD_RING , 0x04035C06}, + {"n2_cxa1_repr" , 0x0a, 0x04, 0x04, VPD_RING , 0x04032006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace N3 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"n3_fure" , 0x00, 0x05, 0x05, EKB_RING , 0x0503660F}, + {"n3_gptr" , 0x01, 0x05, 0x05, EKB_RING , 0x05037602}, + {"n3_time" , 0x02, 0x05, 0x05, VPD_RING , 0x05037607}, + {"n3_mcs01_fure" , 0x03, 0x05, 0x05, EKB_RING , 0x0503010F}, + {"n3_mcs01_gptr" , 0x04, 0x05, 0x05, EKB_RING , 0x05030102}, + {"n3_mcs01_time" , 0x05, 0x05, 0x05, VPD_RING , 0x05030107}, + {"n3_np_fure" , 0x06, 0x05, 0x05, EKB_RING , 0x0503080F}, + {"n3_np_gptr" , 0x07, 0x05, 0x05, EKB_RING , 0x05030802}, + {"n3_np_time" , 0x08, 0x05, 0x05, VPD_RING , 0x05030807}, + {"n3_br_fure" , 0x09, 0x05, 0x05, EKB_RING , 0x0503100F}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"n3_repr" , 0x0a, 0x05, 0x05, VPD_RING , 0x05037606}, + {"n3_mcs01_repr" , 0x0b, 0x05, 0x05, VPD_RING , 0x05030106}, + {"n3_np_repr" , 0x0c, 0x05, 0x05, VPD_RING , 0x05030806}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace XB +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"xb_fure" , 0x00, 0x06, 0x06, EKB_RING , 0x0603440F}, + {"xb_gptr" , 0x01, 0x06, 0x06, EKB_RING , 0x06034402}, + {"xb_time" , 0x02, 0x06, 0x06, VPD_RING , 0x06034407}, + {"xb_io0_fure" , 0x03, 0x06, 0x06, EKB_RING , 0x0603220F}, + {"xb_io0_gptr" , 0x04, 0x06, 0x06, EKB_RING , 0x06032202}, + {"xb_io0_time" , 0x05, 0x06, 0x06, VPD_RING , 0x06032207}, + {"xb_io1_fure" , 0x06, 0x06, 0x06, EKB_RING , 0x0603110F}, + {"xb_io1_gptr" , 0x07, 0x06, 0x06, EKB_RING , 0x06031102}, + {"xb_io1_time" , 0x08, 0x06, 0x06, VPD_RING , 0x06031107}, + {"xb_io2_fure" , 0x09, 0x06, 0x06, EKB_RING , 0x0603088F}, + {"xb_io2_gptr" , 0x0a, 0x06, 0x06, EKB_RING , 0x06030882}, + {"xb_io2_time" , 0x0b, 0x06, 0x06, VPD_RING , 0x06030887}, + {"xb_pll_gptr" , 0x0c, 0x06, 0x06, EKB_RING , 0x06030012}, + {"xb_pll_bndy" , 0x0d, 0x06, 0x06, EKB_RING , 0x06030018}, + {"xb_pll_func" , 0x0e, 0x06, 0x06, EKB_RING , 0x06030010}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"xb_repr" , 0x13, 0x06, 0x06, VPD_RING , 0x06034406}, + {"xb_io0_repr" , 0x14, 0x06, 0x06, VPD_RING , 0x06032206}, + {"xb_io1_repr" , 0x15, 0x06, 0x06, VPD_RING , 0x06031106}, + {"xb_io2_repr" , 0x16, 0x06, 0x06, VPD_RING , 0x06030886}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace MC +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"mc_fure" , 0x00, 0x07, 0x07, EKB_RING , 0x0703600F}, + {"mc_gptr" , 0x01, 0x07, 0x07, EKB_RING , 0x07036002}, + {"mc_time" , 0x02, 0x07, 0x07, VPD_RING , 0x07036007}, + {"mc_iom01_fure" , 0x03, 0x07, 0x07, EKB_RING , 0x0703100F}, + {"mc_iom01_gptr" , 0x04, 0x07, 0x07, EKB_RING , 0x07031002}, + {"mc_iom01_time" , 0x05, 0x07, 0x07, VPD_RING , 0x07031007}, + {"mc_iom23_fure" , 0x06, 0x07, 0x07, EKB_RING , 0x0703080F}, + {"mc_iom23_gptr" , 0x07, 0x07, 0x07, EKB_RING , 0x07030802}, + {"mc_iom23_time" , 0x08, 0x07, 0x07, VPD_RING , 0x07030807}, + {"mc_pll_gptr" , 0x09, 0x07, 0x07, EKB_RING , 0x07030012}, + {"mc_pll_bndy_bucket_1", 0x0a, 0x07, 0x07, EKB_RING , 0x07030018}, + {"mc_pll_bndy_bucket_2", 0x0b, 0x07, 0x07, EKB_RING , 0x07030018}, + {"mc_pll_bndy_bucket_3", 0x0c, 0x07, 0x07, EKB_RING , 0x07030018}, + {"mc_pll_bndy_bucket_4", 0x0d, 0x07, 0x07, EKB_RING , 0x07030018}, + {"mc_pll_bndy_bucket_5", 0x0e, 0x07, 0x07, EKB_RING , 0x07030018}, + {"mc_pll_func" , 0x0f, 0x07, 0x07, EKB_RING , 0x07030010}, + {"mc_omi0_fure" , 0x10, 0x07, 0x08, EKB_RING , 0x0703100F}, + {"mc_omi0_gptr" , 0x11, 0x07, 0x07, EKB_RING , 0x07031002}, + {"mc_omi1_fure" , 0x12, 0x07, 0x07, EKB_RING , 0x0703080F}, + {"mc_omi1_gptr" , 0x13, 0x07, 0x07, EKB_RING , 0x07030802}, + {"mc_omi2_fure" , 0x14, 0x07, 0x07, EKB_RING , 0x0703040F}, + {"mc_omi2_gptr" , 0x15, 0x07, 0x07, EKB_RING , 0x07030402}, + {"mc_omippe_fure" , 0x16, 0x07, 0x07, EKB_RING , 0x0703020F}, + {"mc_omippe_gptr" , 0x17, 0x07, 0x07, EKB_RING , 0x07030202}, + {"mc_omippe_time" , 0x18, 0x07, 0x07, VPD_RING , 0x07030207}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"mc_repr" , 0x19, 0x07, 0x08, VPD_RING , 0x07036006}, + {"mc_iom23_repr" , 0x1a, 0x07, 0x08, VPD_RING , 0x07030806}, + {"mc_omippe_repr" , 0x1b, 0x07, 0x08, VPD_RING , 0x07030206}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace OB0 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"ob0_pll_bndy_bucket_1" , 0x00, 0x09, 0x09, EKB_RING , 0x09030018}, + {"ob0_pll_bndy_bucket_2" , 0x01, 0x09, 0x09, EKB_RING , 0x09030018}, + {"ob0_gptr" , 0x02, 0x09, 0x09, EKB_RING , 0x09037002}, + {"ob0_time" , 0x03, 0x09, 0x09, VPD_RING , 0x09037007}, + {"ob0_pll_gptr" , 0x04, 0x09, 0x09, EKB_RING , 0x09030012}, + {"ob0_fure" , 0x05, 0x09, 0x09, EKB_RING , 0x0903700F}, + {"ob0_pll_bndy_bucket_3" , 0x06, 0x09, 0x09, EKB_RING , 0x09030018}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"ob0_repr" , 0x07, 0x09, 0x09, VPD_RING , 0x09037006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace OB1 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"ob1_pll_bndy_bucket_1" , 0x00, 0x0a, 0x0a, EKB_RING , 0x0A030018}, + {"ob1_pll_bndy_bucket_2" , 0x01, 0x0a, 0x0a, EKB_RING , 0x0A030018}, + {"ob1_gptr" , 0x02, 0x0a, 0x0a, EKB_RING , 0x0A037002}, + {"ob1_time" , 0x03, 0x0a, 0x0a, VPD_RING , 0x0A037007}, + {"ob1_pll_gptr" , 0x04, 0x0a, 0x0a, EKB_RING , 0x0A030012}, + {"ob1_fure" , 0x05, 0x0a, 0x0a, EKB_RING , 0x0A03700F}, + {"ob1_pll_bndy_bucket_3" , 0x06, 0x0a, 0x0a, EKB_RING , 0x0A030018}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"ob1_repr" , 0x07, 0x0a, 0x0a, VPD_RING , 0x0A037006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace OB2 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"ob2_pll_bndy_bucket_1" , 0x00, 0x0b, 0x0b, EKB_RING , 0x0B030018}, + {"ob2_pll_bndy_bucket_2" , 0x01, 0x0b, 0x0b, EKB_RING , 0x0B030018}, + {"ob2_gptr" , 0x02, 0x0b, 0x0b, EKB_RING , 0x0B037002}, + {"ob2_time" , 0x03, 0x0b, 0x0b, VPD_RING , 0x0B037007}, + {"ob2_pll_gptr" , 0x04, 0x0b, 0x0b, EKB_RING , 0x0B030012}, + {"ob2_fure" , 0x05, 0x0b, 0x0b, EKB_RING , 0x0B03700F}, + {"ob2_pll_bndy_bucket_3" , 0x06, 0x0b, 0x0b, EKB_RING , 0x0B030018}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"ob2_repr" , 0x07, 0x0b, 0x0b, VPD_RING , 0x0B037006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace OB3 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"ob3_pll_bndy_bucket_1" , 0x00, 0x0c, 0x0c, EKB_RING , 0x0C030018}, + {"ob3_pll_bndy_bucket_2" , 0x01, 0x0c, 0x0c, EKB_RING , 0x0C030018}, + {"ob3_gptr" , 0x02, 0x0c, 0x0c, EKB_RING , 0x0C037002}, + {"ob3_time" , 0x03, 0x0c, 0x0c, VPD_RING , 0x0C037007}, + {"ob3_pll_gptr" , 0x04, 0x0c, 0x0c, EKB_RING , 0x0C030012}, + {"ob3_fure" , 0x05, 0x0c, 0x0c, EKB_RING , 0x0C03700F}, + {"ob3_pll_bndy_bucket_3" , 0x06, 0x0c, 0x0c, EKB_RING , 0x0C030018}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"ob3_repr" , 0x07, 0x0c, 0x0c, VPD_RING , 0x0C037006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace PCI0 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"pci0_fure" , 0x00, 0x0d, 0x0d, EKB_RING , 0x0D03700F}, + {"pci0_gptr" , 0x01, 0x0d, 0x0d, EKB_RING , 0x0D037002}, + {"pci0_time" , 0x02, 0x0d, 0x0d, VPD_RING , 0x0D037007}, + {"pci0_pll_bndy" , 0x03, 0x0d, 0x0d, EKB_RING , 0x0D030018}, + {"pci0_pll_gptr" , 0x04, 0x0d, 0x0d, EKB_RING , 0x0D030012}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"pci0_repr" , 0x05, 0x0d, 0x0d, VPD_RING , 0x0D037006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace PCI1 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"pci1_fure" , 0x00, 0x0e, 0x0e, EKB_RING , 0x0E03780F}, + {"pci1_gptr" , 0x01, 0x0e, 0x0e, EKB_RING , 0x0E037802}, + {"pci1_time" , 0x02, 0x0e, 0x0e, VPD_RING , 0x0E037807}, + {"pci1_pll_bndy" , 0x03, 0x0e, 0x0e, EKB_RING , 0x0E030018}, + {"pci1_pll_gptr" , 0x04, 0x0e, 0x0e, EKB_RING , 0x0E030012}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"pci1_repr" , 0x05, 0x0e, 0x0e, VPD_RING , 0x0E037806}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace PCI2 +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"pci2_fure" , 0x00, 0x0f, 0x0f, EKB_RING , 0x0F037C0F}, + {"pci2_gptr" , 0x01, 0x0f, 0x0f, EKB_RING , 0x0F037C02}, + {"pci2_time" , 0x02, 0x0f, 0x0f, VPD_RING , 0x0F037C07}, + {"pci2_pll_bndy" , 0x03, 0x0f, 0x0f, EKB_RING , 0x0F030018}, + {"pci2_pll_gptr" , 0x04, 0x0f, 0x0f, EKB_RING , 0x0F030012}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"pci2_repr" , 0x05, 0x0F, 0x0F, VPD_RING , 0x0F037C06}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; +}; + + +namespace EQ +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + {"eq_fure" , 0x00, 0x10, 0x10, EKB_RING , 0x1003608F}, + {"eq_gptr" , 0x01, 0x10, 0x10, EKB_RING , 0x10036082}, + {"eq_time" , 0x02, 0x10, 0x10, VPD_RING , 0x10036087}, + {"eq_inex" , 0x03, 0x10, 0x10, EKB_RING , 0x1003608B}, + {"ex_l3_fure" , 0x04, 0x10, 0x10, EKB_RING , 0x1003100F}, + {"ex_l3_gptr" , 0x05, 0x10, 0x10, EKB_RING , 0x10031002}, + {"ex_l3_time" , 0x06, 0x10, 0x10, VPD_RING , 0x10031007}, + {"ex_l2_mode" , 0x07, 0x10, 0x10, EKB_RING , 0x10030401}, + {"ex_l2_fure" , 0x08, 0x10, 0x10, EKB_RING , 0x1003040F}, + {"ex_l2_gptr" , 0x09, 0x10, 0x10, EKB_RING , 0x10030402}, + {"ex_l2_time" , 0x0a, 0x10, 0x10, VPD_RING , 0x10030407}, + {"ex_l3_refr_fure" , 0x0b, 0x10, 0x10, EKB_RING , 0x1003004F}, + {"ex_l3_refr_gptr" , 0x0c, 0x10, 0x10, EKB_RING , 0x10030042}, + {"eq_ana_func" , 0x0d, 0x10, 0x10, EKB_RING , 0x10030100}, + {"eq_ana_gptr" , 0x0e, 0x10, 0x10, EKB_RING , 0x10030102}, + {"eq_dpll_func" , 0x0f, 0x10, 0x10, EKB_RING , 0x10030010}, + {"eq_dpll_gptr" , 0x10, 0x10, 0x10, EKB_RING , 0x10030012}, + {"eq_dpll_mode" , 0x11, 0x10, 0x10, EKB_RING , 0x10030011}, + {"eq_ana_bndy_bucket_0" , 0x12, 0x10, 0x10, EKB_RING , 0x10030108}, + {"eq_ana_bndy_bucket_1" , 0x13, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_2" , 0x14, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_3" , 0x15, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_4" , 0x16, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_5" , 0x17, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_6" , 0x18, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_7" , 0x19, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_8" , 0x1a, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_9" , 0x1b, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_10" , 0x1c, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_11" , 0x1d, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_12" , 0x1e, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_13" , 0x1f, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_14" , 0x20, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_15" , 0x21, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_16" , 0x22, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_17" , 0x23, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_18" , 0x24, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_19" , 0x25, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_20" , 0x26, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_21" , 0x27, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_22" , 0x28, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_23" , 0x29, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_24" , 0x2a, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_25" , 0x2b, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_l3dcc" , 0x2c, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_mode" , 0x2d, 0x10, 0x10, EKB_RING , 0x10030101}, + {"eq_ana_bndy_bucket_26" , 0x2e, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_27" , 0x2f, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_28" , 0x30, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_29" , 0x31, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_30" , 0x32, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_31" , 0x33, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_32" , 0x34, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_33" , 0x35, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_34" , 0x36, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_35" , 0x37, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_36" , 0x38, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_37" , 0x39, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_38" , 0x3a, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_39" , 0x3b, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_40" , 0x3c, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_ana_bndy_bucket_41" , 0x3d, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, + {"eq_inex_bucket_1" , 0x3e, 0x10, 0x10, EKB_RING , 0x1003608B}, + {"eq_inex_bucket_2" , 0x3f, 0x10, 0x10, EKB_RING , 0x1003608B}, + {"eq_inex_bucket_3" , 0x40, 0x10, 0x10, EKB_RING , 0x1003608B}, + {"eq_inex_bucket_4" , 0x41, 0x10, 0x10, EKB_RING , 0x1003608B}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + {"eq_repr" , 0x42, 0x10, 0x1b, VPD_RING , 0x10036086}, + {"ex_l3_repr" , 0x43, 0x10, 0x1b, VPD_RING , 0x10031006}, + {"ex_l2_repr" , 0x44, 0x10, 0x1b, VPD_RING , 0x10030406}, + {"ex_l3_refr_repr" , 0x45, 0x10, 0x1b, VPD_RING , 0x10030046}, + {"ex_l3_refr_time" , 0x46, 0x10, 0x1b, VPD_RING , 0x10030047}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 }; +}; + + +namespace EC +{ +const GenRingIdList RING_ID_LIST_COMMON[] = +{ + { "ec_func" , 0x00, 0x20, 0x20, EKB_STUMPED_RING , 0x2003700F}, + { "ec_gptr" , 0x01, 0x20, 0x20, EKB_RING , 0x20037002}, + { "ec_time" , 0x02, 0x20, 0x20, VPD_RING , 0x20037007}, + { "ec_mode" , 0x03, 0x20, 0x20, EKB_RING , 0x20037001}, + { "ec_abst" , 0x04, 0x20, 0x20, EKB_RING , 0x20037005}, + { "ec_cmsk" , 0xFF, 0xFF, 0xFF, EKB_CMSK_RING , 0x2003700A}, +}; +const GenRingIdList RING_ID_LIST_INSTANCE[] = +{ + { "ec_repr" , 0x05, 0x20, 0x37, VPD_RING , 0x20037006}, +}; +const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 }; +}; + + +}; // namespace P9_RID + + using namespace P9_RID; +ChipletType_t P9_RID::ringid_get_chiplet(RingId_t i_ringId) +{ + return RING_PROPERTIES[i_ringId].iv_type; +} + void P9_RID::ringid_get_chiplet_properties( ChipletType_t i_chipletType, - ChipletData_t** o_chipletData) + ChipletData_t** o_cpltData, + GenRingIdList** o_ringComm, + GenRingIdList** o_ringInst, + RingVariantOrder** o_varOrder, + uint8_t* o_numVariants) { switch (i_chipletType) { case PERV_TYPE : - *o_chipletData = (ChipletData_t*)&PERV::g_chipletData; + *o_cpltData = (ChipletData_t*) &PERV::g_chipletData; + *o_ringComm = (GenRingIdList*) PERV::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) PERV::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) PERV::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case N0_TYPE : - *o_chipletData = (ChipletData_t*)&N0::g_chipletData; + *o_cpltData = (ChipletData_t*) &N0::g_chipletData; + *o_ringComm = (GenRingIdList*) N0::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) N0::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) N0::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case N1_TYPE : - *o_chipletData = (ChipletData_t*)&N1::g_chipletData; + *o_cpltData = (ChipletData_t*) &N1::g_chipletData; + *o_ringComm = (GenRingIdList*) N1::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) N1::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) N1::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case N2_TYPE : - *o_chipletData = (ChipletData_t*)&N2::g_chipletData; + *o_cpltData = (ChipletData_t*) &N2::g_chipletData; + *o_ringComm = (GenRingIdList*) N2::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) N2::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) N2::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case N3_TYPE : - *o_chipletData = (ChipletData_t*)&N3::g_chipletData; + *o_cpltData = (ChipletData_t*) &N3::g_chipletData; + *o_ringComm = (GenRingIdList*) N3::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) N3::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) N3::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case XB_TYPE : - *o_chipletData = (ChipletData_t*)&XB::g_chipletData; + *o_cpltData = (ChipletData_t*) &XB::g_chipletData; + *o_ringComm = (GenRingIdList*) XB::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) XB::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) XB::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case MC_TYPE : - *o_chipletData = (ChipletData_t*)&MC::g_chipletData; + *o_cpltData = (ChipletData_t*) &MC::g_chipletData; + *o_ringComm = (GenRingIdList*) MC::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) MC::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) MC::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case OB0_TYPE : - *o_chipletData = (ChipletData_t*)&OB0::g_chipletData; + *o_cpltData = (ChipletData_t*) &OB0::g_chipletData; + *o_ringComm = (GenRingIdList*) OB0::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) OB0::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) OB0::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case OB1_TYPE : - *o_chipletData = (ChipletData_t*)&OB1::g_chipletData; + *o_cpltData = (ChipletData_t*) &OB1::g_chipletData; + *o_ringComm = (GenRingIdList*) OB1::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) OB1::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) OB1::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case OB2_TYPE : - *o_chipletData = (ChipletData_t*)&OB2::g_chipletData; + *o_cpltData = (ChipletData_t*) &OB2::g_chipletData; + *o_ringComm = (GenRingIdList*) OB2::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) OB2::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) OB2::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case OB3_TYPE : - *o_chipletData = (ChipletData_t*)&OB3::g_chipletData; + *o_cpltData = (ChipletData_t*) &OB3::g_chipletData; + *o_ringComm = (GenRingIdList*) OB3::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) OB3::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) OB3::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case PCI0_TYPE : - *o_chipletData = (ChipletData_t*)&PCI0::g_chipletData; + *o_cpltData = (ChipletData_t*) &PCI0::g_chipletData; + *o_ringComm = (GenRingIdList*) PCI0::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) PCI0::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) PCI0::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case PCI1_TYPE : - *o_chipletData = (ChipletData_t*)&PCI1::g_chipletData; + *o_cpltData = (ChipletData_t*) &PCI1::g_chipletData; + *o_ringComm = (GenRingIdList*) PCI1::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) PCI1::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) PCI1::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case PCI2_TYPE : - *o_chipletData = (ChipletData_t*)&PCI2::g_chipletData; + *o_cpltData = (ChipletData_t*) &PCI2::g_chipletData; + *o_ringComm = (GenRingIdList*) PCI2::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) PCI2::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) PCI2::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case EQ_TYPE : - *o_chipletData = (ChipletData_t*)&EQ::g_chipletData; + *o_cpltData = (ChipletData_t*) &EQ::g_chipletData; + *o_ringComm = (GenRingIdList*) EQ::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) EQ::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) EQ::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; case EC_TYPE : - *o_chipletData = (ChipletData_t*)&EC::g_chipletData; + *o_cpltData = (ChipletData_t*) &EC::g_chipletData; + *o_ringComm = (GenRingIdList*) EC::RING_ID_LIST_COMMON; + *o_ringInst = (GenRingIdList*) EC::RING_ID_LIST_INSTANCE; + *o_varOrder = (RingVariantOrder*) EC::RING_VARIANT_ORDER; + *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; break; default : - *o_chipletData = NULL; + *o_cpltData = NULL; + *o_ringComm = NULL; + *o_ringInst = NULL; + *o_varOrder = NULL; + *o_numVariants = 0; break; } } + +GenRingIdList* P9_RID::_ringid_get_ring_list(RingId_t i_ringId) +{ + ChipletData_t* l_cpltData; + GenRingIdList* l_ringList[2]; // 0: common, 1: instance + RingVariantOrder* l_varOrder; + uint8_t l_numVariants; + int i, j, n; + + P9_RID::ringid_get_chiplet_properties( + P9_RID::ringid_get_chiplet(i_ringId), + &l_cpltData, &l_ringList[0], &l_ringList[1], &l_varOrder, &l_numVariants); + + if (!l_ringList[0]) + { + return NULL; + } + + for (j = 0; j < 2; j++) // 0: common, 1: instance + { + n = (j ? l_cpltData->iv_num_instance_rings + : l_cpltData->iv_num_common_rings); + + for (i = 0; i < n; i++) + { + if (!strcmp(l_ringList[j][i].ringName, + RING_PROPERTIES[i_ringId].iv_name)) + { + return &(l_ringList[j][i]); + } + } + } + + return NULL; +} diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H index c0aff85a7..b6ec27a85 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H @@ -38,7 +38,7 @@ #endif -enum Chiplets +enum CHIPLET_TYPE { PERV_TYPE, N0_TYPE, @@ -56,12 +56,123 @@ enum Chiplets PCI2_TYPE, EQ_TYPE, EC_TYPE, - SBE_NUM_CHIPLETS + SBE_NOOF_CHIPLETS }; -const ChipletType_t CME_NUM_CHIPLETS = 1; -const ChipletType_t SGPE_NUM_CHIPLETS = 1; +const ChipletType_t CME_NOOF_CHIPLETS = 1; +const ChipletType_t SGPE_NOOF_CHIPLETS = 1; +namespace PERV +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace N0 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace N1 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace N2 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace N3 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace XB +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace MC +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace OB0 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace OB1 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace OB2 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace OB3 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace PCI0 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace PCI1 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace PCI2 +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace EQ +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} + +namespace EC +{ +extern const GenRingIdList RING_ID_LIST_COMMON[]; +extern const GenRingIdList RING_ID_LIST_INSTANCE[]; +extern const RingVariantOrder RING_VARIANT_ORDER[]; +} namespace PERV { @@ -102,15 +213,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x01, // Base chiplet/instance ID - 1, // Number of chiplet instances + 1, // Pervasive Chiplet ID is 1 21, // 21 common rings for pervasive chiplet 3, // 3 instance specific rings for pervasive chiplet 3, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // end of namespace PERV namespace N0 @@ -135,15 +243,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x02, // Base chiplet/instance ID - 1, // Number of chiplet instances + 2, // N0 Chiplet ID is 2. 9, // 9 common rings for N0 Chiplet 3, // 3 instance specific rings for N0 chiplet 3, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; namespace N1 @@ -172,15 +277,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x03, // Base chiplet/instance ID - 1, // Number of chiplet instances + 3, // N1 Chiplet ID is 3. 12, // 12 common rings for N1 Chiplet 4, // 4 instance specific rings for N1 chiplet 4, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; namespace N2 @@ -204,15 +306,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x04, // Base chiplet/instance ID - 1, // Number of chiplet instances + 4, // N2 Chiplet ID is 4. 9, // 9 common rings for N2 Chiplet 2, // 2 instance specific rings for N2 chiplet 2, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; namespace N3 @@ -238,15 +337,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x05, // Base chiplet/instance ID - 1, // Number of chiplet instances + 5, // N3 Chiplet ID is 5 10,// 10 common rings for N3 Chiplet 3, // 3 instance specific rings for N3 chiplet 3, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; namespace XB @@ -278,15 +374,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x06, // Base chiplet/instance ID - 1, // Number of chiplet instances + 6, // X-Bus Chiplet ID is 6 15, // 15 common rings for X-Bus Chiplet 4, // 4 instance specific rings for XB chiplet 4, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // end of namespace XB namespace MC @@ -328,15 +421,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x07, // Base chiplet/instance ID - 2, // Number of chiplet instances + 7, // MC Chiplet ID range is 7 - 8. The base ID is 7. 25, // 25 common rings for MC Chiplet 3, // 3 instance specific rings for each MC instance 3, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // end of namespace MC namespace OB0 @@ -358,15 +448,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x09, // Base chiplet/instance ID - 1, // Number of chiplet instances + 9, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // end of namespace OB0 namespace OB1 @@ -388,15 +475,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x0a, // Base chiplet/instance ID - 1, // Number of chiplet instances + 10, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // end of namespace OB1 @@ -419,15 +503,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x0b, // Base chiplet/instance ID - 1, // Number of chiplet instances + 11, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // end of namespace OB2 namespace OB3 @@ -449,15 +530,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x0c, // Base chiplet/instance ID - 1, // Number of chiplet instances + 12, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; // end of namespace OB2 namespace PCI0 @@ -476,15 +554,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x0d, // Base chiplet/instance ID - 1, // Number of chiplet instances + 13, // PCI0 Chiplet Chiplet ID is 13 5, // 5 common rings for PCI0 chiplet 1, // 1 instance specific rings for PCI0 chiplet 1, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; namespace PCI1 @@ -503,15 +578,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x0e, // Base chiplet/instance ID - 1, // Number of chiplet instances + 14, // PCI1 Chiplet Chiplet ID is 14 5, // 5 common rings for PCI1 chiplet 1, // 1 instance specific rings for PCI1 chiplet 1, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; namespace PCI2 @@ -530,15 +602,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x0f, // Base chiplet/instance ID - 1, // Number of chiplet instances + 15, // PCI2 Chiplet Chiplet ID is 15 5, // 5 common rings for PCI2 chiplet 1, // 1 instance specific rings for PCI2 chiplet 1, 2, // 2 common ring variants: BASE, RL - { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; - }; namespace EQ @@ -624,17 +693,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x10, // Base chiplet/instance ID. - // Note that the Quad EQ chiplet/instance ID range is 16 - 21 but that in addition - // to this there are two EXs per EQ: even and odd, making a total of 12 instances - 12, // Max num of EX/EQ combined instance IDs = 2 (EX) x 6 (EQ) = 12 + 16, // Quad Chiplet ID range is 16 - 21. The base ID is 16. 66, // 66 common rings for Quad chiplet. 5, // 5 instance specific rings for each EQ chiplet 9, // 9 different rings since 2 per EX ring and 1 per EQ 7, // 7 common ring variants: BASE, CC, RL, RL2/3/4/5 - { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 } }; - }; // end of namespace EQ namespace EC @@ -654,15 +718,12 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 0x20, // Core chiplet/instance ID range is 32-55. The base instance ID is 32. - 24, // Number of chiplet instances + 32, // Core Chiplet ID range is 32-55. The base ID is 32. 6, // 6 common rings for Core chiplet 1, // 1 instance specific ring for each Core chiplet 1, 7, // 7 common ring variants: BASE, CC, RL, RL2/3/4/5 - { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 } }; - }; // end of namespace EC @@ -670,555 +731,568 @@ static const ChipletData_t g_chipletData = static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { - { "perv_fure" , 0x0103400F, PERV::perv_fure , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 0 - { "perv_gptr" , 0x01034002, PERV::perv_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 1 - { "perv_time" , 0x01034007, PERV::perv_time , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 2 - { "occ_fure" , 0x0103080F, PERV::occ_fure , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 3 - { "occ_gptr" , 0x01030802, PERV::occ_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 4 - { "occ_time" , 0x01030807, PERV::occ_time , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 5 - { "perv_ana_func" , 0x01030400, PERV::perv_ana_func , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 6 - { "perv_ana_gptr" , 0x01030402, PERV::perv_ana_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 7 - { "perv_pll_gptr" , 0x01030012, PERV::perv_pll_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 8 - { "perv_pll_bndy" , 0x01030018, PERV::perv_pll_bndy , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 9 - { "perv_pll_bndy_bucket_1" , 0x01030018, PERV::perv_pll_bndy_bucket_1, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 10 - { "perv_pll_bndy_bucket_2" , 0x01030018, PERV::perv_pll_bndy_bucket_2, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 11 - { "perv_pll_bndy_bucket_3" , 0x01030018, PERV::perv_pll_bndy_bucket_3, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 12 - { "perv_pll_bndy_bucket_4" , 0x01030018, PERV::perv_pll_bndy_bucket_4, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 13 - { "perv_pll_bndy_bucket_5" , 0x01030018, PERV::perv_pll_bndy_bucket_5, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 14 - { "perv_pll_func" , 0x01030010, PERV::perv_pll_func , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 15 - { "perv_repr" , 0x01034006, PERV::perv_repr , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 16 - { "occ_repr" , 0x01030806, PERV::occ_repr , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 17 - { "sbe_fure" , 0x0103020F, PERV::sbe_fure , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 18 - { "sbe_gptr" , 0x01030202, PERV::sbe_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 19 - { "sbe_repr" , 0x01030206, PERV::sbe_repr , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 20 - { "n0_fure" , 0x02034E0F, N0::n0_fure , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 21 - { "n0_gptr" , 0x02034E02, N0::n0_gptr , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 22 - { "n0_time" , 0x02034E07, N0::n0_time , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 23 - { "n0_nx_fure" , 0x0203200F, N0::n0_nx_fure , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 24 - { "n0_nx_gptr" , 0x02032002, N0::n0_nx_gptr , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 25 - { "n0_nx_time" , 0x02032007, N0::n0_nx_time , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 26 - { "n0_cxa0_fure" , 0x0203100F, N0::n0_cxa0_fure , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 27 - { "n0_cxa0_gptr" , 0x02031002, N0::n0_cxa0_gptr , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 28 - { "n0_cxa0_time" , 0x02031007, N0::n0_cxa0_time , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 29 - { "n0_repr" , 0x02034E06, N0::n0_repr , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 30 - { "n0_nx_repr" , 0x02032006, N0::n0_nx_repr , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 31 - { "n0_cxa0_repr" , 0x02031006, N0::n0_cxa0_repr , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 32 - { "n1_fure" , 0x0303700F, N1::n1_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 33 - { "n1_gptr" , 0x03037002, N1::n1_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 34 - { "n1_time" , 0x03037007, N1::n1_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 35 - { "n1_ioo0_fure" , 0x0303080F, N1::n1_ioo0_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 36 - { "n1_ioo0_gptr" , 0x03030802, N1::n1_ioo0_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 37 - { "n1_ioo0_time" , 0x03030807, N1::n1_ioo0_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 38 - { "n1_ioo1_fure" , 0x0303040F, N1::n1_ioo1_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 39 - { "n1_ioo1_gptr" , 0x03030402, N1::n1_ioo1_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 40 - { "n1_ioo1_time" , 0x03030407, N1::n1_ioo1_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 41 - { "n1_mcs23_fure" , 0x0303020F, N1::n1_mcs23_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 42 - { "n1_mcs23_gptr" , 0x03030202, N1::n1_mcs23_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 43 - { "n1_mcs23_time" , 0x03030207, N1::n1_mcs23_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 44 - { "n1_repr" , 0x03037006, N1::n1_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 45 - { "n1_ioo0_repr" , 0x03030806, N1::n1_ioo0_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 46 - { "n1_ioo1_repr" , 0x03030406, N1::n1_ioo1_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 47 - { "n1_mcs23_repr" , 0x03030206, N1::n1_mcs23_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 48 - { "n2_fure" , 0x04035C0F, N2::n2_fure , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 49 - { "n2_gptr" , 0x04035C02, N2::n2_gptr , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 50 - { "n2_time" , 0x04035C07, N2::n2_time , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 51 - { "n2_cxa1_fure" , 0x0403200F, N2::n2_cxa1_fure , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 52 - { "n2_cxa1_gptr" , 0x04032002, N2::n2_cxa1_gptr , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 53 - { "n2_cxa1_time" , 0x04032007, N2::n2_cxa1_time , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 54 - { "n2_psi_fure" , 0x0403020F, N2::n2_psi_fure , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 55 - { "n2_psi_gptr" , 0x04030202, N2::n2_psi_gptr , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 56 - { "n2_psi_time" , 0x04030207, N2::n2_psi_time , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 57 - { "n2_repr" , 0x04035C06, N2::n2_repr , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 58 - { "n2_cxa1_repr" , 0x04032006, N2::n2_cxa1_repr , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 59 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, N2_TYPE , UNDEFINED_RING_CLASS }, // 60 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, N2_TYPE , UNDEFINED_RING_CLASS }, // 61 - { "n3_fure" , 0x0503660F, N3::n3_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 62 - { "n3_gptr" , 0x05037602, N3::n3_gptr , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 63 - { "n3_time" , 0x05037607, N3::n3_time , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 64 - { "n3_mcs01_fure" , 0x0503010F, N3::n3_mcs01_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 65 - { "n3_mcs01_gptr" , 0x05030102, N3::n3_mcs01_gptr , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 66 - { "n3_mcs01_time" , 0x05030107, N3::n3_mcs01_time , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 67 - { "n3_np_fure" , 0x0503080F, N3::n3_np_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 68 - { "n3_np_gptr" , 0x05030802, N3::n3_np_gptr , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 69 - { "n3_np_time" , 0x05030807, N3::n3_np_time , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 70 - { "n3_repr" , 0x05037606, N3::n3_repr , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 71 - { "n3_mcs01_repr" , 0x05030106, N3::n3_mcs01_repr , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 72 - { "n3_np_repr" , 0x05030806, N3::n3_np_repr , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 73 - { "n3_br_fure" , 0x0503100F, N3::n3_br_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 74 - { "xb_fure" , 0x0603440F, XB::xb_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 75 - { "xb_gptr" , 0x06034402, XB::xb_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 76 - { "xb_time" , 0x06034407, XB::xb_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 77 - { "xb_io0_fure" , 0x0603220F, XB::xb_io0_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 78 - { "xb_io0_gptr" , 0x06032202, XB::xb_io0_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 79 - { "xb_io0_time" , 0x06032207, XB::xb_io0_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 80 - { "xb_io1_fure" , 0x0603110F, XB::xb_io1_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 81 - { "xb_io1_gptr" , 0x06031102, XB::xb_io1_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 82 - { "xb_io1_time" , 0x06031107, XB::xb_io1_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 83 - { "xb_io2_fure" , 0x0603088F, XB::xb_io2_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 84 - { "xb_io2_gptr" , 0x06030882, XB::xb_io2_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 85 - { "xb_io2_time" , 0x06030887, XB::xb_io2_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 86 - { "xb_pll_gptr" , 0x06030012, XB::xb_pll_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 87 - { "xb_pll_bndy" , 0x06030018, XB::xb_pll_bndy , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 88 - { "xb_pll_func" , 0x06030010, XB::xb_pll_func , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 89 - { "xb_repr" , 0x06034406, XB::xb_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 90 - { "xb_io0_repr" , 0x06032206, XB::xb_io0_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 91 - { "xb_io1_repr" , 0x06031106, XB::xb_io1_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 92 - { "xb_io2_repr" , 0x06030886, XB::xb_io2_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 93 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, XB_TYPE , UNDEFINED_RING_CLASS }, // 94 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, XB_TYPE , UNDEFINED_RING_CLASS }, // 95 - { "mc_fure" , 0x0703600F, MC::mc_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 96 - { "mc_gptr" , 0x07036002, MC::mc_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 97 - { "mc_time" , 0x07036007, MC::mc_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 98 - { "mc_iom01_fure" , 0x0703100F, MC::mc_iom01_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 99 - { "mc_iom01_gptr" , 0x07031002, MC::mc_iom01_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 100 - { "mc_iom01_time" , 0x07031007, MC::mc_iom01_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 101 - { "mc_iom23_fure" , 0x0703080F, MC::mc_iom23_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 102 - { "mc_iom23_gptr" , 0x07030802, MC::mc_iom23_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 103 - { "mc_iom23_time" , 0x07030807, MC::mc_iom23_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 104 - { "mc_pll_gptr" , 0x07030012, MC::mc_pll_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 105 - { "mc_pll_bndy" , 0x07030018, MC::mc_pll_bndy , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 106 - { "mc_pll_bndy_bucket_1" , 0x07030018, MC::mc_pll_bndy_bucket_1 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 107 - { "mc_pll_bndy_bucket_2" , 0x07030018, MC::mc_pll_bndy_bucket_2 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 108 - { "mc_pll_bndy_bucket_3" , 0x07030018, MC::mc_pll_bndy_bucket_3 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 109 - { "mc_pll_bndy_bucket_4" , 0x07030018, MC::mc_pll_bndy_bucket_4 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 110 - { "mc_pll_bndy_bucket_5" , 0x07030018, MC::mc_pll_bndy_bucket_5 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 111 - { "mc_pll_func" , 0x07030010, MC::mc_pll_func , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 112 - { "mc_repr" , 0x07036006, MC::mc_repr , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 113 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, MC_TYPE , UNDEFINED_RING_CLASS }, // 114 - { "mc_iom23_repr" , 0x07030806, MC::mc_iom23_repr , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 115 - { "ob0_pll_bndy" , 0x09030018, OB0::ob0_pll_bndy , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 116 - { "ob0_pll_bndy_bucket_1" , 0x09030018, OB0::ob0_pll_bndy_bucket_1 , OB0_TYPE , RCLS_EKB_FLUSH_RING }, // 117 - { "ob0_pll_bndy_bucket_2" , 0x09030018, OB0::ob0_pll_bndy_bucket_2 , OB0_TYPE , RCLS_EKB_FLUSH_RING }, // 118 - { "ob0_gptr" , 0x09037002, OB0::ob0_gptr , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 119 - { "ob0_time" , 0x09037007, OB0::ob0_time , OB0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 120 - { "ob0_pll_gptr" , 0x09030012, OB0::ob0_pll_gptr , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 121 - { "ob0_fure" , 0x0903700F, OB0::ob0_fure , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 122 - { "ob0_pll_bndy_bucket_3" , 0x09030018, OB0::ob0_pll_bndy_bucket_3 , OB0_TYPE , RCLS_EKB_FLUSH_RING }, // 123 - { "ob0_repr" , 0x09037006, OB0::ob0_repr , OB0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 124 - { "ob1_pll_bndy" , 0x0A030018, OB1::ob1_pll_bndy , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 125 - { "ob1_pll_bndy_bucket_1" , 0x0A030018, OB1::ob1_pll_bndy_bucket_1 , OB1_TYPE , RCLS_EKB_FLUSH_RING }, // 126 - { "ob1_pll_bndy_bucket_2" , 0x0A030018, OB1::ob1_pll_bndy_bucket_2 , OB1_TYPE , RCLS_EKB_FLUSH_RING }, // 127 - { "ob1_gptr" , 0x0A037002, OB1::ob1_gptr , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 128 - { "ob1_time" , 0x0A037007, OB1::ob1_time , OB1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 129 - { "ob1_pll_gptr" , 0x0A030012, OB1::ob1_pll_gptr , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 130 - { "ob1_fure" , 0x0A03700F, OB1::ob1_fure , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 131 - { "ob1_pll_bndy_bucket_3" , 0x0A030018, OB1::ob1_pll_bndy_bucket_3 , OB1_TYPE , RCLS_EKB_FLUSH_RING }, // 132 - { "ob1_repr" , 0x0A037006, OB1::ob1_repr , OB1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 133 - { "ob2_pll_bndy" , 0x0B030018, OB2::ob2_pll_bndy , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 134 - { "ob2_pll_bndy_bucket_1" , 0x0B030018, OB2::ob2_pll_bndy_bucket_1 , OB2_TYPE , RCLS_EKB_FLUSH_RING }, // 135 - { "ob2_pll_bndy_bucket_2" , 0x0B030018, OB2::ob2_pll_bndy_bucket_2 , OB2_TYPE , RCLS_EKB_FLUSH_RING }, // 136 - { "ob2_gptr" , 0x0B037002, OB2::ob2_gptr , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 137 - { "ob2_time" , 0x0B037007, OB2::ob2_time , OB2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 138 - { "ob2_pll_gptr" , 0x0B030012, OB2::ob2_pll_gptr , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 139 - { "ob2_fure" , 0x0B03700F, OB2::ob2_fure , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 140 - { "ob2_pll_bndy_bucket_3" , 0x0B030018, OB2::ob2_pll_bndy_bucket_3 , OB2_TYPE , RCLS_EKB_FLUSH_RING }, // 141 - { "ob2_repr" , 0x0B037006, OB2::ob2_repr , OB2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 142 - { "ob3_pll_bndy" , 0x0C030018, OB3::ob3_pll_bndy , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 143 - { "ob3_pll_bndy_bucket_1" , 0x0C030018, OB3::ob3_pll_bndy_bucket_1 , OB3_TYPE , RCLS_EKB_FLUSH_RING }, // 144 - { "ob3_pll_bndy_bucket_2" , 0x0C030018, OB3::ob3_pll_bndy_bucket_2 , OB3_TYPE , RCLS_EKB_FLUSH_RING }, // 145 - { "ob3_gptr" , 0x0C037002, OB3::ob3_gptr , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 146 - { "ob3_time" , 0x0C037007, OB3::ob3_time , OB3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 147 - { "ob3_pll_gptr" , 0x0C030012, OB3::ob3_pll_gptr , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 148 - { "ob3_fure" , 0x0C03700F, OB3::ob3_fure , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 149 - { "ob3_pll_bndy_bucket_3" , 0x0C030018, OB3::ob3_pll_bndy_bucket_3 , OB3_TYPE , RCLS_EKB_FLUSH_RING }, // 150 - { "ob3_repr" , 0x0C037006, OB3::ob3_repr , OB3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 151 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, OB3_TYPE , UNDEFINED_RING_CLASS }, // 152 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, OB3_TYPE , UNDEFINED_RING_CLASS }, // 153 - { "pci0_fure" , 0x0D03700F, PCI0::pci0_fure , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 154 - { "pci0_gptr" , 0x0D037002, PCI0::pci0_gptr , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 155 - { "pci0_time" , 0x0D037007, PCI0::pci0_time , PCI0_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 156 - { "pci0_pll_bndy" , 0x0D030018, PCI0::pci0_pll_bndy , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 157 - { "pci0_pll_gptr" , 0x0D030012, PCI0::pci0_pll_gptr , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 158 - { "pci0_repr" , 0x0D037006, PCI0::pci0_repr , PCI0_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 159 - { "pci1_fure" , 0x0E03780F, PCI1::pci1_fure , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 160 - { "pci1_gptr" , 0x0E037802, PCI1::pci1_gptr , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 161 - { "pci1_time" , 0x0E037807, PCI1::pci1_time , PCI1_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 162 - { "pci1_pll_bndy" , 0x0E030018, PCI1::pci1_pll_bndy , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 163 - { "pci1_pll_gptr" , 0x0E030012, PCI1::pci1_pll_gptr , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 164 - { "pci1_repr" , 0x0E037806, PCI1::pci1_repr , PCI1_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 165 - { "pci2_fure" , 0x0F037C0F, PCI2::pci2_fure , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 166 - { "pci2_gptr" , 0x0F037C02, PCI2::pci2_gptr , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 167 - { "pci2_time" , 0x0F037C07, PCI2::pci2_time , PCI2_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 168 - { "pci2_pll_bndy" , 0x0F030018, PCI2::pci2_pll_bndy , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 169 - { "pci2_pll_gptr" , 0x0F030012, PCI2::pci2_pll_gptr , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 170 - { "pci2_repr" , 0x0F037C06, PCI2::pci2_repr , PCI2_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 171 - { "eq_fure" , 0x1003608F, EQ::eq_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 172 - { "eq_gptr" , 0x10036082, EQ::eq_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 173 - { "eq_time" , 0x10036087, EQ::eq_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 174 - { "eq_inex" , 0x1003608B, EQ::eq_inex , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 175 - { "ex_l3_fure" , 0x1003100F, EQ::ex_l3_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 176 - { "ex_l3_gptr" , 0x10031002, EQ::ex_l3_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 177 - { "ex_l3_time" , 0x10031007, EQ::ex_l3_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 178 - { "ex_l2_mode" , 0x10030401, EQ::ex_l2_mode , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 179 - { "ex_l2_fure" , 0x1003040F, EQ::ex_l2_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 180 - { "ex_l2_gptr" , 0x10030402, EQ::ex_l2_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 181 - { "ex_l2_time" , 0x10030407, EQ::ex_l2_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 182 - { "ex_l3_refr_fure" , 0x1003004F, EQ::ex_l3_refr_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 183 - { "ex_l3_refr_gptr" , 0x10030042, EQ::ex_l3_refr_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 184 - { "ex_l3_refr_time" , 0x10030047, EQ::ex_l3_refr_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 185 - { "eq_ana_func" , 0x10030100, EQ::eq_ana_func , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 186 - { "eq_ana_gptr" , 0x10030102, EQ::eq_ana_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 187 - { "eq_dpll_func" , 0x10030010, EQ::eq_dpll_func , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 188 - { "eq_dpll_gptr" , 0x10030012, EQ::eq_dpll_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 189 - { "eq_dpll_mode" , 0x10030011, EQ::eq_dpll_mode , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 190 - { "eq_ana_bndy" , 0x10030108, EQ::eq_ana_bndy , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FSM_RING }, // 191 - { "eq_ana_bndy_bucket_0" , 0x10030108, EQ::eq_ana_bndy_bucket_0 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 192 - { "eq_ana_bndy_bucket_1" , 0x10030108, EQ::eq_ana_bndy_bucket_1 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 193 - { "eq_ana_bndy_bucket_2" , 0x10030108, EQ::eq_ana_bndy_bucket_2 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 194 - { "eq_ana_bndy_bucket_3" , 0x10030108, EQ::eq_ana_bndy_bucket_3 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 195 - { "eq_ana_bndy_bucket_4" , 0x10030108, EQ::eq_ana_bndy_bucket_4 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 196 - { "eq_ana_bndy_bucket_5" , 0x10030108, EQ::eq_ana_bndy_bucket_5 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 197 - { "eq_ana_bndy_bucket_6" , 0x10030108, EQ::eq_ana_bndy_bucket_6 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 198 - { "eq_ana_bndy_bucket_7" , 0x10030108, EQ::eq_ana_bndy_bucket_7 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 199 - { "eq_ana_bndy_bucket_8" , 0x10030108, EQ::eq_ana_bndy_bucket_8 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 200 - { "eq_ana_bndy_bucket_9" , 0x10030108, EQ::eq_ana_bndy_bucket_9 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 201 - { "eq_ana_bndy_bucket_10" , 0x10030108, EQ::eq_ana_bndy_bucket_10 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 202 - { "eq_ana_bndy_bucket_11" , 0x10030108, EQ::eq_ana_bndy_bucket_11 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 203 - { "eq_ana_bndy_bucket_12" , 0x10030108, EQ::eq_ana_bndy_bucket_12 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 204 - { "eq_ana_bndy_bucket_13" , 0x10030108, EQ::eq_ana_bndy_bucket_13 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 205 - { "eq_ana_bndy_bucket_14" , 0x10030108, EQ::eq_ana_bndy_bucket_14 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 206 - { "eq_ana_bndy_bucket_15" , 0x10030108, EQ::eq_ana_bndy_bucket_15 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 207 - { "eq_ana_bndy_bucket_16" , 0x10030108, EQ::eq_ana_bndy_bucket_16 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 208 - { "eq_ana_bndy_bucket_17" , 0x10030108, EQ::eq_ana_bndy_bucket_17 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 209 - { "eq_ana_bndy_bucket_18" , 0x10030108, EQ::eq_ana_bndy_bucket_18 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 210 - { "eq_ana_bndy_bucket_19" , 0x10030108, EQ::eq_ana_bndy_bucket_19 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 211 - { "eq_ana_bndy_bucket_20" , 0x10030108, EQ::eq_ana_bndy_bucket_20 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 212 - { "eq_ana_bndy_bucket_21" , 0x10030108, EQ::eq_ana_bndy_bucket_21 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 213 - { "eq_ana_bndy_bucket_22" , 0x10030108, EQ::eq_ana_bndy_bucket_22 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 214 - { "eq_ana_bndy_bucket_23" , 0x10030108, EQ::eq_ana_bndy_bucket_23 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 215 - { "eq_ana_bndy_bucket_24" , 0x10030108, EQ::eq_ana_bndy_bucket_24 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 216 - { "eq_ana_bndy_bucket_25" , 0x10030108, EQ::eq_ana_bndy_bucket_25 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 217 - { "eq_ana_bndy_bucket_l3dcc", 0x10030108, EQ::eq_ana_bndy_bucket_l3dcc, EQ_TYPE , RCLS_EKB_FSM_RING }, // 218 - { "eq_ana_mode" , 0x10030101, EQ::eq_ana_mode , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 219 - { "eq_repr" , 0x10036086, EQ::eq_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 220 - { "ex_l3_repr" , 0x10031006, EQ::ex_l3_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 221 - { "ex_l2_repr" , 0x10030406, EQ::ex_l2_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 222 - { "ex_l3_refr_repr" , 0x10030046, EQ::ex_l3_refr_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 223 - { "ec_func" , 0x2003700F, EC::ec_func , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_STUMPED_RING }, // 224 - { "ec_gptr" , 0x20037002, EC::ec_gptr , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 225 - { "ec_time" , 0x20037007, EC::ec_time , EC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 226 - { "ec_mode" , 0x20037001, EC::ec_mode , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 227 - { "ec_repr" , 0x20037006, EC::ec_repr , EC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 228 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, EQ_TYPE , UNDEFINED_RING_CLASS }, // 229 - { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, EQ_TYPE , UNDEFINED_RING_CLASS }, // 230 - { "ec_abst" , 0x20037005, EC::ec_abst , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 231 - { "eq_ana_bndy_bucket_26" , 0x10030108, EQ::eq_ana_bndy_bucket_26 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 232 - { "eq_ana_bndy_bucket_27" , 0x10030108, EQ::eq_ana_bndy_bucket_27 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 233 - { "eq_ana_bndy_bucket_28" , 0x10030108, EQ::eq_ana_bndy_bucket_28 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 234 - { "eq_ana_bndy_bucket_29" , 0x10030108, EQ::eq_ana_bndy_bucket_29 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 235 - { "eq_ana_bndy_bucket_30" , 0x10030108, EQ::eq_ana_bndy_bucket_30 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 236 - { "eq_ana_bndy_bucket_31" , 0x10030108, EQ::eq_ana_bndy_bucket_31 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 237 - { "eq_ana_bndy_bucket_32" , 0x10030108, EQ::eq_ana_bndy_bucket_32 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 238 - { "eq_ana_bndy_bucket_33" , 0x10030108, EQ::eq_ana_bndy_bucket_33 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 239 - { "eq_ana_bndy_bucket_34" , 0x10030108, EQ::eq_ana_bndy_bucket_34 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 240 - { "eq_ana_bndy_bucket_35" , 0x10030108, EQ::eq_ana_bndy_bucket_35 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 241 - { "eq_ana_bndy_bucket_36" , 0x10030108, EQ::eq_ana_bndy_bucket_36 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 242 - { "eq_ana_bndy_bucket_37" , 0x10030108, EQ::eq_ana_bndy_bucket_37 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 243 - { "eq_ana_bndy_bucket_38" , 0x10030108, EQ::eq_ana_bndy_bucket_38 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 244 - { "eq_ana_bndy_bucket_39" , 0x10030108, EQ::eq_ana_bndy_bucket_39 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 245 - { "eq_ana_bndy_bucket_40" , 0x10030108, EQ::eq_ana_bndy_bucket_40 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 246 - { "eq_ana_bndy_bucket_41" , 0x10030108, EQ::eq_ana_bndy_bucket_41 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 247 - { "eq_inex_bucket_1" , 0x1003608B, EQ::eq_inex_bucket_1 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 248 - { "eq_inex_bucket_2" , 0x1003608B, EQ::eq_inex_bucket_2 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 249 - { "eq_inex_bucket_3" , 0x1003608B, EQ::eq_inex_bucket_3 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 250 - { "eq_inex_bucket_4" , 0x1003608B, EQ::eq_inex_bucket_4 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 251 - { "ec_cmsk" , 0x2003700A, EC::ec_cmsk , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_CMSK_RING }, // 252 - { "perv_pll_bndy_flt_1" , 0x01030018, PERV::perv_pll_bndy_flt_1 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 253 - { "perv_pll_bndy_flt_2" , 0x01030018, PERV::perv_pll_bndy_flt_2 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 254 - { "perv_pll_bndy_flt_3" , 0x01030018, PERV::perv_pll_bndy_flt_3 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 255 - { "perv_pll_bndy_flt_4" , 0x01030018, PERV::perv_pll_bndy_flt_4 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 256 - { "mc_omi0_fure" , 0x0703100F, MC::mc_omi0_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 257 - { "mc_omi0_gptr" , 0x07031002, MC::mc_omi0_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 258 - { "mc_omi1_fure" , 0x0703080F, MC::mc_omi1_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 259 - { "mc_omi1_gptr" , 0x07030802, MC::mc_omi1_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 260 - { "mc_omi2_fure" , 0x0703040F, MC::mc_omi2_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 261 - { "mc_omi2_gptr" , 0x07030402, MC::mc_omi2_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 262 - { "mc_omippe_fure" , 0x0703020F, MC::mc_omippe_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 263 - { "mc_omippe_gptr" , 0x07030202, MC::mc_omippe_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 264 - { "mc_omippe_time" , 0x07030207, MC::mc_omippe_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 265 - { "mc_omippe_repr" , 0x07030206, MC::mc_omippe_repr , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 266 + { PERV::perv_fure , "perv_fure" , PERV_TYPE }, // 0 + { PERV::perv_gptr , "perv_gptr" , PERV_TYPE }, // 1 + { PERV::perv_time , "perv_time" , PERV_TYPE }, // 2 + { PERV::occ_fure , "occ_fure" , PERV_TYPE }, // 3 + { PERV::occ_gptr , "occ_gptr" , PERV_TYPE }, // 4 + { PERV::occ_time , "occ_time" , PERV_TYPE }, // 5 + { PERV::perv_ana_func , "perv_ana_func" , PERV_TYPE }, // 6 + { PERV::perv_ana_gptr , "perv_ana_gptr" , PERV_TYPE }, // 7 + { PERV::perv_pll_gptr , "perv_pll_gptr" , PERV_TYPE }, // 8 + { PERV::perv_pll_bndy , "perv_pll_bndy" , PERV_TYPE }, // 9 + { PERV::perv_pll_bndy_bucket_1 , "perv_pll_bndy_bucket_1" , PERV_TYPE }, // 10 + { PERV::perv_pll_bndy_bucket_2 , "perv_pll_bndy_bucket_2" , PERV_TYPE }, // 11 + { PERV::perv_pll_bndy_bucket_3 , "perv_pll_bndy_bucket_3" , PERV_TYPE }, // 12 + { PERV::perv_pll_bndy_bucket_4 , "perv_pll_bndy_bucket_4" , PERV_TYPE }, // 13 + { PERV::perv_pll_bndy_bucket_5 , "perv_pll_bndy_bucket_5" , PERV_TYPE }, // 14 + { PERV::perv_pll_func , "perv_pll_func" , PERV_TYPE }, // 15 + { PERV::perv_repr , "perv_repr" , PERV_TYPE }, // 16 + { PERV::occ_repr , "occ_repr" , PERV_TYPE }, // 17 + { PERV::sbe_fure , "sbe_fure" , PERV_TYPE }, // 18 + { PERV::sbe_gptr , "sbe_gptr" , PERV_TYPE }, // 19 + { PERV::sbe_repr , "sbe_repr" , PERV_TYPE }, // 20 + { N0::n0_fure , "n0_fure" , N0_TYPE }, // 21 + { N0::n0_gptr , "n0_gptr" , N0_TYPE }, // 22 + { N0::n0_time , "n0_time" , N0_TYPE }, // 23 + { N0::n0_nx_fure , "n0_nx_fure" , N0_TYPE }, // 24 + { N0::n0_nx_gptr , "n0_nx_gptr" , N0_TYPE }, // 25 + { N0::n0_nx_time , "n0_nx_time" , N0_TYPE }, // 26 + { N0::n0_cxa0_fure , "n0_cxa0_fure" , N0_TYPE }, // 27 + { N0::n0_cxa0_gptr , "n0_cxa0_gptr" , N0_TYPE }, // 28 + { N0::n0_cxa0_time , "n0_cxa0_time" , N0_TYPE }, // 29 + { N0::n0_repr , "n0_repr" , N0_TYPE }, // 30 + { N0::n0_nx_repr , "n0_nx_repr" , N0_TYPE }, // 31 + { N0::n0_cxa0_repr , "n0_cxa0_repr" , N0_TYPE }, // 32 + { N1::n1_fure , "n1_fure" , N1_TYPE }, // 33 + { N1::n1_gptr , "n1_gptr" , N1_TYPE }, // 34 + { N1::n1_time , "n1_time" , N1_TYPE }, // 35 + { N1::n1_ioo0_fure , "n1_ioo0_fure" , N1_TYPE }, // 36 + { N1::n1_ioo0_gptr , "n1_ioo0_gptr" , N1_TYPE }, // 37 + { N1::n1_ioo0_time , "n1_ioo0_time" , N1_TYPE }, // 38 + { N1::n1_ioo1_fure , "n1_ioo1_fure" , N1_TYPE }, // 39 + { N1::n1_ioo1_gptr , "n1_ioo1_gptr" , N1_TYPE }, // 40 + { N1::n1_ioo1_time , "n1_ioo1_time" , N1_TYPE }, // 41 + { N1::n1_mcs23_fure , "n1_mcs23_fure" , N1_TYPE }, // 42 + { N1::n1_mcs23_gptr , "n1_mcs23_gptr" , N1_TYPE }, // 43 + { N1::n1_mcs23_time , "n1_mcs23_time" , N1_TYPE }, // 44 + { N1::n1_repr , "n1_repr" , N1_TYPE }, // 45 + { N1::n1_ioo0_repr , "n1_ioo0_repr" , N1_TYPE }, // 46 + { N1::n1_ioo1_repr , "n1_ioo1_repr" , N1_TYPE }, // 47 + { N1::n1_mcs23_repr , "n1_mcs23_repr" , N1_TYPE }, // 48 + { N2::n2_fure , "n2_fure" , N2_TYPE }, // 49 + { N2::n2_gptr , "n2_gptr" , N2_TYPE }, // 50 + { N2::n2_time , "n2_time" , N2_TYPE }, // 51 + { N2::n2_cxa1_fure , "n2_cxa1_fure" , N2_TYPE }, // 52 + { N2::n2_cxa1_gptr , "n2_cxa1_gptr" , N2_TYPE }, // 53 + { N2::n2_cxa1_time , "n2_cxa1_time" , N2_TYPE }, // 54 + { N2::n2_psi_fure , "n2_psi_fure" , N2_TYPE }, // 55 + { N2::n2_psi_gptr , "n2_psi_gptr" , N2_TYPE }, // 56 + { N2::n2_psi_time , "n2_psi_time" , N2_TYPE }, // 57 + { N2::n2_repr , "n2_repr" , N2_TYPE }, // 58 + { N2::n2_cxa1_repr , "n2_cxa1_repr" , N2_TYPE }, // 59 + { INVALID_RING_OFFSET , "invalid" , N2_TYPE }, // 60 + { INVALID_RING_OFFSET , "invalid" , N2_TYPE }, // 61 + { N3::n3_fure , "n3_fure" , N3_TYPE }, // 62 + { N3::n3_gptr , "n3_gptr" , N3_TYPE }, // 63 + { N3::n3_time , "n3_time" , N3_TYPE }, // 64 + { N3::n3_mcs01_fure , "n3_mcs01_fure" , N3_TYPE }, // 65 + { N3::n3_mcs01_gptr , "n3_mcs01_gptr" , N3_TYPE }, // 66 + { N3::n3_mcs01_time , "n3_mcs01_time" , N3_TYPE }, // 67 + { N3::n3_np_fure , "n3_np_fure" , N3_TYPE }, // 68 + { N3::n3_np_gptr , "n3_np_gptr" , N3_TYPE }, // 69 + { N3::n3_np_time , "n3_np_time" , N3_TYPE }, // 70 + { N3::n3_repr , "n3_repr" , N3_TYPE }, // 71 + { N3::n3_mcs01_repr , "n3_mcs01_repr" , N3_TYPE }, // 72 + { N3::n3_np_repr , "n3_np_repr" , N3_TYPE }, // 73 + { N3::n3_br_fure , "n3_br_fure" , N3_TYPE }, // 74 + { XB::xb_fure , "xb_fure" , XB_TYPE }, // 75 + { XB::xb_gptr , "xb_gptr" , XB_TYPE }, // 76 + { XB::xb_time , "xb_time" , XB_TYPE }, // 77 + { XB::xb_io0_fure , "xb_io0_fure" , XB_TYPE }, // 78 + { XB::xb_io0_gptr , "xb_io0_gptr" , XB_TYPE }, // 79 + { XB::xb_io0_time , "xb_io0_time" , XB_TYPE }, // 80 + { XB::xb_io1_fure , "xb_io1_fure" , XB_TYPE }, // 81 + { XB::xb_io1_gptr , "xb_io1_gptr" , XB_TYPE }, // 82 + { XB::xb_io1_time , "xb_io1_time" , XB_TYPE }, // 83 + { XB::xb_io2_fure , "xb_io2_fure" , XB_TYPE }, // 84 + { XB::xb_io2_gptr , "xb_io2_gptr" , XB_TYPE }, // 85 + { XB::xb_io2_time , "xb_io2_time" , XB_TYPE }, // 86 + { XB::xb_pll_gptr , "xb_pll_gptr" , XB_TYPE }, // 87 + { XB::xb_pll_bndy , "xb_pll_bndy" , XB_TYPE }, // 88 + { XB::xb_pll_func , "xb_pll_func" , XB_TYPE }, // 89 + { XB::xb_repr , "xb_repr" , XB_TYPE }, // 90 + { XB::xb_io0_repr , "xb_io0_repr" , XB_TYPE }, // 91 + { XB::xb_io1_repr , "xb_io1_repr" , XB_TYPE }, // 92 + { XB::xb_io2_repr , "xb_io2_repr" , XB_TYPE }, // 93 + { INVALID_RING_OFFSET , "invalid" , XB_TYPE }, // 94 + { INVALID_RING_OFFSET , "invalid" , XB_TYPE }, // 95 + { MC::mc_fure , "mc_fure" , MC_TYPE }, // 96 + { MC::mc_gptr , "mc_gptr" , MC_TYPE }, // 97 + { MC::mc_time , "mc_time" , MC_TYPE }, // 98 + { MC::mc_iom01_fure , "mc_iom01_fure" , MC_TYPE }, // 99 + { MC::mc_iom01_gptr , "mc_iom01_gptr" , MC_TYPE }, // 100 + { MC::mc_iom01_time , "mc_iom01_time" , MC_TYPE }, // 101 + { MC::mc_iom23_fure , "mc_iom23_fure" , MC_TYPE }, // 102 + { MC::mc_iom23_gptr , "mc_iom23_gptr" , MC_TYPE }, // 103 + { MC::mc_iom23_time , "mc_iom23_time" , MC_TYPE }, // 104 + { MC::mc_pll_gptr , "mc_pll_gptr" , MC_TYPE }, // 105 + { MC::mc_pll_bndy , "mc_pll_bndy" , MC_TYPE }, // 106 + { MC::mc_pll_bndy_bucket_1 , "mc_pll_bndy_bucket_1" , MC_TYPE }, // 107 + { MC::mc_pll_bndy_bucket_2 , "mc_pll_bndy_bucket_2" , MC_TYPE }, // 108 + { MC::mc_pll_bndy_bucket_3 , "mc_pll_bndy_bucket_3" , MC_TYPE }, // 109 + { MC::mc_pll_bndy_bucket_4 , "mc_pll_bndy_bucket_4" , MC_TYPE }, // 110 + { MC::mc_pll_bndy_bucket_5 , "mc_pll_bndy_bucket_5" , MC_TYPE }, // 111 + { MC::mc_pll_func , "mc_pll_func" , MC_TYPE }, // 112 + { MC::mc_repr , "mc_repr" , MC_TYPE }, // 113 + { INVALID_RING_OFFSET , "invalid" , MC_TYPE }, // 114 + { MC::mc_iom23_repr , "mc_iom23_repr" , MC_TYPE }, // 115 + { OB0::ob0_pll_bndy , "ob0_pll_bndy" , OB0_TYPE }, // 116 + { OB0::ob0_pll_bndy_bucket_1 , "ob0_pll_bndy_bucket_1" , OB0_TYPE }, // 117 + { OB0::ob0_pll_bndy_bucket_2 , "ob0_pll_bndy_bucket_2" , OB0_TYPE }, // 118 + { OB0::ob0_gptr , "ob0_gptr" , OB0_TYPE }, // 119 + { OB0::ob0_time , "ob0_time" , OB0_TYPE }, // 120 + { OB0::ob0_pll_gptr , "ob0_pll_gptr" , OB0_TYPE }, // 121 + { OB0::ob0_fure , "ob0_fure" , OB0_TYPE }, // 122 + { OB0::ob0_pll_bndy_bucket_3 , "ob0_pll_bndy_bucket_3" , OB0_TYPE }, // 123 + { OB0::ob0_repr , "ob0_repr" , OB0_TYPE }, // 124 + { OB1::ob1_pll_bndy , "ob1_pll_bndy" , OB1_TYPE }, // 125 + { OB1::ob1_pll_bndy_bucket_1 , "ob1_pll_bndy_bucket_1" , OB1_TYPE }, // 126 + { OB1::ob1_pll_bndy_bucket_2 , "ob1_pll_bndy_bucket_2" , OB1_TYPE }, // 127 + { OB1::ob1_gptr , "ob1_gptr" , OB1_TYPE }, // 128 + { OB1::ob1_time , "ob1_time" , OB1_TYPE }, // 129 + { OB1::ob1_pll_gptr , "ob1_pll_gptr" , OB1_TYPE }, // 130 + { OB1::ob1_fure , "ob1_fure" , OB1_TYPE }, // 131 + { OB1::ob1_pll_bndy_bucket_3 , "ob1_pll_bndy_bucket_3" , OB1_TYPE }, // 132 + { OB1::ob1_repr , "ob1_repr" , OB1_TYPE }, // 133 + { OB2::ob2_pll_bndy , "ob2_pll_bndy" , OB2_TYPE }, // 134 + { OB2::ob2_pll_bndy_bucket_1 , "ob2_pll_bndy_bucket_1" , OB2_TYPE }, // 135 + { OB2::ob2_pll_bndy_bucket_2 , "ob2_pll_bndy_bucket_2" , OB2_TYPE }, // 136 + { OB2::ob2_gptr , "ob2_gptr" , OB2_TYPE }, // 137 + { OB2::ob2_time , "ob2_time" , OB2_TYPE }, // 138 + { OB2::ob2_pll_gptr , "ob2_pll_gptr" , OB2_TYPE }, // 139 + { OB2::ob2_fure , "ob2_fure" , OB2_TYPE }, // 140 + { OB2::ob2_pll_bndy_bucket_3 , "ob2_pll_bndy_bucket_3" , OB2_TYPE }, // 141 + { OB2::ob2_repr , "ob2_repr" , OB2_TYPE }, // 142 + { OB3::ob3_pll_bndy , "ob3_pll_bndy" , OB3_TYPE }, // 143 + { OB3::ob3_pll_bndy_bucket_1 , "ob3_pll_bndy_bucket_1" , OB3_TYPE }, // 144 + { OB3::ob3_pll_bndy_bucket_2 , "ob3_pll_bndy_bucket_2" , OB3_TYPE }, // 145 + { OB3::ob3_gptr , "ob3_gptr" , OB3_TYPE }, // 146 + { OB3::ob3_time , "ob3_time" , OB3_TYPE }, // 147 + { OB3::ob3_pll_gptr , "ob3_pll_gptr" , OB3_TYPE }, // 148 + { OB3::ob3_fure , "ob3_fure" , OB3_TYPE }, // 149 + { OB3::ob3_pll_bndy_bucket_3 , "ob3_pll_bndy_bucket_3" , OB3_TYPE }, // 150 + { OB3::ob3_repr , "ob3_repr" , OB3_TYPE }, // 151 + { INVALID_RING_OFFSET , "invalid" , OB3_TYPE }, // 152 + { INVALID_RING_OFFSET , "invalid" , OB3_TYPE }, // 153 + { PCI0::pci0_fure , "pci0_fure" , PCI0_TYPE }, // 154 + { PCI0::pci0_gptr , "pci0_gptr" , PCI0_TYPE }, // 155 + { PCI0::pci0_time , "pci0_time" , PCI0_TYPE }, // 156 + { PCI0::pci0_pll_bndy , "pci0_pll_bndy" , PCI0_TYPE }, // 157 + { PCI0::pci0_pll_gptr , "pci0_pll_gptr" , PCI0_TYPE }, // 158 + { PCI0::pci0_repr , "pci0_repr" , PCI0_TYPE }, // 159 + { PCI1::pci1_fure , "pci1_fure" , PCI1_TYPE }, // 160 + { PCI1::pci1_gptr , "pci1_gptr" , PCI1_TYPE }, // 161 + { PCI1::pci1_time , "pci1_time" , PCI1_TYPE }, // 162 + { PCI1::pci1_pll_bndy , "pci1_pll_bndy" , PCI1_TYPE }, // 163 + { PCI1::pci1_pll_gptr , "pci1_pll_gptr" , PCI1_TYPE }, // 164 + { PCI1::pci1_repr , "pci1_repr" , PCI1_TYPE }, // 165 + { PCI2::pci2_fure , "pci2_fure" , PCI2_TYPE }, // 166 + { PCI2::pci2_gptr , "pci2_gptr" , PCI2_TYPE }, // 167 + { PCI2::pci2_time , "pci2_time" , PCI2_TYPE }, // 168 + { PCI2::pci2_pll_bndy , "pci2_pll_bndy" , PCI2_TYPE }, // 169 + { PCI2::pci2_pll_gptr , "pci2_pll_gptr" , PCI2_TYPE }, // 170 + { PCI2::pci2_repr , "pci2_repr" , PCI2_TYPE }, // 171 + { EQ::eq_fure , "eq_fure" , EQ_TYPE }, // 172 + { EQ::eq_gptr , "eq_gptr" , EQ_TYPE }, // 173 + { EQ::eq_time , "eq_time" , EQ_TYPE }, // 174 + { EQ::eq_inex , "eq_inex" , EQ_TYPE }, // 175 + { EQ::ex_l3_fure , "ex_l3_fure" , EQ_TYPE }, // 176 + { EQ::ex_l3_gptr , "ex_l3_gptr" , EQ_TYPE }, // 177 + { EQ::ex_l3_time , "ex_l3_time" , EQ_TYPE }, // 178 + { EQ::ex_l2_mode , "ex_l2_mode" , EQ_TYPE }, // 179 + { EQ::ex_l2_fure , "ex_l2_fure" , EQ_TYPE }, // 180 + { EQ::ex_l2_gptr , "ex_l2_gptr" , EQ_TYPE }, // 181 + { EQ::ex_l2_time , "ex_l2_time" , EQ_TYPE }, // 182 + { EQ::ex_l3_refr_fure , "ex_l3_refr_fure" , EQ_TYPE }, // 183 + { EQ::ex_l3_refr_gptr , "ex_l3_refr_gptr" , EQ_TYPE }, // 184 + { EQ::ex_l3_refr_time , "ex_l3_refr_time" , EQ_TYPE }, // 185 + { EQ::eq_ana_func , "eq_ana_func" , EQ_TYPE }, // 186 + { EQ::eq_ana_gptr , "eq_ana_gptr" , EQ_TYPE }, // 187 + { EQ::eq_dpll_func , "eq_dpll_func" , EQ_TYPE }, // 188 + { EQ::eq_dpll_gptr , "eq_dpll_gptr" , EQ_TYPE }, // 189 + { EQ::eq_dpll_mode , "eq_dpll_mode" , EQ_TYPE }, // 190 + { EQ::eq_ana_bndy , "eq_ana_bndy" , EQ_TYPE }, // 191 + { EQ::eq_ana_bndy_bucket_0 , "eq_ana_bndy_bucket_0" , EQ_TYPE }, // 192 + { EQ::eq_ana_bndy_bucket_1 , "eq_ana_bndy_bucket_1" , EQ_TYPE }, // 193 + { EQ::eq_ana_bndy_bucket_2 , "eq_ana_bndy_bucket_2" , EQ_TYPE }, // 194 + { EQ::eq_ana_bndy_bucket_3 , "eq_ana_bndy_bucket_3" , EQ_TYPE }, // 195 + { EQ::eq_ana_bndy_bucket_4 , "eq_ana_bndy_bucket_4" , EQ_TYPE }, // 196 + { EQ::eq_ana_bndy_bucket_5 , "eq_ana_bndy_bucket_5" , EQ_TYPE }, // 197 + { EQ::eq_ana_bndy_bucket_6 , "eq_ana_bndy_bucket_6" , EQ_TYPE }, // 198 + { EQ::eq_ana_bndy_bucket_7 , "eq_ana_bndy_bucket_7" , EQ_TYPE }, // 199 + { EQ::eq_ana_bndy_bucket_8 , "eq_ana_bndy_bucket_8" , EQ_TYPE }, // 200 + { EQ::eq_ana_bndy_bucket_9 , "eq_ana_bndy_bucket_9" , EQ_TYPE }, // 201 + { EQ::eq_ana_bndy_bucket_10 , "eq_ana_bndy_bucket_10" , EQ_TYPE }, // 202 + { EQ::eq_ana_bndy_bucket_11 , "eq_ana_bndy_bucket_11" , EQ_TYPE }, // 203 + { EQ::eq_ana_bndy_bucket_12 , "eq_ana_bndy_bucket_12" , EQ_TYPE }, // 204 + { EQ::eq_ana_bndy_bucket_13 , "eq_ana_bndy_bucket_13" , EQ_TYPE }, // 205 + { EQ::eq_ana_bndy_bucket_14 , "eq_ana_bndy_bucket_14" , EQ_TYPE }, // 206 + { EQ::eq_ana_bndy_bucket_15 , "eq_ana_bndy_bucket_15" , EQ_TYPE }, // 207 + { EQ::eq_ana_bndy_bucket_16 , "eq_ana_bndy_bucket_16" , EQ_TYPE }, // 208 + { EQ::eq_ana_bndy_bucket_17 , "eq_ana_bndy_bucket_17" , EQ_TYPE }, // 209 + { EQ::eq_ana_bndy_bucket_18 , "eq_ana_bndy_bucket_18" , EQ_TYPE }, // 210 + { EQ::eq_ana_bndy_bucket_19 , "eq_ana_bndy_bucket_19" , EQ_TYPE }, // 211 + { EQ::eq_ana_bndy_bucket_20 , "eq_ana_bndy_bucket_20" , EQ_TYPE }, // 212 + { EQ::eq_ana_bndy_bucket_21 , "eq_ana_bndy_bucket_21" , EQ_TYPE }, // 213 + { EQ::eq_ana_bndy_bucket_22 , "eq_ana_bndy_bucket_22" , EQ_TYPE }, // 214 + { EQ::eq_ana_bndy_bucket_23 , "eq_ana_bndy_bucket_23" , EQ_TYPE }, // 215 + { EQ::eq_ana_bndy_bucket_24 , "eq_ana_bndy_bucket_24" , EQ_TYPE }, // 216 + { EQ::eq_ana_bndy_bucket_25 , "eq_ana_bndy_bucket_25" , EQ_TYPE }, // 217 + { EQ::eq_ana_bndy_bucket_l3dcc , "eq_ana_bndy_bucket_l3dcc" , EQ_TYPE }, // 218 + { EQ::eq_ana_mode , "eq_ana_mode" , EQ_TYPE }, // 219 + { EQ::eq_repr , "eq_repr" , EQ_TYPE }, // 220 + { EQ::ex_l3_repr , "ex_l3_repr" , EQ_TYPE }, // 221 + { EQ::ex_l2_repr , "ex_l2_repr" , EQ_TYPE }, // 222 + { EQ::ex_l3_refr_repr , "ex_l3_refr_repr" , EQ_TYPE }, // 223 + { EC::ec_func , "ec_func" , EC_TYPE }, // 224 + { EC::ec_gptr , "ec_gptr" , EC_TYPE }, // 225 + { EC::ec_time , "ec_time" , EC_TYPE }, // 226 + { EC::ec_mode , "ec_mode" , EC_TYPE }, // 227 + { EC::ec_repr , "ec_repr" , EC_TYPE }, // 228 + { INVALID_RING_OFFSET , "invalid" , EQ_TYPE }, // 229 + { INVALID_RING_OFFSET , "invalid" , EQ_TYPE }, // 230 + { EC::ec_abst , "ec_abst" , EC_TYPE }, // 231 + { EQ::eq_ana_bndy_bucket_26 , "eq_ana_bndy_bucket_26" , EQ_TYPE }, // 232 + { EQ::eq_ana_bndy_bucket_27 , "eq_ana_bndy_bucket_27" , EQ_TYPE }, // 233 + { EQ::eq_ana_bndy_bucket_28 , "eq_ana_bndy_bucket_28" , EQ_TYPE }, // 234 + { EQ::eq_ana_bndy_bucket_29 , "eq_ana_bndy_bucket_29" , EQ_TYPE }, // 235 + { EQ::eq_ana_bndy_bucket_30 , "eq_ana_bndy_bucket_30" , EQ_TYPE }, // 236 + { EQ::eq_ana_bndy_bucket_31 , "eq_ana_bndy_bucket_31" , EQ_TYPE }, // 237 + { EQ::eq_ana_bndy_bucket_32 , "eq_ana_bndy_bucket_32" , EQ_TYPE }, // 238 + { EQ::eq_ana_bndy_bucket_33 , "eq_ana_bndy_bucket_33" , EQ_TYPE }, // 239 + { EQ::eq_ana_bndy_bucket_34 , "eq_ana_bndy_bucket_34" , EQ_TYPE }, // 240 + { EQ::eq_ana_bndy_bucket_35 , "eq_ana_bndy_bucket_35" , EQ_TYPE }, // 241 + { EQ::eq_ana_bndy_bucket_36 , "eq_ana_bndy_bucket_36" , EQ_TYPE }, // 242 + { EQ::eq_ana_bndy_bucket_37 , "eq_ana_bndy_bucket_37" , EQ_TYPE }, // 243 + { EQ::eq_ana_bndy_bucket_38 , "eq_ana_bndy_bucket_38" , EQ_TYPE }, // 244 + { EQ::eq_ana_bndy_bucket_39 , "eq_ana_bndy_bucket_39" , EQ_TYPE }, // 245 + { EQ::eq_ana_bndy_bucket_40 , "eq_ana_bndy_bucket_40" , EQ_TYPE }, // 246 + { EQ::eq_ana_bndy_bucket_41 , "eq_ana_bndy_bucket_41" , EQ_TYPE }, // 247 + { EQ::eq_inex_bucket_1 , "eq_inex_bucket_1" , EQ_TYPE }, // 248 + { EQ::eq_inex_bucket_2 , "eq_inex_bucket_2" , EQ_TYPE }, // 249 + { EQ::eq_inex_bucket_3 , "eq_inex_bucket_3" , EQ_TYPE }, // 250 + { EQ::eq_inex_bucket_4 , "eq_inex_bucket_4" , EQ_TYPE }, // 251 + { EC::ec_cmsk , "ec_cmsk" , EC_TYPE }, // 252 + { PERV::perv_pll_bndy_flt_1 , "perv_pll_bndy_flt_1" , PERV_TYPE }, // 253 + { PERV::perv_pll_bndy_flt_2 , "perv_pll_bndy_flt_2" , PERV_TYPE }, // 254 + { PERV::perv_pll_bndy_flt_3 , "perv_pll_bndy_flt_3" , PERV_TYPE }, // 255 + { PERV::perv_pll_bndy_flt_4 , "perv_pll_bndy_flt_4" , PERV_TYPE }, // 256 + { MC::mc_omi0_fure , "mc_omi0_fure" , MC_TYPE }, // 257 + { MC::mc_omi0_gptr , "mc_omi0_gptr" , MC_TYPE }, // 258 + { MC::mc_omi1_fure , "mc_omi1_fure" , MC_TYPE }, // 259 + { MC::mc_omi1_gptr , "mc_omi1_gptr" , MC_TYPE }, // 260 + { MC::mc_omi2_fure , "mc_omi2_fure" , MC_TYPE }, // 261 + { MC::mc_omi2_gptr , "mc_omi2_gptr" , MC_TYPE }, // 262 + { MC::mc_omippe_fure , "mc_omippe_fure" , MC_TYPE }, // 263 + { MC::mc_omippe_gptr , "mc_omippe_gptr" , MC_TYPE }, // 264 + { MC::mc_omippe_time , "mc_omippe_time" , MC_TYPE }, // 265 + { MC::mc_omippe_repr , "mc_omippe_repr" , MC_TYPE }, // 266 }; #endif #ifdef __PPE__ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { - { PERV::perv_fure , PERV_TYPE }, // 0 - { PERV::perv_gptr , PERV_TYPE }, // 1 - { PERV::perv_time , PERV_TYPE }, // 2 - { PERV::occ_fure , PERV_TYPE }, // 3 - { PERV::occ_gptr , PERV_TYPE }, // 4 - { PERV::occ_time , PERV_TYPE }, // 5 - { PERV::perv_ana_func , PERV_TYPE }, // 6 - { PERV::perv_ana_gptr , PERV_TYPE }, // 7 - { PERV::perv_pll_gptr , PERV_TYPE }, // 8 - { PERV::perv_pll_bndy , PERV_TYPE }, // 9 - { PERV::perv_pll_bndy_bucket_1 , PERV_TYPE }, // 10 - { PERV::perv_pll_bndy_bucket_2 , PERV_TYPE }, // 11 - { PERV::perv_pll_bndy_bucket_3 , PERV_TYPE }, // 12 - { PERV::perv_pll_bndy_bucket_4 , PERV_TYPE }, // 13 - { PERV::perv_pll_bndy_bucket_5 , PERV_TYPE }, // 14 - { PERV::perv_pll_func , PERV_TYPE }, // 15 - { PERV::perv_repr , PERV_TYPE }, // 16 - { PERV::occ_repr , PERV_TYPE }, // 17 - { PERV::sbe_fure , PERV_TYPE }, // 18 - { PERV::sbe_gptr , PERV_TYPE }, // 19 - { PERV::sbe_repr , PERV_TYPE }, // 20 - { N0::n0_fure , N0_TYPE }, // 21 - { N0::n0_gptr , N0_TYPE }, // 22 - { N0::n0_time , N0_TYPE }, // 23 - { N0::n0_nx_fure , N0_TYPE }, // 24 - { N0::n0_nx_gptr , N0_TYPE }, // 25 - { N0::n0_nx_time , N0_TYPE }, // 26 - { N0::n0_cxa0_fure , N0_TYPE }, // 27 - { N0::n0_cxa0_gptr , N0_TYPE }, // 28 - { N0::n0_cxa0_time , N0_TYPE }, // 29 - { N0::n0_repr , N0_TYPE }, // 30 - { N0::n0_nx_repr , N0_TYPE }, // 31 - { N0::n0_cxa0_repr , N0_TYPE }, // 32 - { N1::n1_fure , N1_TYPE }, // 33 - { N1::n1_gptr , N1_TYPE }, // 34 - { N1::n1_time , N1_TYPE }, // 35 - { N1::n1_ioo0_fure , N1_TYPE }, // 36 - { N1::n1_ioo0_gptr , N1_TYPE }, // 37 - { N1::n1_ioo0_time , N1_TYPE }, // 38 - { N1::n1_ioo1_fure , N1_TYPE }, // 39 - { N1::n1_ioo1_gptr , N1_TYPE }, // 40 - { N1::n1_ioo1_time , N1_TYPE }, // 41 - { N1::n1_mcs23_fure , N1_TYPE }, // 42 - { N1::n1_mcs23_gptr , N1_TYPE }, // 43 - { N1::n1_mcs23_time , N1_TYPE }, // 44 - { N1::n1_repr , N1_TYPE }, // 45 - { N1::n1_ioo0_repr , N1_TYPE }, // 46 - { N1::n1_ioo1_repr , N1_TYPE }, // 47 - { N1::n1_mcs23_repr , N1_TYPE }, // 48 - { N2::n2_fure , N2_TYPE }, // 49 - { N2::n2_gptr , N2_TYPE }, // 50 - { N2::n2_time , N2_TYPE }, // 51 - { N2::n2_cxa1_fure , N2_TYPE }, // 52 - { N2::n2_cxa1_gptr , N2_TYPE }, // 53 - { N2::n2_cxa1_time , N2_TYPE }, // 54 - { N2::n2_psi_fure , N2_TYPE }, // 55 - { N2::n2_psi_gptr , N2_TYPE }, // 56 - { N2::n2_psi_time , N2_TYPE }, // 57 - { N2::n2_repr , N2_TYPE }, // 58 - { N2::n2_cxa1_repr , N2_TYPE }, // 59 - { INVALID_RING_OFFSET , N2_TYPE }, // 60 - { INVALID_RING_OFFSET , N2_TYPE }, // 61 - { N3::n3_fure , N3_TYPE }, // 62 - { N3::n3_gptr , N3_TYPE }, // 63 - { N3::n3_time , N3_TYPE }, // 64 - { N3::n3_mcs01_fure , N3_TYPE }, // 65 - { N3::n3_mcs01_gptr , N3_TYPE }, // 66 - { N3::n3_mcs01_time , N3_TYPE }, // 67 - { N3::n3_np_fure , N3_TYPE }, // 68 - { N3::n3_np_gptr , N3_TYPE }, // 69 - { N3::n3_np_time , N3_TYPE }, // 70 - { N3::n3_repr , N3_TYPE }, // 71 - { N3::n3_mcs01_repr , N3_TYPE }, // 72 - { N3::n3_np_repr , N3_TYPE }, // 73 - { N3::n3_br_fure , N3_TYPE }, // 74 - { XB::xb_fure , XB_TYPE }, // 75 - { XB::xb_gptr , XB_TYPE }, // 76 - { XB::xb_time , XB_TYPE }, // 77 - { XB::xb_io0_fure , XB_TYPE }, // 78 - { XB::xb_io0_gptr , XB_TYPE }, // 79 - { XB::xb_io0_time , XB_TYPE }, // 80 - { XB::xb_io1_fure , XB_TYPE }, // 81 - { XB::xb_io1_gptr , XB_TYPE }, // 82 - { XB::xb_io1_time , XB_TYPE }, // 83 - { XB::xb_io2_fure , XB_TYPE }, // 84 - { XB::xb_io2_gptr , XB_TYPE }, // 85 - { XB::xb_io2_time , XB_TYPE }, // 86 - { XB::xb_pll_gptr , XB_TYPE }, // 87 - { XB::xb_pll_bndy , XB_TYPE }, // 88 - { XB::xb_pll_func , XB_TYPE }, // 89 - { XB::xb_repr , XB_TYPE }, // 90 - { XB::xb_io0_repr , XB_TYPE }, // 91 - { XB::xb_io1_repr , XB_TYPE }, // 92 - { XB::xb_io2_repr , XB_TYPE }, // 93 - { INVALID_RING_OFFSET , XB_TYPE }, // 94 - { INVALID_RING_OFFSET , XB_TYPE }, // 95 - { MC::mc_fure , MC_TYPE }, // 96 - { MC::mc_gptr , MC_TYPE }, // 97 - { MC::mc_time , MC_TYPE }, // 98 - { MC::mc_iom01_fure , MC_TYPE }, // 99 - { MC::mc_iom01_gptr , MC_TYPE }, // 100 - { MC::mc_iom01_time , MC_TYPE }, // 101 - { MC::mc_iom23_fure , MC_TYPE }, // 102 - { MC::mc_iom23_gptr , MC_TYPE }, // 103 - { MC::mc_iom23_time , MC_TYPE }, // 104 - { MC::mc_pll_gptr , MC_TYPE }, // 105 - { MC::mc_pll_bndy , MC_TYPE }, // 106 - { MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 107 - { MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 108 - { MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 109 - { MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 110 - { MC::mc_pll_bndy_bucket_5 , MC_TYPE }, // 111 - { MC::mc_pll_func , MC_TYPE }, // 112 - { MC::mc_repr , MC_TYPE }, // 113 - { INVALID_RING_OFFSET , MC_TYPE }, // 114 - { MC::mc_iom23_repr , MC_TYPE }, // 115 - { OB0::ob0_pll_bndy , OB0_TYPE }, // 116 - { OB0::ob0_pll_bndy_bucket_1 , OB0_TYPE }, // 117 - { OB0::ob0_pll_bndy_bucket_2 , OB0_TYPE }, // 118 - { OB0::ob0_gptr , OB0_TYPE }, // 119 - { OB0::ob0_time , OB0_TYPE }, // 120 - { OB0::ob0_pll_gptr , OB0_TYPE }, // 121 - { OB0::ob0_fure , OB0_TYPE }, // 122 - { OB0::ob0_pll_bndy_bucket_3 , OB0_TYPE }, // 123 - { OB0::ob0_repr , OB0_TYPE }, // 124 - { OB1::ob1_pll_bndy , OB1_TYPE }, // 125 - { OB1::ob1_pll_bndy_bucket_1 , OB1_TYPE }, // 126 - { OB1::ob1_pll_bndy_bucket_2 , OB1_TYPE }, // 127 - { OB1::ob1_gptr , OB1_TYPE }, // 128 - { OB1::ob1_time , OB1_TYPE }, // 129 - { OB1::ob1_pll_gptr , OB1_TYPE }, // 130 - { OB1::ob1_fure , OB1_TYPE }, // 131 - { OB1::ob1_pll_bndy_bucket_3 , OB1_TYPE }, // 132 - { OB1::ob1_repr , OB1_TYPE }, // 133 - { OB2::ob2_pll_bndy , OB2_TYPE }, // 134 - { OB2::ob2_pll_bndy_bucket_1 , OB2_TYPE }, // 135 - { OB2::ob2_pll_bndy_bucket_2 , OB2_TYPE }, // 136 - { OB2::ob2_gptr , OB2_TYPE }, // 137 - { OB2::ob2_time , OB2_TYPE }, // 138 - { OB2::ob2_pll_gptr , OB2_TYPE }, // 139 - { OB2::ob2_fure , OB2_TYPE }, // 140 - { OB2::ob2_pll_bndy_bucket_3 , OB2_TYPE }, // 141 - { OB2::ob2_repr , OB2_TYPE }, // 142 - { OB3::ob3_pll_bndy , OB3_TYPE }, // 143 - { OB3::ob3_pll_bndy_bucket_1 , OB3_TYPE }, // 144 - { OB3::ob3_pll_bndy_bucket_2 , OB3_TYPE }, // 145 - { OB3::ob3_gptr , OB3_TYPE }, // 146 - { OB3::ob3_time , OB3_TYPE }, // 147 - { OB3::ob3_pll_gptr , OB3_TYPE }, // 148 - { OB3::ob3_fure , OB3_TYPE }, // 149 - { OB3::ob3_pll_bndy_bucket_3 , OB3_TYPE }, // 150 - { OB3::ob3_repr , OB3_TYPE }, // 151 - { INVALID_RING_OFFSET , OB3_TYPE }, // 152 - { INVALID_RING_OFFSET , OB3_TYPE }, // 153 - { PCI0::pci0_fure , PCI0_TYPE }, // 154 - { PCI0::pci0_gptr , PCI0_TYPE }, // 155 - { PCI0::pci0_time , PCI0_TYPE }, // 156 - { PCI0::pci0_pll_bndy , PCI0_TYPE }, // 157 - { PCI0::pci0_pll_gptr , PCI0_TYPE }, // 158 - { PCI0::pci0_repr , PCI0_TYPE }, // 159 - { PCI1::pci1_fure , PCI1_TYPE }, // 160 - { PCI1::pci1_gptr , PCI1_TYPE }, // 161 - { PCI1::pci1_time , PCI1_TYPE }, // 162 - { PCI1::pci1_pll_bndy , PCI1_TYPE }, // 163 - { PCI1::pci1_pll_gptr , PCI1_TYPE }, // 164 - { PCI1::pci1_repr , PCI1_TYPE }, // 165 - { PCI2::pci2_fure , PCI2_TYPE }, // 166 - { PCI2::pci2_gptr , PCI2_TYPE }, // 167 - { PCI2::pci2_time , PCI2_TYPE }, // 168 - { PCI2::pci2_pll_bndy , PCI2_TYPE }, // 169 - { PCI2::pci2_pll_gptr , PCI2_TYPE }, // 170 - { PCI2::pci2_repr , PCI2_TYPE }, // 171 - { EQ::eq_fure , EQ_TYPE }, // 172 - { EQ::eq_gptr , EQ_TYPE }, // 173 - { EQ::eq_time , EQ_TYPE }, // 174 - { EQ::eq_inex , EQ_TYPE }, // 175 - { EQ::ex_l3_fure , EQ_TYPE }, // 176 - { EQ::ex_l3_gptr , EQ_TYPE }, // 177 - { EQ::ex_l3_time , EQ_TYPE }, // 178 - { EQ::ex_l2_mode , EQ_TYPE }, // 179 - { EQ::ex_l2_fure , EQ_TYPE }, // 180 - { EQ::ex_l2_gptr , EQ_TYPE }, // 181 - { EQ::ex_l2_time , EQ_TYPE }, // 182 - { EQ::ex_l3_refr_fure , EQ_TYPE }, // 183 - { EQ::ex_l3_refr_gptr , EQ_TYPE }, // 184 - { EQ::ex_l3_refr_time , EQ_TYPE }, // 185 - { EQ::eq_ana_func , EQ_TYPE }, // 186 - { EQ::eq_ana_gptr , EQ_TYPE }, // 187 - { EQ::eq_dpll_func , EQ_TYPE }, // 188 - { EQ::eq_dpll_gptr , EQ_TYPE }, // 189 - { EQ::eq_dpll_mode , EQ_TYPE }, // 190 - { EQ::eq_ana_bndy , EQ_TYPE }, // 191 - { EQ::eq_ana_bndy_bucket_0 , EQ_TYPE }, // 192 - { EQ::eq_ana_bndy_bucket_1 , EQ_TYPE }, // 193 - { EQ::eq_ana_bndy_bucket_2 , EQ_TYPE }, // 194 - { EQ::eq_ana_bndy_bucket_3 , EQ_TYPE }, // 195 - { EQ::eq_ana_bndy_bucket_4 , EQ_TYPE }, // 196 - { EQ::eq_ana_bndy_bucket_5 , EQ_TYPE }, // 197 - { EQ::eq_ana_bndy_bucket_6 , EQ_TYPE }, // 198 - { EQ::eq_ana_bndy_bucket_7 , EQ_TYPE }, // 199 - { EQ::eq_ana_bndy_bucket_8 , EQ_TYPE }, // 200 - { EQ::eq_ana_bndy_bucket_9 , EQ_TYPE }, // 201 - { EQ::eq_ana_bndy_bucket_10 , EQ_TYPE }, // 202 - { EQ::eq_ana_bndy_bucket_11 , EQ_TYPE }, // 203 - { EQ::eq_ana_bndy_bucket_12 , EQ_TYPE }, // 204 - { EQ::eq_ana_bndy_bucket_13 , EQ_TYPE }, // 205 - { EQ::eq_ana_bndy_bucket_14 , EQ_TYPE }, // 206 - { EQ::eq_ana_bndy_bucket_15 , EQ_TYPE }, // 207 - { EQ::eq_ana_bndy_bucket_16 , EQ_TYPE }, // 208 - { EQ::eq_ana_bndy_bucket_17 , EQ_TYPE }, // 209 - { EQ::eq_ana_bndy_bucket_18 , EQ_TYPE }, // 210 - { EQ::eq_ana_bndy_bucket_19 , EQ_TYPE }, // 211 - { EQ::eq_ana_bndy_bucket_20 , EQ_TYPE }, // 212 - { EQ::eq_ana_bndy_bucket_21 , EQ_TYPE }, // 213 - { EQ::eq_ana_bndy_bucket_22 , EQ_TYPE }, // 214 - { EQ::eq_ana_bndy_bucket_23 , EQ_TYPE }, // 215 - { EQ::eq_ana_bndy_bucket_24 , EQ_TYPE }, // 216 - { EQ::eq_ana_bndy_bucket_25 , EQ_TYPE }, // 217 - { EQ::eq_ana_bndy_bucket_l3dcc , EQ_TYPE }, // 218 - { EQ::eq_ana_mode , EQ_TYPE }, // 219 - { EQ::eq_repr , EQ_TYPE }, // 220 - { EQ::ex_l3_repr , EQ_TYPE }, // 221 - { EQ::ex_l2_repr , EQ_TYPE }, // 222 - { EQ::ex_l3_refr_repr , EQ_TYPE }, // 223 - { EC::ec_func , EC_TYPE }, // 224 - { EC::ec_gptr , EC_TYPE }, // 225 - { EC::ec_time , EC_TYPE }, // 226 - { EC::ec_mode , EC_TYPE }, // 227 - { EC::ec_repr , EC_TYPE }, // 228 - { INVALID_RING_OFFSET , EQ_TYPE }, // 229 - { INVALID_RING_OFFSET , EQ_TYPE }, // 230 - { EC::ec_abst , EC_TYPE }, // 231 - { EQ::eq_ana_bndy_bucket_26 , EQ_TYPE }, // 232 - { EQ::eq_ana_bndy_bucket_27 , EQ_TYPE }, // 233 - { EQ::eq_ana_bndy_bucket_28 , EQ_TYPE }, // 234 - { EQ::eq_ana_bndy_bucket_29 , EQ_TYPE }, // 235 - { EQ::eq_ana_bndy_bucket_30 , EQ_TYPE }, // 236 - { EQ::eq_ana_bndy_bucket_31 , EQ_TYPE }, // 237 - { EQ::eq_ana_bndy_bucket_32 , EQ_TYPE }, // 238 - { EQ::eq_ana_bndy_bucket_33 , EQ_TYPE }, // 239 - { EQ::eq_ana_bndy_bucket_34 , EQ_TYPE }, // 240 - { EQ::eq_ana_bndy_bucket_35 , EQ_TYPE }, // 241 - { EQ::eq_ana_bndy_bucket_36 , EQ_TYPE }, // 242 - { EQ::eq_ana_bndy_bucket_37 , EQ_TYPE }, // 243 - { EQ::eq_ana_bndy_bucket_38 , EQ_TYPE }, // 244 - { EQ::eq_ana_bndy_bucket_39 , EQ_TYPE }, // 245 - { EQ::eq_ana_bndy_bucket_40 , EQ_TYPE }, // 246 - { EQ::eq_ana_bndy_bucket_41 , EQ_TYPE }, // 247 - { EQ::eq_inex_bucket_1 , EQ_TYPE }, // 248 - { EQ::eq_inex_bucket_2 , EQ_TYPE }, // 249 - { EQ::eq_inex_bucket_3 , EQ_TYPE }, // 250 - { EQ::eq_inex_bucket_4 , EQ_TYPE }, // 251 - { EC::ec_cmsk , EC_TYPE }, // 252 - { PERV::perv_pll_bndy_flt_1 , PERV_TYPE }, // 253 - { PERV::perv_pll_bndy_flt_2 , PERV_TYPE }, // 254 - { PERV::perv_pll_bndy_flt_3 , PERV_TYPE }, // 255 - { PERV::perv_pll_bndy_flt_4 , PERV_TYPE }, // 256 - { MC::mc_omi0_fure , MC_TYPE }, // 257 - { MC::mc_omi0_gptr , MC_TYPE }, // 258 - { MC::mc_omi1_fure , MC_TYPE }, // 259 - { MC::mc_omi1_gptr , MC_TYPE }, // 260 - { MC::mc_omi2_fure , MC_TYPE }, // 261 - { MC::mc_omi2_gptr , MC_TYPE }, // 262 - { MC::mc_omippe_fure , MC_TYPE }, // 263 - { MC::mc_omippe_gptr , MC_TYPE }, // 264 - { MC::mc_omippe_time , MC_TYPE }, // 265 - { MC::mc_omippe_repr , MC_TYPE }, // 266 + { PERV::perv_fure , PERV_TYPE }, // 0 + { PERV::perv_gptr , PERV_TYPE }, // 1 + { PERV::perv_time , PERV_TYPE }, // 2 + { PERV::occ_fure , PERV_TYPE }, // 3 + { PERV::occ_gptr , PERV_TYPE }, // 4 + { PERV::occ_time , PERV_TYPE }, // 5 + { PERV::perv_ana_func , PERV_TYPE }, // 6 + { PERV::perv_ana_gptr , PERV_TYPE }, // 7 + { PERV::perv_pll_gptr , PERV_TYPE }, // 8 + { PERV::perv_pll_bndy , PERV_TYPE }, // 9 + { PERV::perv_pll_bndy_bucket_1 , PERV_TYPE }, // 10 + { PERV::perv_pll_bndy_bucket_2 , PERV_TYPE }, // 11 + { PERV::perv_pll_bndy_bucket_3 , PERV_TYPE }, // 12 + { PERV::perv_pll_bndy_bucket_4 , PERV_TYPE }, // 13 + { PERV::perv_pll_bndy_bucket_5 , PERV_TYPE }, // 14 + { PERV::perv_pll_func , PERV_TYPE }, // 15 + { PERV::perv_repr , PERV_TYPE }, // 16 + { PERV::occ_repr , PERV_TYPE }, // 17 + { PERV::sbe_fure , PERV_TYPE }, // 18 + { PERV::sbe_gptr , PERV_TYPE }, // 19 + { PERV::sbe_repr , PERV_TYPE }, // 20 + { N0::n0_fure , N0_TYPE }, // 21 + { N0::n0_gptr , N0_TYPE }, // 22 + { N0::n0_time , N0_TYPE }, // 23 + { N0::n0_nx_fure , N0_TYPE }, // 24 + { N0::n0_nx_gptr , N0_TYPE }, // 25 + { N0::n0_nx_time , N0_TYPE }, // 26 + { N0::n0_cxa0_fure , N0_TYPE }, // 27 + { N0::n0_cxa0_gptr , N0_TYPE }, // 28 + { N0::n0_cxa0_time , N0_TYPE }, // 29 + { N0::n0_repr , N0_TYPE }, // 30 + { N0::n0_nx_repr , N0_TYPE }, // 31 + { N0::n0_cxa0_repr , N0_TYPE }, // 32 + { N1::n1_fure , N1_TYPE }, // 33 + { N1::n1_gptr , N1_TYPE }, // 34 + { N1::n1_time , N1_TYPE }, // 35 + { N1::n1_ioo0_fure , N1_TYPE }, // 36 + { N1::n1_ioo0_gptr , N1_TYPE }, // 37 + { N1::n1_ioo0_time , N1_TYPE }, // 38 + { N1::n1_ioo1_fure , N1_TYPE }, // 39 + { N1::n1_ioo1_gptr , N1_TYPE }, // 40 + { N1::n1_ioo1_time , N1_TYPE }, // 41 + { N1::n1_mcs23_fure , N1_TYPE }, // 42 + { N1::n1_mcs23_gptr , N1_TYPE }, // 43 + { N1::n1_mcs23_time , N1_TYPE }, // 44 + { N1::n1_repr , N1_TYPE }, // 45 + { N1::n1_ioo0_repr , N1_TYPE }, // 46 + { N1::n1_ioo1_repr , N1_TYPE }, // 47 + { N1::n1_mcs23_repr , N1_TYPE }, // 48 + { N2::n2_fure , N2_TYPE }, // 49 + { N2::n2_gptr , N2_TYPE }, // 50 + { N2::n2_time , N2_TYPE }, // 51 + { N2::n2_cxa1_fure , N2_TYPE }, // 52 + { N2::n2_cxa1_gptr , N2_TYPE }, // 53 + { N2::n2_cxa1_time , N2_TYPE }, // 54 + { N2::n2_psi_fure , N2_TYPE }, // 55 + { N2::n2_psi_gptr , N2_TYPE }, // 56 + { N2::n2_psi_time , N2_TYPE }, // 57 + { N2::n2_repr , N2_TYPE }, // 58 + { N2::n2_cxa1_repr , N2_TYPE }, // 59 + { INVALID_RING_OFFSET , N2_TYPE }, // 60 + { INVALID_RING_OFFSET , N2_TYPE }, // 61 + { N3::n3_fure , N3_TYPE }, // 62 + { N3::n3_gptr , N3_TYPE }, // 63 + { N3::n3_time , N3_TYPE }, // 64 + { N3::n3_mcs01_fure , N3_TYPE }, // 65 + { N3::n3_mcs01_gptr , N3_TYPE }, // 66 + { N3::n3_mcs01_time , N3_TYPE }, // 67 + { N3::n3_np_fure , N3_TYPE }, // 68 + { N3::n3_np_gptr , N3_TYPE }, // 69 + { N3::n3_np_time , N3_TYPE }, // 70 + { N3::n3_repr , N3_TYPE }, // 71 + { N3::n3_mcs01_repr , N3_TYPE }, // 72 + { N3::n3_np_repr , N3_TYPE }, // 73 + { N3::n3_br_fure , N3_TYPE }, // 74 + { XB::xb_fure , XB_TYPE }, // 75 + { XB::xb_gptr , XB_TYPE }, // 76 + { XB::xb_time , XB_TYPE }, // 77 + { XB::xb_io0_fure , XB_TYPE }, // 78 + { XB::xb_io0_gptr , XB_TYPE }, // 79 + { XB::xb_io0_time , XB_TYPE }, // 80 + { XB::xb_io1_fure , XB_TYPE }, // 81 + { XB::xb_io1_gptr , XB_TYPE }, // 82 + { XB::xb_io1_time , XB_TYPE }, // 83 + { XB::xb_io2_fure , XB_TYPE }, // 84 + { XB::xb_io2_gptr , XB_TYPE }, // 85 + { XB::xb_io2_time , XB_TYPE }, // 86 + { XB::xb_pll_gptr , XB_TYPE }, // 87 + { XB::xb_pll_bndy , XB_TYPE }, // 88 + { XB::xb_pll_func , XB_TYPE }, // 89 + { XB::xb_repr , XB_TYPE }, // 90 + { XB::xb_io0_repr , XB_TYPE }, // 91 + { XB::xb_io1_repr , XB_TYPE }, // 92 + { XB::xb_io2_repr , XB_TYPE }, // 93 + { INVALID_RING_OFFSET , XB_TYPE }, // 94 + { INVALID_RING_OFFSET , XB_TYPE }, // 95 + { MC::mc_fure , MC_TYPE }, // 96 + { MC::mc_gptr , MC_TYPE }, // 97 + { MC::mc_time , MC_TYPE }, // 98 + { MC::mc_iom01_fure , MC_TYPE }, // 99 + { MC::mc_iom01_gptr , MC_TYPE }, // 100 + { MC::mc_iom01_time , MC_TYPE }, // 101 + { MC::mc_iom23_fure , MC_TYPE }, // 102 + { MC::mc_iom23_gptr , MC_TYPE }, // 103 + { MC::mc_iom23_time , MC_TYPE }, // 104 + { MC::mc_pll_gptr , MC_TYPE }, // 105 + { MC::mc_pll_bndy , MC_TYPE }, // 106 + { MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 107 + { MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 108 + { MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 109 + { MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 110 + { MC::mc_pll_bndy_bucket_5 , MC_TYPE }, // 111 + { MC::mc_pll_func , MC_TYPE }, // 112 + { MC::mc_repr , MC_TYPE }, // 113 + { INVALID_RING_OFFSET , MC_TYPE }, // 114 + { MC::mc_iom23_repr , MC_TYPE }, // 115 + { OB0::ob0_pll_bndy , OB0_TYPE }, // 116 + { OB0::ob0_pll_bndy_bucket_1 , OB0_TYPE }, // 117 + { OB0::ob0_pll_bndy_bucket_2 , OB0_TYPE }, // 118 + { OB0::ob0_gptr , OB0_TYPE }, // 119 + { OB0::ob0_time , OB0_TYPE }, // 120 + { OB0::ob0_pll_gptr , OB0_TYPE }, // 121 + { OB0::ob0_fure , OB0_TYPE }, // 122 + { OB0::ob0_pll_bndy_bucket_3 , OB0_TYPE }, // 123 + { OB0::ob0_repr , OB0_TYPE }, // 124 + { OB1::ob1_pll_bndy , OB1_TYPE }, // 125 + { OB1::ob1_pll_bndy_bucket_1 , OB1_TYPE }, // 126 + { OB1::ob1_pll_bndy_bucket_2 , OB1_TYPE }, // 127 + { OB1::ob1_gptr , OB1_TYPE }, // 128 + { OB1::ob1_time , OB1_TYPE }, // 129 + { OB1::ob1_pll_gptr , OB1_TYPE }, // 130 + { OB1::ob1_fure , OB1_TYPE }, // 131 + { OB1::ob1_pll_bndy_bucket_3 , OB1_TYPE }, // 132 + { OB1::ob1_repr , OB1_TYPE }, // 133 + { OB2::ob2_pll_bndy , OB2_TYPE }, // 134 + { OB2::ob2_pll_bndy_bucket_1 , OB2_TYPE }, // 135 + { OB2::ob2_pll_bndy_bucket_2 , OB2_TYPE }, // 136 + { OB2::ob2_gptr , OB2_TYPE }, // 137 + { OB2::ob2_time , OB2_TYPE }, // 138 + { OB2::ob2_pll_gptr , OB2_TYPE }, // 139 + { OB2::ob2_fure , OB2_TYPE }, // 140 + { OB2::ob2_pll_bndy_bucket_3 , OB2_TYPE }, // 141 + { OB2::ob2_repr , OB2_TYPE }, // 142 + { OB3::ob3_pll_bndy , OB3_TYPE }, // 143 + { OB3::ob3_pll_bndy_bucket_1 , OB3_TYPE }, // 144 + { OB3::ob3_pll_bndy_bucket_2 , OB3_TYPE }, // 145 + { OB3::ob3_gptr , OB3_TYPE }, // 146 + { OB3::ob3_time , OB3_TYPE }, // 147 + { OB3::ob3_pll_gptr , OB3_TYPE }, // 148 + { OB3::ob3_fure , OB3_TYPE }, // 149 + { OB3::ob3_pll_bndy_bucket_3 , OB3_TYPE }, // 150 + { OB3::ob3_repr , OB3_TYPE }, // 151 + { INVALID_RING_OFFSET , OB3_TYPE }, // 152 + { INVALID_RING_OFFSET , OB3_TYPE }, // 153 + { PCI0::pci0_fure , PCI0_TYPE }, // 154 + { PCI0::pci0_gptr , PCI0_TYPE }, // 155 + { PCI0::pci0_time , PCI0_TYPE }, // 156 + { PCI0::pci0_pll_bndy , PCI0_TYPE }, // 157 + { PCI0::pci0_pll_gptr , PCI0_TYPE }, // 158 + { PCI0::pci0_repr , PCI0_TYPE }, // 159 + { PCI1::pci1_fure , PCI1_TYPE }, // 160 + { PCI1::pci1_gptr , PCI1_TYPE }, // 161 + { PCI1::pci1_time , PCI1_TYPE }, // 162 + { PCI1::pci1_pll_bndy , PCI1_TYPE }, // 163 + { PCI1::pci1_pll_gptr , PCI1_TYPE }, // 164 + { PCI1::pci1_repr , PCI1_TYPE }, // 165 + { PCI2::pci2_fure , PCI2_TYPE }, // 166 + { PCI2::pci2_gptr , PCI2_TYPE }, // 167 + { PCI2::pci2_time , PCI2_TYPE }, // 168 + { PCI2::pci2_pll_bndy , PCI2_TYPE }, // 169 + { PCI2::pci2_pll_gptr , PCI2_TYPE }, // 170 + { PCI2::pci2_repr , PCI2_TYPE }, // 171 + { EQ::eq_fure , EQ_TYPE }, // 172 + { EQ::eq_gptr , EQ_TYPE }, // 173 + { EQ::eq_time , EQ_TYPE }, // 174 + { EQ::eq_inex , EQ_TYPE }, // 175 + { EQ::ex_l3_fure , EQ_TYPE }, // 176 + { EQ::ex_l3_gptr , EQ_TYPE }, // 177 + { EQ::ex_l3_time , EQ_TYPE }, // 178 + { EQ::ex_l2_mode , EQ_TYPE }, // 179 + { EQ::ex_l2_fure , EQ_TYPE }, // 180 + { EQ::ex_l2_gptr , EQ_TYPE }, // 181 + { EQ::ex_l2_time , EQ_TYPE }, // 182 + { EQ::ex_l3_refr_fure , EQ_TYPE }, // 183 + { EQ::ex_l3_refr_gptr , EQ_TYPE }, // 184 + { EQ::ex_l3_refr_time , EQ_TYPE }, // 185 + { EQ::eq_ana_func , EQ_TYPE }, // 186 + { EQ::eq_ana_gptr , EQ_TYPE }, // 187 + { EQ::eq_dpll_func , EQ_TYPE }, // 188 + { EQ::eq_dpll_gptr , EQ_TYPE }, // 189 + { EQ::eq_dpll_mode , EQ_TYPE }, // 190 + { EQ::eq_ana_bndy , EQ_TYPE }, // 191 + { EQ::eq_ana_bndy_bucket_0 , EQ_TYPE }, // 192 + { EQ::eq_ana_bndy_bucket_1 , EQ_TYPE }, // 193 + { EQ::eq_ana_bndy_bucket_2 , EQ_TYPE }, // 194 + { EQ::eq_ana_bndy_bucket_3 , EQ_TYPE }, // 195 + { EQ::eq_ana_bndy_bucket_4 , EQ_TYPE }, // 196 + { EQ::eq_ana_bndy_bucket_5 , EQ_TYPE }, // 197 + { EQ::eq_ana_bndy_bucket_6 , EQ_TYPE }, // 198 + { EQ::eq_ana_bndy_bucket_7 , EQ_TYPE }, // 199 + { EQ::eq_ana_bndy_bucket_8 , EQ_TYPE }, // 200 + { EQ::eq_ana_bndy_bucket_9 , EQ_TYPE }, // 201 + { EQ::eq_ana_bndy_bucket_10 , EQ_TYPE }, // 202 + { EQ::eq_ana_bndy_bucket_11 , EQ_TYPE }, // 203 + { EQ::eq_ana_bndy_bucket_12 , EQ_TYPE }, // 204 + { EQ::eq_ana_bndy_bucket_13 , EQ_TYPE }, // 205 + { EQ::eq_ana_bndy_bucket_14 , EQ_TYPE }, // 206 + { EQ::eq_ana_bndy_bucket_15 , EQ_TYPE }, // 207 + { EQ::eq_ana_bndy_bucket_16 , EQ_TYPE }, // 208 + { EQ::eq_ana_bndy_bucket_17 , EQ_TYPE }, // 209 + { EQ::eq_ana_bndy_bucket_18 , EQ_TYPE }, // 210 + { EQ::eq_ana_bndy_bucket_19 , EQ_TYPE }, // 211 + { EQ::eq_ana_bndy_bucket_20 , EQ_TYPE }, // 212 + { EQ::eq_ana_bndy_bucket_21 , EQ_TYPE }, // 213 + { EQ::eq_ana_bndy_bucket_22 , EQ_TYPE }, // 214 + { EQ::eq_ana_bndy_bucket_23 , EQ_TYPE }, // 215 + { EQ::eq_ana_bndy_bucket_24 , EQ_TYPE }, // 216 + { EQ::eq_ana_bndy_bucket_25 , EQ_TYPE }, // 217 + { EQ::eq_ana_bndy_bucket_l3dcc , EQ_TYPE }, // 218 + { EQ::eq_ana_mode , EQ_TYPE }, // 219 + { EQ::eq_repr , EQ_TYPE }, // 220 + { EQ::ex_l3_repr , EQ_TYPE }, // 221 + { EQ::ex_l2_repr , EQ_TYPE }, // 222 + { EQ::ex_l3_refr_repr , EQ_TYPE }, // 223 + { EC::ec_func , EC_TYPE }, // 224 + { EC::ec_gptr , EC_TYPE }, // 225 + { EC::ec_time , EC_TYPE }, // 226 + { EC::ec_mode , EC_TYPE }, // 227 + { EC::ec_repr , EC_TYPE }, // 228 + { INVALID_RING_OFFSET , EQ_TYPE }, // 229 + { INVALID_RING_OFFSET , EQ_TYPE }, // 230 + { EC::ec_abst , EC_TYPE }, // 231 + { EQ::eq_ana_bndy_bucket_26 , EQ_TYPE }, // 232 + { EQ::eq_ana_bndy_bucket_27 , EQ_TYPE }, // 233 + { EQ::eq_ana_bndy_bucket_28 , EQ_TYPE }, // 234 + { EQ::eq_ana_bndy_bucket_29 , EQ_TYPE }, // 235 + { EQ::eq_ana_bndy_bucket_30 , EQ_TYPE }, // 236 + { EQ::eq_ana_bndy_bucket_31 , EQ_TYPE }, // 237 + { EQ::eq_ana_bndy_bucket_32 , EQ_TYPE }, // 238 + { EQ::eq_ana_bndy_bucket_33 , EQ_TYPE }, // 239 + { EQ::eq_ana_bndy_bucket_34 , EQ_TYPE }, // 240 + { EQ::eq_ana_bndy_bucket_35 , EQ_TYPE }, // 241 + { EQ::eq_ana_bndy_bucket_36 , EQ_TYPE }, // 242 + { EQ::eq_ana_bndy_bucket_37 , EQ_TYPE }, // 243 + { EQ::eq_ana_bndy_bucket_38 , EQ_TYPE }, // 244 + { EQ::eq_ana_bndy_bucket_39 , EQ_TYPE }, // 245 + { EQ::eq_ana_bndy_bucket_40 , EQ_TYPE }, // 246 + { EQ::eq_ana_bndy_bucket_41 , EQ_TYPE }, // 247 + { EQ::eq_inex_bucket_1 , EQ_TYPE }, // 248 + { EQ::eq_inex_bucket_2 , EQ_TYPE }, // 249 + { EQ::eq_inex_bucket_3 , EQ_TYPE }, // 250 + { EQ::eq_inex_bucket_4 , EQ_TYPE }, // 251 + { EC::ec_cmsk , EC_TYPE }, // 252 + { PERV::perv_pll_bndy_flt_1 , PERV_TYPE }, // 253 + { PERV::perv_pll_bndy_flt_2 , PERV_TYPE }, // 254 + { PERV::perv_pll_bndy_flt_3 , PERV_TYPE }, // 255 + { PERV::perv_pll_bndy_flt_4 , PERV_TYPE }, // 256 + { MC::mc_omi0_fure , MC_TYPE }, // 257 + { MC::mc_omi0_gptr , MC_TYPE }, // 258 + { MC::mc_omi1_fure , MC_TYPE }, // 259 + { MC::mc_omi1_gptr , MC_TYPE }, // 260 + { MC::mc_omi2_fure , MC_TYPE }, // 261 + { MC::mc_omi2_gptr , MC_TYPE }, // 262 + { MC::mc_omippe_fure , MC_TYPE }, // 263 + { MC::mc_omippe_gptr , MC_TYPE }, // 264 + { MC::mc_omippe_time , MC_TYPE }, // 265 + { MC::mc_omippe_repr , MC_TYPE }, // 266 }; #endif -// Returns data structure assocated with chipletType +// Returns our own chiplet enum value for this ringId +ChipletType_t +ringid_get_chiplet(RingId_t i_ringId); + +// Returns data structures defined for chiplet type +// as determined by ringId void ringid_get_chiplet_properties( ChipletType_t i_chipletType, - ChipletData_t** o_chipletData); + ChipletData_t** o_cpltData, + GenRingIdList** o_ringComm, + GenRingIdList** o_ringInst, + RingVariantOrder** o_varOrder, + uint8_t* o_numVariants); + +// Returns properties of a ring as determined by ringId +GenRingIdList* +_ringid_get_ring_list(RingId_t i_ringId); #endif diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.C b/src/import/chips/p9/utils/imageProcs/p9_tor.C index 44bf731e0..143c5c7ba 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.C +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.C @@ -51,287 +51,245 @@ int get_ring_from_ring_section( void* i_ringSection, // Ring secti uint32_t i_dbgl ) // Debug option { int rc = TOR_SUCCESS; + uint8_t iInst, iRing, iVariant; TorHeader_t* torHeader; uint32_t torMagic; uint8_t torVersion; - ChipId_t chipId; + uint8_t chipType; TorCpltBlock_t* cpltBlock; TorCpltOffset_t cpltOffset; // Offset from ringSection to chiplet section TorRingOffset_t ringOffset; // Offset to actual ring container uint32_t torSlotNum; // TOR slot number (within a chiplet section) uint32_t ringSize; // Size of whole ring container/block. - RingVariant_t* ringVariantOrder; + RingVariantOrder* ringVariantOrder; RingId_t numRings; - ChipletType_t chipletType = UNDEFINED_CHIPLET_TYPE; - ChipletType_t chipletIndex = UNDEFINED_CHIPLET_TYPE; // Effective chiplet index - MyBool_t bInstCase = UNDEFINED_BOOLEAN; - ChipletData_t* chipletData; - uint8_t numInstances; + GenRingIdList* ringIdListCommon; + GenRingIdList* ringIdListInstance; + GenRingIdList* ringIdList; + uint8_t bInstCase = 0; + ChipletData_t* cpltData; uint8_t numVariants; - RingProperties_t* ringProps = NULL; - uint8_t idxRingEff; // Effective chiplet ring index - uint8_t iInst, iRing, iVariant; // Index counters for instance, chiplet rings, variant + ChipletType_t numChiplets; + RingProperties_t* ringProps; torHeader = (TorHeader_t*)i_ringSection; torMagic = be32toh(torHeader->magic); torVersion = torHeader->version; - chipId = torHeader->chipId; + chipType = torHeader->chipType; - // - // Get main ring properties list for the chip ID - // - rc = ringid_get_ringProps( chipId, - &ringProps ); - - if (rc) - { - MY_ERR("ringid_get_ringProps() failed w/rc=0x%08x\n", rc); - return rc; - } - - chipletType = ringProps[i_ringId].chipletType; - - // - // Get all other metadata for the chipletType - // - rc = ringid_get_chipletProps( chipId, - torMagic, - torHeader->version, - chipletType, - &chipletData, - &numVariants ); + rc = ringid_get_noof_chiplets( chipType, + torMagic, + &numChiplets); if (rc) { - MY_ERR("ringid_get_chipletProps() failed w/rc=0x%08x\n", rc); + MY_ERR("ringid_get_noof_chiplets() failed w/rc=0x%08x\n", rc); return rc; } - ringVariantOrder = chipletData->ringVariantOrder; - // - // Check the scope of chipletType and Get the effective chipletType's index + // Looper for each SBE chipleti // - rc = ringid_get_chipletIndex( chipId, - torMagic, - chipletType, - &chipletIndex ); - - if (rc) + for (ChipletType_t iCplt = 0; iCplt < numChiplets; iCplt++) { - if ( rc == TOR_INVALID_CHIPLET_TYPE ) - { - // Many things could have lead to this error. It's not necessarily fatal or even - // unacceptable. For example, xip_tool will hit this one a lot, so we can't trace - // out here. Instead, for now, we're just returning TOR_INVALID_CHIPLET_TYPE. - // But maybe this needs to change in future. - return rc; - } - else + rc = ringid_get_properties( chipType, + torMagic, + torHeader->version, + iCplt, + &cpltData, + &ringIdListCommon, + &ringIdListInstance, + &ringVariantOrder, + &ringProps, + &numVariants ); + + if (rc) { - MY_ERR("ringid_get_chipletIndex() failed w/rc=0x%08x\n", rc); + MY_ERR("ringid_get_properties() failed w/rc=0x%08x\n", rc); return rc; } - } - - // - // Determine whether Common or Instance section based on the INSTANCE_RING_MARK - // - if ( ringProps[i_ringId].idxRing & INSTANCE_RING_MARK ) - { - bInstCase = 1; - } - else - { - bInstCase = 0; - } - - // - // Calculate various loop upper limits - // - numInstances = bInstCase ? - chipletData->numChipletInstances : - 1; - - numRings = bInstCase ? - chipletData->numInstanceRings : - chipletData->numCommonRings; - - idxRingEff = ringProps[i_ringId].idxRing & INSTANCE_RING_MASK; // Always safe - - // Adjust number of variants according to TOR version of image - if (torVersion < 7) - { - // Nothing to do. Number of variants is the same for Common and Instance rings. - } - else - { - numVariants = bInstCase ? - 1 : // Only BASE variant for Instance rings - numVariants; - } - - // Unless we find a ring, then the following rc will be returned - rc = TOR_RING_HAS_NO_TOR_SLOT; - // - // Now traverse the chiplet's Common or Instance ring section - // - if (numRings) // Only proceed if chiplet has [Common/Instance] rings. - { - // Calc offset to chiplet's CMN or INST section, cpltOffset (steps 1-3) // - // 1. Calc offset to TOR slot pointing to chiplet's COM or INST section - cpltOffset = sizeof(TorHeader_t) + - chipletIndex * sizeof(TorCpltBlock_t) + - bInstCase * sizeof(cpltBlock->cmnOffset); - // 2. Retrive offset, endian convert and make it relative to ring section origin - cpltOffset = *(uint32_t*)( (uint8_t*)i_ringSection + cpltOffset ); - cpltOffset = be32toh(cpltOffset); - // 3. Make offset relative to ring section origin - cpltOffset = sizeof(TorHeader_t) + cpltOffset; - - torSlotNum = 0; - - for ( iInst = 0; iInst < numInstances; iInst++ ) + // Sequentially traverse ring offset slots within a chiplet's CMN or INST section + // + for ( bInstCase = 0; bInstCase <= 1; bInstCase++ ) { - for ( iRing = 0; iRing < numRings; iRing++ ) + numRings = bInstCase ? cpltData->iv_num_instance_rings : cpltData->iv_num_common_rings; + ringIdList = bInstCase ? ringIdListInstance : ringIdListCommon; + + // Adjust number of variants according to TOR version of image + if (torVersion < 7) + { + // Nothing to do. Number of variants is the same for Common and Instance rings. + } + else { - for ( iVariant = 0; iVariant < numVariants; iVariant++ ) + numVariants = bInstCase ? 1 : numVariants; // Only BASE variant for Instance rings + } + + if (ringIdList) // Only proceed if chiplet has [Common/Instance] rings. + { + // Calc offset to chiplet's CMN or INST section, cpltOffset (steps 1-3) + // + // 1. Calc offset to TOR slot pointing to chiplet's COM or INST section + cpltOffset = sizeof(TorHeader_t) + + iCplt * sizeof(TorCpltBlock_t) + + bInstCase * sizeof(cpltBlock->cmnOffset); + // 2. Retrive offset, endian convert and make it relative to ring section origin + cpltOffset = *(uint32_t*)( (uint8_t*)i_ringSection + cpltOffset ); + cpltOffset = be32toh(cpltOffset); + // 3. Make offset relative to ring section origin + cpltOffset = sizeof(TorHeader_t) + cpltOffset; + + torSlotNum = 0; + + for ( iInst = ringIdList->instanceIdMin; + iInst <= ringIdList->instanceIdMax; + iInst++ ) { - if ( idxRingEff == iRing && // We're already in the right chiplet here! - ( i_ringVariant == ringVariantOrder[iVariant] || - // Support overrides etc where ringVariant doesn't necessarily apply - ( numVariants == 1 && i_ringVariant == UNDEFINED_RING_VARIANT ) ) && - ( !bInstCase || ( bInstCase && iInst == (io_instanceId - chipletData->chipletBaseId) ) ) ) + for ( iRing = 0; iRing < numRings; iRing++ ) { - strcpy(o_ringName, ringProps[i_ringId].ringName); - - // Calc offset to actual ring, ringOffset (steps 1-3) - // - // 1. Calc offset to TOR slot pointing to actual ring - ringOffset = cpltOffset + torSlotNum * sizeof(ringOffset); - // 2. Retrieve offset and endian convert - ringOffset = *(TorRingOffset_t*)( (uint8_t*)i_ringSection + ringOffset ); - ringOffset = be16toh(ringOffset); - - if (i_ringBlockType == GET_SINGLE_RING) + for ( iVariant = 0; iVariant < numVariants; iVariant++ ) { - ringSize = 0; - - if (ringOffset) + if ( strcmp( (ringIdList + iRing)->ringName, + ringProps[i_ringId].iv_name ) == 0 && + ( i_ringVariant == ringVariantOrder->variant[iVariant] || + numVariants == 1 ) && // If no variants, ignore i_ringVariant and assume "BASE" ring + ( !bInstCase || ( bInstCase && iInst == io_instanceId ) ) ) { - // 3. Make offset relative to ring section origin - ringOffset = cpltOffset + ringOffset; + strcpy(o_ringName, (ringIdList + iRing)->ringName); - ringSize = be16toh( ((CompressedScanData*) - ((uint8_t*)i_ringSection + ringOffset))->iv_size ); + // Calc offset to actual ring, ringOffset (steps 1-3) + // + // 1. Calc offset to TOR slot pointing to actual ring + ringOffset = cpltOffset + torSlotNum * sizeof(ringOffset); + // 2. Retrieve offset and endian convert + ringOffset = *(TorRingOffset_t*)( (uint8_t*)i_ringSection + ringOffset ); + ringOffset = be16toh(ringOffset); - if (io_ringBlockSize == 0) + if (i_ringBlockType == GET_SINGLE_RING) { + ringSize = 0; + + if (ringOffset) + { + // 3. Make offset relative to ring section origin + ringOffset = cpltOffset + ringOffset; + + ringSize = be16toh( ((CompressedScanData*) + ((uint8_t*)i_ringSection + ringOffset))->iv_size ); + + if (io_ringBlockSize == 0) + { + if (i_dbgl > 0) + { + MY_DBG("io_ringBlockSize is zero. Returning required size.\n"); + } + + io_ringBlockSize = ringSize; + return TOR_SUCCESS; + } + + if (io_ringBlockSize < ringSize) + { + MY_ERR("io_ringBlockSize is less than required size.\n"); + return TOR_BUFFER_TOO_SMALL; + } + + // Produce return parms + memcpy( *io_ringBlockPtr, (uint8_t*)i_ringSection + ringOffset, ringSize); + io_ringBlockSize = ringSize; + io_instanceId = (bInstCase) ? io_instanceId : (ringIdList + iRing)->instanceIdMin; + + if (i_dbgl > 0) + { + MY_DBG("Found a ring:\n" \ + " Name: %s\n" \ + " Blocksize: %d\n", + o_ringName, io_ringBlockSize); + } + + rc = TOR_SUCCESS; + } + else + { + if (i_dbgl > 0) + { + MY_DBG("Ring %s was not found.\n", o_ringName); + } + + rc = TOR_RING_NOT_FOUND; + } + if (i_dbgl > 0) { - MY_DBG("io_ringBlockSize is zero. Returning required size.\n"); + MY_DBG("Details for chiplet ring index=%d: \n" + " Full offset to chiplet section = 0x%08x \n" + " Full offset to RS4 header = 0x%08x \n" + " Ring size = 0x%08x \n", + iRing, cpltOffset, ringOffset, ringSize); } - io_ringBlockSize = ringSize; - return TOR_SUCCESS; - } + return rc; - if (io_ringBlockSize < ringSize) - { - MY_ERR("io_ringBlockSize is less than required size.\n"); - return TOR_BUFFER_TOO_SMALL; } + else if (i_ringBlockType == PUT_SINGLE_RING) + { + if (ringOffset) + { + MY_ERR("Ring container is already present in image\n"); + MY_ERR(" Ring section addr: 0x%016lx (First 8B: 0x%016lx)\n", + (uintptr_t)i_ringSection, + be64toh(*((uint64_t*)i_ringSection))); + MY_ERR(" cpltOffset=0x%08x, torSlotNum=0x%x, TOR offset=0x%04x\n", + cpltOffset, torSlotNum, ringOffset); + return TOR_RING_AVAILABLE_IN_RINGSECTION; + } - // Produce return parms - memcpy( *io_ringBlockPtr, (uint8_t*)i_ringSection + ringOffset, ringSize); - io_ringBlockSize = ringSize; - io_instanceId = bInstCase ? - io_instanceId : - chipletData->chipletBaseId; + // Special [mis]use of io_ringBlockPtr and io_ringBlockSize: + // Put location of chiplet's CMN or INST section into ringBlockPtr + memcpy( *io_ringBlockPtr, &cpltOffset, sizeof(cpltOffset)); + // Put location of ringOffset slot into ringBlockSize + io_ringBlockSize = cpltOffset + (torSlotNum * sizeof(ringOffset)); - if (i_dbgl > 0) - { - MY_DBG("Found a ring:\n" \ - " Name: %s\n" \ - " Blocksize: %d\n", - o_ringName, io_ringBlockSize); + return TOR_SUCCESS; } - - rc = TOR_SUCCESS; - } - else - { - if (i_dbgl > 0) + else { - MY_DBG("ringName=%s was found but is empty\n", - o_ringName); + MY_ERR("Ring block type (i_ringBlockType=%d) is not supported\n", i_ringBlockType); + return TOR_INVALID_RING_BLOCK_TYPE; } - - rc = TOR_RING_IS_EMPTY; } - if (i_dbgl > 0) - { - MY_DBG("Details for chiplet ring index=%d: \n" - " Full offset to chiplet section = 0x%08x \n" - " Full offset to RS4 header = 0x%08x \n" - " Ring size = 0x%08x \n", - iRing, cpltOffset, ringOffset, ringSize); - } - - return rc; - - } - else if (i_ringBlockType == PUT_SINGLE_RING) - { - if (ringOffset) - { - MY_ERR("Ring container is already present in image\n"); - MY_ERR(" Ring section addr: 0x%016lx (First 8B: 0x%016lx)\n", - (uintptr_t)i_ringSection, - be64toh(*((uint64_t*)i_ringSection))); - MY_ERR(" cpltOffset=0x%08x, torSlotNum=0x%x, TOR offset=0x%04x\n", - cpltOffset, torSlotNum, ringOffset); - return TOR_RING_IS_POPULATED; - } - - // Special [mis]use of io_ringBlockPtr and io_ringBlockSize: - // Put location of chiplet's CMN or INST section into ringBlockPtr - memcpy( *io_ringBlockPtr, &cpltOffset, sizeof(cpltOffset)); - // Put location of ringOffset slot into ringBlockSize - io_ringBlockSize = cpltOffset + (torSlotNum * sizeof(ringOffset)); - - return TOR_SUCCESS; - } - else - { - MY_ERR("Ring block type (i_ringBlockType=%d) is not supported\n", i_ringBlockType); - return TOR_INVALID_RING_BLOCK_TYPE; + torSlotNum++; // Next TOR ring slot } } - - torSlotNum++; // Next TOR ring slot } } - } - } - else // Code bug if we get here + else // Since there's no Common/Instance rings, set RING_NOT_FOUND + { + // Note that if we get here, it's because the chiplet doesn't have either + // a Common or Instance rings. This happens e.g. for Centaur which has + // no Instance rings. And theoretically, it's possible to only have + // Instance rings and no Common rings, so accommodating that as well here. + if (i_dbgl > 0) + { + MY_DBG("Chiplet=%d has no CMN(%d) or INST(%d) section\n", + iCplt, (1 - bInstCase), bInstCase); + } + + rc = TOR_RING_NOT_FOUND; + + } // if (ringIdList) + } // for (bInstCase) + } // for (iCplt) + + if (i_dbgl > 0) { - MY_ERR("CODE BUG: We can't have a ring section with no rings (i.e., no ring slots)." - " Check RING_PROPERTIES and ChipletData lists for :\n" - "chipId: %d\n" - "torMagic: %d\n" - "ringId: 0x%x\n" - "chipletType: %d\n" - "bInstCase: %d\n", - chipId, torMagic, i_ringId, chipletType, bInstCase); - - return INFRASTRUCT_RC_CODE_BUG; - } // if (numRings) + MY_DBG("i_ringId=0x%x is an invalid ring ID\n", i_ringId); + } - return rc; + return TOR_INVALID_RING_ID; } // End of get_ring_from_ring_section() @@ -372,14 +330,14 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr MY_DBG("TOR header fields\n" " magic: 0x%08x\n" " version: %d\n" - " chipId: %d\n" + " chipType: %d\n" " ddLevel: 0x%x\n" " size: %d\n" "API parms\n" " i_ddLevel: 0x%x\n" " i_ppeType: %d\n" " i_ringVariant: %d\n", - torMagic, torHeader->version, torHeader->chipId, + torMagic, torHeader->version, torHeader->chipType, torHeader->ddLevel, be32toh(torHeader->size), i_ddLevel, i_ppeType, i_ringVariant); @@ -402,23 +360,19 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr } if ( torMagic >> 8 != TOR_MAGIC || - // Check that we're not trying to be "forward" compatible to a newer image - torHeader->version > TOR_VERSION || - // Make sure version is set + torHeader->version > TOR_VERSION || // Code cannot be forward compatible to a newer image torHeader->version == 0 || - // Check for valid chip ID and for valid ring ID - ringid_check_ringId(torHeader->chipId, i_ringId) != INFRASTRUCT_RC_SUCCESS ) + torHeader->chipType >= NUM_CHIP_TYPES ) { - MY_ERR("Invalid TOR header or ringId:\n" - " magic: 0x%08x (TOR_MAGIC: 0x%08x)\n" - " version: %d (TOR_VERSION: %d)\n" - " chipId: %d\n" - " ringId: 0x%x\n" + MY_ERR("Invalid TOR header:\n" + " magic: 0x%08x\n" + " version: %d\n" + " chipType: %d\n" " ddLevel: 0x%x (requested ddLevel=0x%x)\n" " size: %d\n", - torMagic, TOR_MAGIC, torHeader->version, TOR_VERSION, - torHeader->chipId, i_ringId, torHeader->ddLevel, - i_ddLevel, be32toh(torHeader->size)); + torMagic, torHeader->version, torHeader->chipType, + torHeader->ddLevel, i_ddLevel, + be32toh(torHeader->size)); return TOR_INVALID_MAGIC_NUMBER; } @@ -571,6 +525,7 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr int tor_get_block_of_rings ( void* i_ringSection, // Ring section ptr uint8_t i_ddLevel, // DD level PpeType_t i_ppeType, // SBE,CME,SGPE + RingVariant_t i_ringVariant, // Base,CC,RL void** io_ringBlockPtr, // Output ring buffer uint32_t& io_ringBlockSize, // Size of ring data uint32_t i_dbgl ) // Debug option @@ -579,7 +534,7 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section uint8_t l_instanceId; char i_ringName[MAX_RING_NAME_LENGTH]; uint32_t torMagic; - ChipId_t chipId = UNDEFINED_CHIP_ID; + ChipType_t chipType = UNDEFINED_CHIP_TYPE; TorHeader_t* torHeader; if (i_dbgl > 1) @@ -589,9 +544,9 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section torHeader = (TorHeader_t*)i_ringSection; torMagic = be32toh(torHeader->magic); - chipId = torHeader->chipId; + chipType = torHeader->chipType; - if ( torMagic == TOR_MAGIC_HW && chipId != CID_CEN ) + if ( torMagic == TOR_MAGIC_HW && chipType != CT_CEN ) { if (i_ppeType == PT_SBE || i_ppeType == PT_CME || i_ppeType == PT_SGPE) { @@ -600,7 +555,7 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section UNDEFINED_RING_ID, i_ddLevel, i_ppeType, - UNDEFINED_RING_VARIANT, + i_ringVariant, l_instanceId, GET_PPE_LEVEL_RINGS, io_ringBlockPtr, @@ -616,8 +571,8 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section } else { - MY_ERR("tor_get_block_of_rings(): Only the P9 HW ring section is supported. However, torMagic=0x%08x and chipId=%d\n", - torMagic, chipId); + MY_ERR("tor_get_block_of_rings(): Only the P9 HW ring section is supported. However, torMagic=0x%08x and chipType=%d\n", + torMagic, chipType); return TOR_UNSUPPORTED_RING_SECTION; } diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.H b/src/import/chips/p9/utils/imageProcs/p9_tor.H index 52e281a17..65e863167 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.H +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.H @@ -184,6 +184,10 @@ int tor_get_single_ring ( void* i_ringSection, /// TOR API uses Ppe type to extract single ring or block of rings /// on either hw_image or SBE image /// +/// \param[in] i_RingVariant A enum to indicate which variant type of +/// requested for single ring extract. There are three major types. +/// They are base, Cache contained and Risk level ring +/// /// \param[in/out] io_ringBlockPtr A void point to pointer. Returns data /// which copied block of rings. Note: Caller's responsibility for free() /// to avoid memory leak @@ -202,6 +206,7 @@ int tor_get_single_ring ( void* i_ringSection, int tor_get_block_of_rings ( void* i_ringSection, uint8_t i_ddLevel, PpeType_t i_PpeType, + RingVariant_t i_RingVariant, void** io_ringBlockPtr, uint32_t& io_ringBlockSize, uint32_t i_dbgl = 0 ); diff --git a/src/import/chips/p9/xip/p9_xip_image.h b/src/import/chips/p9/xip/p9_xip_image.h index 42b35e0b1..d5e8cc43c 100644 --- a/src/import/chips/p9/xip/p9_xip_image.h +++ b/src/import/chips/p9/xip/p9_xip_image.h @@ -708,7 +708,7 @@ int p9_xip_get_section(const void* i_image, const int i_sectionId, P9XipSection* o_hostSection, -#ifdef __PPE__ +#if defined(__PPE__) uint8_t i_ddLevel); #else uint8_t i_ddLevel=UNDEFINED_DD_LEVEL); @@ -1489,8 +1489,8 @@ p9_xip_decode_toc_dump(void* i_image, void* i_dump, /// Attempt to grow the image past its defined memory allocation #define P9_XIP_WOULD_OVERFLOW 14 -/// Error returned from an TOR API function. -#define P9_XIP_TOR_API_ERROR 15 +/// Error associated with the disassembler occured. +#define P9_XIP_DISASSEMBLER_ERROR 15 /// Hash collision creating the .fixed_toc section #define P9_XIP_HASH_COLLISION 16 diff --git a/src/usr/fapi2/plat_utils.C b/src/usr/fapi2/plat_utils.C index 93956fde1..ee1fde715 100644 --- a/src/usr/fapi2/plat_utils.C +++ b/src/usr/fapi2/plat_utils.C @@ -342,9 +342,10 @@ ReturnCode get_ring(Target<TARGET_TYPE_MEMBUF_CHIP>i_target, // return the ring lenght in bits o_ringLength = l_ringSizeInBits; - // grab the address from the main ring id list - uint32_t l_ringAddress = UNDEFINED_SCOM_ADDR; - rc = ringid_get_scanScomAddr(CID_CEN, l_ringId, &l_ringAddress); + // grab the address from the Generic ring id list + GenRingIdList* l_idList; + + rc = ringid_get_ring_list(CT_CEN, l_ringId, &l_idList); if (rc != INFRASTRUCT_RC_SUCCESS) { @@ -376,7 +377,8 @@ ReturnCode get_ring(Target<TARGET_TYPE_MEMBUF_CHIP>i_target, break; } - o_ringAddress = l_ringAddress; + o_ringAddress = l_idList->scanScomAddress; + } else { diff --git a/src/usr/sbe/sbe_update.C b/src/usr/sbe/sbe_update.C index 14193b1f9..cfa3372ec 100644 --- a/src/usr/sbe/sbe_update.C +++ b/src/usr/sbe/sbe_update.C @@ -1137,7 +1137,7 @@ namespace SBE (void*)RING_SEC_VADDR, l_ringSectionBufSize, SYSPHASE_HB_SBE, - 0, //Was MODEBUILD_IPL=0 but not used in P9 + MODEBUILD_IPL, (void*)RING_BUF1_VADDR, (uint32_t)MAX_RING_BUF_SIZE, (void*)RING_BUF2_VADDR, |
