diff options
Diffstat (limited to 'src/usr')
-rw-r--r-- | src/usr/isteps/istep08/call_host_slave_sbe_config.C | 54 | ||||
-rwxr-xr-x | src/usr/targeting/targetservicestart.C | 7 | ||||
-rw-r--r-- | src/usr/util/utilmbox_scratch.C | 15 |
3 files changed, 60 insertions, 16 deletions
diff --git a/src/usr/isteps/istep08/call_host_slave_sbe_config.C b/src/usr/isteps/istep08/call_host_slave_sbe_config.C index 4867b6b6e..cf0300ba5 100644 --- a/src/usr/isteps/istep08/call_host_slave_sbe_config.C +++ b/src/usr/isteps/istep08/call_host_slave_sbe_config.C @@ -61,6 +61,7 @@ #include <errl/errludtarget.H> #include <p9_setup_sbe_config.H> +#include <initservice/mboxRegs.H> using namespace ISTEP_ERROR; using namespace ERRORLOG; @@ -78,13 +79,56 @@ void* call_host_slave_sbe_config(void *io_pArgs) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_slave_sbe_config entry" ); + TARGETING::Target* l_pMasterProcTarget = NULL; + TARGETING::targetService().masterProcChipTargetHandle(l_pMasterProcTarget); + + TARGETING::Target* l_sys = NULL; + targetService().getTopLevelTarget(l_sys); + assert( l_sys != NULL ); + + // Setup the boot flags attribute for the slaves based on the data + // from the master proc + INITSERVICE::SPLESS::MboxScratch3_t l_scratch3; + uint64_t l_scratch3scom = 0; + size_t scomsize = sizeof(l_scratch3scom); + l_errl = deviceRead( l_pMasterProcTarget, + &l_scratch3scom, + scomsize, + DEVICE_SCOM_ADDRESS( + INITSERVICE::SPLESS::MBOX_SCRATCH_REG3 ) ); + if( l_errl ) + { + // Create IStep error log and cross reference error that occurred + l_stepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, ISTEP_COMP_ID ); + + // Just make some reasonable guesses... + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Failed to read MBOX Scratch3" ); + + l_scratch3.data32 = 0; + l_scratch3.fspAttached = INITSERVICE::spBaseServicesEnabled(); + l_scratch3.sbeFFDC = 0; + l_scratch3.sbeInternalFFDC = 1; + } + else + { + // data is in bits 0:31 + l_scratch3.data32 = static_cast<uint32_t>(l_scratch3scom >> 32); + + // turn off the istep bit + l_scratch3.istepMode = 0; + } + // write the attribute + l_sys->setAttr<ATTR_BOOT_FLAGS>(l_scratch3.data32); + + // execute p9_setup_sbe_config.C for non-primary processor targets TARGETING::TargetHandleList l_cpuTargetList; getAllChips(l_cpuTargetList, TYPE_PROC); - TARGETING::Target* l_pMasterProcTarget = NULL; - TARGETING::targetService().masterProcChipTargetHandle(l_pMasterProcTarget); - for (const auto & l_cpu_target: l_cpuTargetList) { // do not call HWP on master processor @@ -111,7 +155,7 @@ void* call_host_slave_sbe_config(void *io_pArgs) "PLID=0x%x", l_errl->plid() ); // Commit Error - errlCommit( l_errl, HWPF_COMP_ID ); + errlCommit( l_errl, ISTEP_COMP_ID ); } } } // end of cycling through all processor chips @@ -126,7 +170,7 @@ void* call_host_slave_sbe_config(void *io_pArgs) l_stepError.addErrorDetails( err ); // Commit Error - errlCommit( err, HWPF_COMP_ID ); + errlCommit( err, ISTEP_COMP_ID ); } #endif TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C index 853db5ebd..c1f23a1f8 100755 --- a/src/usr/targeting/targetservicestart.C +++ b/src/usr/targeting/targetservicestart.C @@ -246,17 +246,18 @@ static void initializeAttributes(TargetService& i_targetService) // Check mbox scratch reg 3 for IPL boot options // Specifically istep mode (bit 0) and MPIPL (bit 2) - uint64_t l_data = + INITSERVICE::SPLESS::MboxScratch3_t l_scratch3; + l_scratch3.data32 = Util::readScratchReg(INITSERVICE::SPLESS::MBOX_SCRATCH_REG3); // Targeting data defaults to non istep, only turn "on" if bit // is set so we don't tromp default setting - if ((l_data & Util::ISTEP_CONFIG_BIT) == Util::ISTEP_CONFIG_BIT) + if (l_scratch3.istepMode) { l_pTopLevel->setAttr<ATTR_ISTEP_MODE>(1); } - if ((l_data & Util::MPIPL_CONFIG_BIT) == Util::MPIPL_CONFIG_BIT) + if (l_scratch3.isMpipl) { l_isMpipl = true; } diff --git a/src/usr/util/utilmbox_scratch.C b/src/usr/util/utilmbox_scratch.C index 9a38b8dff..814a9026a 100644 --- a/src/usr/util/utilmbox_scratch.C +++ b/src/usr/util/utilmbox_scratch.C @@ -54,14 +54,14 @@ namespace Util mutex_t g_mutex = MUTEX_INITIALIZER; - uint64_t readScratchReg(uint64_t i_addr) + uint32_t readScratchReg(uint64_t i_addr) { size_t l_size = sizeof(uint64_t); - uint64_t value = 0; + uint64_t l_value = 0; errlHndl_t l_errl = deviceRead(TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL, - &value, l_size, + &l_value, l_size, DEVICE_SCOM_ADDRESS(i_addr)); if (l_errl) @@ -69,12 +69,14 @@ namespace Util errlCommit(l_errl, UTIL_COMP_ID); } - return value; + return static_cast<uint32_t>(l_value >> 32); } - void writeScratchReg(uint64_t i_addr, uint64_t i_data) + void writeScratchReg(uint64_t i_addr, uint32_t i_data) { size_t l_size = sizeof(uint64_t); + uint64_t l_value = static_cast<uint64_t>(i_data); + l_value <<= 32; //data is in top half of scom reg errlHndl_t l_errl = deviceWrite(TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL, @@ -94,9 +96,6 @@ namespace Util uint64_t l_bufSize = (i_size & MSG_DATA_SIZE_MASK) | (i_usage << MSG_USAGE_SHIFT); - l_bufAddr <<=32; - l_bufSize <<=32; - //Lock to prevent concurrent access mutex_lock(&g_mutex); |