diff options
Diffstat (limited to 'src/usr')
33 files changed, 8807 insertions, 118 deletions
diff --git a/src/usr/hwas/hwas.C b/src/usr/hwas/hwas.C index ffc971503..acf7b9ded 100644 --- a/src/usr/hwas/hwas.C +++ b/src/usr/hwas/hwas.C @@ -40,7 +40,10 @@ #include <initservice/taskargs.H> #include <errl/errlentry.H> #include <targeting/targetservice.H> +#include <targeting/iterators/rangefilter.H> +#include <targeting/predicates/predicatectm.H> #include <fsi/fsiif.H> + #include <hwas/hwas.H> #include <hwas/deconfigGard.H> #include <targeting/util.H> @@ -57,33 +60,113 @@ void init_target_states( void *io_pArgs ) { INITSERVICE::TaskArgs *pTaskArgs = static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + TARGETING::HwasState l_hwasState; TRACDCOMP( g_trac_hwas, "init_target_states entry: set default HWAS state:" ); // loop through all the targets and set HWAS_STATE to a known default - TARGETING::TargetIterator l_pTarget = TARGETING::targetService().begin(); + TARGETING::TargetIterator l_TargetItr = TARGETING::targetService().begin(); for( ; - l_pTarget != TARGETING::targetService().end(); - ++l_pTarget - ) + l_TargetItr != TARGETING::targetService().end(); + ++l_TargetItr + ) { - // HWAS_STATE attribute definition in the attribute_types.xml file - // gets translated into TARGETING::HwasState . - // fetch it from targeting - this is not strictly necessary (right now) - // but makes debug easier later. - TARGETING::HwasState l_hwasState = - l_pTarget->getAttr<ATTR_HWAS_STATE>(); - + l_hwasState = l_TargetItr->getAttr<ATTR_HWAS_STATE>(); l_hwasState.poweredOn = false; l_hwasState.present = false; l_hwasState.functional = false; l_hwasState.changedSinceLastIPL = false; l_hwasState.gardLevel = 0; + l_TargetItr->setAttr<ATTR_HWAS_STATE>( l_hwasState ); + } - // Now write the modified value back to Targeting. - l_pTarget->setAttr<ATTR_HWAS_STATE>( l_hwasState ); + + + /** + * @todo Enable cpu 0 and centaur 0 for now. + */ + // $$$$$ TEMPORARY $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ + // get the master processor, this should be CPU 0 + TARGETING::Target* l_pMasterProcChipTargetHandle = NULL; + (void)TARGETING::targetService().masterProcChipTargetHandle( + l_pMasterProcChipTargetHandle); + if (l_pMasterProcChipTargetHandle == NULL) + { + TRACFCOMP( g_trac_hwas, "FAILED to get master processor target"); } + else + { + // set master chip to poweredOn, present, functional + l_hwasState = l_pMasterProcChipTargetHandle->getAttr<ATTR_HWAS_STATE>(); + l_hwasState.poweredOn = true; + l_hwasState.present = true; + l_hwasState.functional = true; + l_hwasState.changedSinceLastIPL = false; + l_hwasState.gardLevel = 0; + l_pMasterProcChipTargetHandle->setAttr<ATTR_HWAS_STATE>( l_hwasState ); + + // get the mcs "chiplets" associated with this cpu + TARGETING::PredicateCTM l_mcsChipFilter(CLASS_UNIT, TYPE_MCS); + TARGETING::TargetHandleList l_mcsTargetList; + TARGETING::targetService().getAssociated( + l_mcsTargetList, + l_pMasterProcChipTargetHandle, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::IMMEDIATE, + &l_mcsChipFilter ); + // debug... + TRACDCOMP( g_trac_hwas, + "%d MCSs for master processor", + l_mcsTargetList.size() ); + + for ( uint8_t i=0; i < l_mcsTargetList.size(); i++ ) + { + // set each MCS to poweredON, present, functional + l_hwasState = l_mcsTargetList[i]->getAttr<ATTR_HWAS_STATE>(); + l_hwasState.poweredOn = true; + l_hwasState.present = true; + l_hwasState.functional = true; + l_hwasState.changedSinceLastIPL = false; + l_hwasState.gardLevel = 0; + l_mcsTargetList[i]->setAttr<ATTR_HWAS_STATE>( l_hwasState ); + + + // If ATTR_CHIP_UNIT==0 or 1, find the centaur underneath it + // and set it to good as well. + if ( ( l_mcsTargetList[i]->getAttr<ATTR_CHIP_UNIT>() == 0 ) + || ( l_mcsTargetList[i]->getAttr<ATTR_CHIP_UNIT>() == 1 ) + ) + { + TARGETING::PredicateCTM l_membufChips(CLASS_CHIP, TYPE_MEMBUF); + TARGETING::TargetHandleList l_memTargetList; + TARGETING::targetService().getAssociated(l_memTargetList, + l_mcsTargetList[i], + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_membufChips); + // debug... + TRACDCOMP( g_trac_hwas, + "%d MEMBUFSs associated with MCS %d", + l_memTargetList.size(), + l_mcsTargetList[i]->getAttr<ATTR_CHIP_UNIT>() ); + + for ( uint8_t ii=0; ii < l_memTargetList.size(); ii++ ) + { + // set the Centaur(s) connected to MCS0 to poweredOn, + // present, functional + l_hwasState = l_memTargetList[ii]->getAttr<ATTR_HWAS_STATE>(); + l_hwasState.poweredOn = true; + l_hwasState.present = true; + l_hwasState.functional = true; + l_hwasState.changedSinceLastIPL = false; + l_hwasState.gardLevel = 0; + l_memTargetList[ii]->setAttr<ATTR_HWAS_STATE>( l_hwasState ); + } // end for + } // end if + } // end for + } // end else + // $$$$$ TEMPORARY $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ // wait here on the barrier, then end the task. pTaskArgs->waitChildSync(); diff --git a/src/usr/hwas/test/hwas1test.H b/src/usr/hwas/test/hwas1test.H index 4cc83e2f1..97a1051b7 100644 --- a/src/usr/hwas/test/hwas1test.H +++ b/src/usr/hwas/test/hwas1test.H @@ -58,77 +58,6 @@ class HWAS1test: public CxxTest::TestSuite { public: - /** - * @brief Walk some ofthe targets and verify that HWAS_STATE is set - * correctly. - * - * @note Results of this test will change as more stuff gets added to - * HWAS - how to fix? - */ - void testHWASdefaultPresence() - { - TS_TRACE( "testHWASdefaultPresence entry" ); - - using namespace TARGETING; - - TargetService& l_targetService = targetService(); - l_targetService.init(); - - - // get top level - // Post init - // Test: void getTopLevelTarget(Target*& o_targetHandle) const; - - Target* l_pTopLevel = NULL; - (void) l_targetService.getTopLevelTarget(l_pTopLevel); - if (l_pTopLevel == NULL) - { - TS_FAIL("Top level handle was NULL when initialization complete"); - } - - // Post init - // Test: void getAssociated( - // const Target* i_pTarget, - // ASSOCIATION_TYPE i_type, - // RECURSION_LEVEL i_recursionLevel, - // TargetHandleList& o_list) const; - - TargetHandleList l_list; - (void) l_targetService.getAssociated( - l_list, - l_pTopLevel, - TARGETING::TargetService::CHILD, - TARGETING::TargetService::ALL); - - TS_TRACE("Child list size is 0x%x", l_list.size() ); - for (uint64_t i=0; i<l_list.size(); i++ ) - { - // 2011-10-19 all attribute fields should be 0 at this point. - if ( ( l_list[i]->getAttr<ATTR_HWAS_STATE>().poweredOn) - || ( l_list[i]->getAttr<ATTR_HWAS_STATE>().present) - || ( l_list[i]->getAttr<ATTR_HWAS_STATE>().functional) - || ( l_list[i]->getAttr<ATTR_HWAS_STATE>().changedSinceLastIPL) - || ( l_list[i]->getAttr<ATTR_HWAS_STATE>().gardLevel) - ) - { - l_list[i]->getAttr<ATTR_PHYS_PATH>().dump(); - TS_TRACE( " poweredOn = 0x%x", - l_list[i]->getAttr<ATTR_HWAS_STATE>().poweredOn ); - TS_TRACE( " present = 0x%x", - l_list[i]->getAttr<ATTR_HWAS_STATE>().present ); - TS_TRACE( " l_functional = 0x%x", - l_list[i]->getAttr<ATTR_HWAS_STATE>().functional ); - TS_TRACE( " l_changedSinceLastIPL = 0x%x", - l_list[i]->getAttr<ATTR_HWAS_STATE>().changedSinceLastIPL ); - TS_TRACE( " l_gardLevel = 0x%x", - l_list[i]->getAttr<ATTR_HWAS_STATE>().gardLevel ); - - TS_FAIL( "Attribute fields not correct: "); - } - } - - TS_TRACE( "testHWASdefaultPresence exit" ); - } /** * @brief Write to all the attributes and then read them back. diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/edi_regs.h b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/edi_regs.h new file mode 100644 index 000000000..4238d2c0f --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/edi_regs.h @@ -0,0 +1,2301 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_io_run_training/edi_regs.h $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +//----------------------------------------------------- +// ____ ____ _ ______ ______ +// / __ \/ __ \ / | / / __ \/_ __/ +// / / / / / / / / |/ / / / / / / +// / /_/ / /_/ / / /| / /_/ / / / +// /_____/\____/ /_/ |_/\____/ /_/ +// +// __________ __________ +// / ____/ __ \/ _/_ __/ +// / __/ / / / // / / / +// / /___/ /_/ // / / / +// /_____/_____/___/ /_/ +// +// ________ ___________ ____________ ________ +// /_ __/ / / / _/ ___/ / ____/ _/ / / ____/ / +// / / / /_/ // / \__ \ / /_ / // / / __/ / / +// / / / __ // / ___/ / / __/ _/ // /___/ /___/_/ +// /_/ /_/ /_/___//____/ /_/ /___/_____/_____(_) +//----------------------------------------------------- +// Constant file for edi_reg_attribute.txt_fixed +// File generated at 16:23 on 8/31/2011 using system_pervasive/common/tools/CreateConstantsH.pl +// $Id: edi_regs.h,v 1.5 2012/01/20 12:32:47 varkeykv Exp $ +// $URL: $ +// +// *!************************************************************************** +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!*************************************************************************** +// *! FILENAME : /afs/apd.pok.ibm.com/func/vlsi/eclipz/c22/verif/p8dd1/system_pervasive/common/include/edi_regs.h +// +// *! PERL SCRIPT OWNER NAME : Jim Goldade Email: goldade@us.ibm.com +// *! edi_reg_attribute.txt_fixed +//----------------------------------------------------------------------------------------------------------------------------- +// EDI Register Def +//----------------------------------------------------------------------------------------------------------------------------- +#ifndef _edi_regs_h +#define _edi_regs_h +//FROM EDI_REGS + +typedef enum { + tx_mode_pl, + tx_cntl_stat_pl, + tx_spare_mode_pl, + tx_bist_stat_pl, + tx_prbs_mode_pl, + tx_data_cntl_gcrmsg_pl, + tx_sync_pattern_gcrmsg_pl, + tx_fir_pl, + tx_fir_mask_pl, + tx_fir_error_inject_pl, + tx_mode_fast_pl, + tx_clk_mode_pg, + tx_spare_mode_pg, + tx_cntl_stat_pg, + tx_mode_pg, + tx_bus_repair_pg, + tx_grp_repair_vec_0_15_pg, + tx_grp_repair_vec_16_31_pg, + tx_reset_act_pg, + tx_bist_stat_pg, + tx_fir_pg, + tx_fir_mask_pg, + tx_fir_error_inject_pg, + tx_id1_pg, + tx_id2_pg, + tx_id3_pg, + tx_minikerf_pg, + tx_clk_cntl_gcrmsg_pg, + tx_ffe_mode_pg, + tx_ffe_main_pg, + tx_ffe_post_pg, + tx_ffe_margin_pg, + tx_bad_lane_enc_gcrmsg_pg, + tx_sls_lane_enc_gcrmsg_pg, + tx_lane_disabled_vec_0_15_pg, + tx_lane_disabled_vec_16_31_pg, + tx_sls_lane_mux_gcrmsg_pg, + tx_dyn_rpr_pg, + tx_slv_mv_sls_ln_req_gcrmsg_pg, + tx_wiretest_pp, + tx_mode_pp, + tx_sls_gcrmsg_pp, + tx_ber_cntl_a_pp, + tx_ber_cntl_b_pp, + tx_dyn_recal_timeouts_pp, + tx_bist_cntl_pp, + tx_ber_cntl_sls_pp, + tx_cntl_pp, + tx_reset_cfg_pp, + tx_impcal_pb, + tx_impcal_nval_pb, + tx_impcal_pval_pb, + tx_impcal_p_4x_pb, + tx_impcal_swo1_pb, + tx_impcal_swo2_pb, + rx_mode_pl, + rx_cntl_pl, + rx_spare_mode_pl, + rx_prot_edge_status_pl, + rx_bist_stat_pl, + rx_eyeopt_mode_pl, + rx_eyeopt_stat_pl, + rx_offset_even_pl, + rx_offset_odd_pl, + rx_amp_val_pl, + rx_amp_cntl_pl, + rx_prot_status_pl, + rx_prot_mode_pl, + rx_prot_cntl_pl, + rx_fifo_stat_pl, + rx_ap_pl, + rx_an_pl, + rx_amin_pl, + rx_h1_even_pl, + rx_h1_odd_pl, + rx_prbs_mode_pl, + rx_stat_pl, + rx_deskew_stat_pl, + rx_fir_pl, + rx_fir_mask_pl, + rx_fir_error_inject_pl, + rx_sls_pl, + rx_wt_status_pl, + rx_fifo_cntl_pl, + rx_ber_status_pl, + rx_ber_timer_0_15_pl, + rx_ber_timer_16_31_pl, + rx_ber_timer_32_39_pl, + rx_servo_cntl_pl, + rx_fifo_diag_0_15_pl, + rx_fifo_diag_16_31_pl, + rx_fifo_diag_32_47_pl, + rx_eye_width_status_pl, + rx_eye_width_cntl_pl, + rx_dfe_clkadj_pl, + rx_clk_mode_pg, + rx_spare_mode_pg, + rx_mode_pg, + rx_bus_repair_pg, + rx_grp_repair_vec_0_15_pg, + rx_grp_repair_vec_16_31_pg, + rx_recal_mode_pg, + rx_reset_act_pg, + rx_id1_pg, + rx_id2_pg, + rx_id3_pg, + rx_minikerf_pg, + rx_bist_cntl_pg, + rx_sls_mode_pg, + rx_training_start_pg, + rx_training_status_pg, + rx_recal_status_pg, + rx_timeout_sel_pg, + rx_fifo_mode_pg, + rx_state_debug_pg, + rx_state_val_pg, + rx_sls_status_pg, + rx_fir1_pg, + rx_fir2_pg, + rx_fir1_mask_pg, + rx_fir2_mask_pg, + rx_fir1_error_inject_pg, + rx_fir2_error_inject_pg, + rx_fir_training_pg, + rx_fir_training_mask_pg, + rx_timeout_sel1_pg, + rx_lane_bad_vec_0_15_pg, + rx_lane_bad_vec_16_31_pg, + rx_lane_disabled_vec_0_15_pg, + rx_lane_disabled_vec_16_31_pg, + rx_lane_swapped_vec_0_15_pg, + rx_lane_swapped_vec_16_31_pg, + rx_init_state_pg, + rx_wiretest_state_pg, + rx_wiretest_laneinfo_pg, + rx_wiretest_gcrmsgs_pg, + rx_deskew_gcrmsgs_pg, + rx_deskew_state_pg, + rx_deskew_mode_pg, + rx_deskew_status_pg, + rx_bad_lane_enc_gcrmsg_pg, + rx_static_repair_state_pg, + rx_tx_bus_info_pg, + rx_sls_lane_enc_gcrmsg_pg, + rx_fence_pg, + rx_timeout_sel2_pg, + rx_misc_analog_pg, + rx_dyn_rpr_pg, + rx_dyn_rpr_gcrmsg_pg, + rx_dyn_rpr_err_tallying_pg, + rx_eo_final_l2u_gcrmsgs_pg, + rx_gcr_msg_debug_dest_ids_pg, + rx_gcr_msg_debug_src_ids_pg, + rx_gcr_msg_debug_dest_addr_pg, + rx_gcr_msg_debug_write_data_pg, + rx_dyn_recal_pg, + rx_wt_clk_status_pg, + rx_dyn_recal_config_pg, + rx_servo_recal_gcrmsg_pg, + rx_dyn_recal_gcrmsg_pg, + rx_wiretest_pll_cntl_pg, + rx_eo_step_cntl_pg, + rx_eo_step_stat_pg, + rx_eo_step_fail_pg, + rx_ap_pg, + rx_an_pg, + rx_amin_pg, + rx_amax_pg, + rx_amp_val_pg, + rx_amp_offset_pg, + rx_eo_convergence_pg, + rx_sls_rcvy_pg, + rx_sls_rcvy_gcrmsg_pg, + rx_tx_lane_info_gcrmsg_pg, + rx_err_tallying_gcrmsg_pg, + rx_trace_pg, + rx_wiretest_pp, + rx_mode_pp, + rx_cntl_pp, + rx_dyn_recal_timeouts_pp, + rx_servo_recal_gcrmsg_pp, + rx_ber_cntl_pp, + rx_ber_mode_pp, + rx_servo_to1_pp, + rx_servo_to2_pp, + rx_servo_to3_pp, + rx_dfe_config_pp, + rx_dfe_timers_pp, + rx_reset_cfg_pp, + rx_fir_msg_pb, +NUM_REGS +} GCR_sub_registers; + +// ext_addr is 9 bits +const uint32_t GCR_sub_reg_ext_addr[] = { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x195, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x000, 0x001, 0x002, 0x003, 0x005, 0x006, 0x007, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x100, 0x101, 0x103, 0x104, 0x105, 0x106, 0x107, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10E, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x115, 0x116, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x144, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x1FE, 0x108 }; + +const char* const GCR_sub_reg_names[] = { + "TX Lane Mode Reg", + "TX Cntl and Status Reg", + "TX Per-Lane Spare Mode Reg", + "TX BIST Status Reg", + "TX Per-Lane PRBS Mode Reg", + "TX Data Control Reg", + "TX Sync Pattern Control Reg", + "TX Per-Lane FIR Error Source-Isolation Reg", + "TX Per-Lane FIR Error Mask Reg", + "TX Per-Lane FIR Error Injection Reg", + "TX Per-Lane Fast-Clocked Mode Reg", + "TX Per-Group Clk Mode Reg", + "TX Per-Group Spare Mode Reg", + "TX Cntl and Status Reg", + "TX Mode Reg", + "TX Bus Repair Reg", + "TX Clkgrp Repair Lanes 0-15 Reg", + "TX Clkgrp Repair Lanes 16-31 Reg", + "TX Reset Control Action Register (RCAR)", + "TX BIST CLK Status Reg", + "TX Per-Group FIR Error Source-Isolation Reg", + "TX Per-Group FIR Error Source-Isolation Reg", + "TX Per-Group FIR Error Injection Reg", + "TX Clock Group Identification 1 Reg", + "TX Clock Group Identification 2 Reg", + "TX Clock Group Identification 3 Reg", + "TX Minikerf Cntl Reg", + "TX Clock Control Reg", + "TX FFE Test Mode Reg", + "TX FFE Main Reg", + "TX FFE Post Reg", + "TX FFE Margin Reg", + "TX Bad Lanes Encoded", + "TX SLS Lane Encoded", + "TX Lane Disable(d) 0 to 15 Reg", + "TX Lane Disable(d) 16 to 31 Reg", + "TX SLS Lane TX Mux Setting", + "TX Dynamic Repair & Recalibration Status", + "TX Dynamic Repair & Recalibration Messages", + "TX Wiretest Per-Group & Pack Shadow Reg", + "TX Mode Per-Pack Shadow Reg", + "TX SLS Command", + "TX Bit Error Injection Control A Shadow Reg", + "TX Bit Error Injection Control B Shadow Reg", + "TX Dynamic Recalibration Timeout Selects", + "TX BIST Cntl Reg", + "TX Bit Error Injection Control SLS Shadow Reg", + "TX Cntl Per-Pack Reg", + "TX Configurable Reset Control Register (CRCR)", + "TX Impedance Cal Cntl and Status Reg", + "TX Impedance Cal N Value Reg", + "TX Impedance Cal P Value Reg", + "TX Impedance Cal P 4x Value Reg", + "TX Impedance Cal SW Workaround 1 Reg", + "TX Impedance Cal SW Workaround 2 Reg", + "RX Lane Mode Reg", + "RX Cntl and Status Reg", + "RX Per-lane Spare Mode Reg", + "RX Phase Rotator Edge Status Reg", + "RX BIST Status Reg", + "RX Eye Optimization Mode Reg", + "RX Eye Optimization Status Reg", + "RX Even Sample Latch Offset Cntl Reg", + "RX Odd Sample Latch Offset Cntl Reg", + "RX Preamp value Reg", + "RX Preamp value Reg", + "RX Phase Rotator Status Reg", + "RX Phase Rotator Mode Reg", + "RX Phase Rotator Control Reg", + "RX FIFO Status Reg", + "RX Ap Even/Odd Sampler Reg", + "RX An Even/Odd Sampler Reg", + "RX Amin Reg", + "RX H1 Even Sampler Reg", + "RX H1 Odd Sampler Reg", + "RX Per-Lane PRBS Mode Reg", + "RX Per-Lane Deskew Status Reg", + "RX FIFO deskew status/error register", + "RX Per-Lane FIR Error Source-Isolation Reg", + "RX Per-Lane FIR Error Source-Isolation Mask Reg", + "RX Per-Lane FIR Error Injection Reg", + "RX SLS Settings Register", + "RX Wiretest Status register ", + "RX FIFO control Reg", + "RX BER Status Reg", + "RX BER Current Timer Value Reg - Bits 0 to 15", + "RX BER Current Timer Value Reg - Bits 16 to 31", + "RX BER Current Timer Value Reg - Bits 32 to 39", + "RX Servo Operation command and control", + "RX FIFO output 0 to 15 for diag", + "RX FIFO output 16 to 31 for diag", + "RX FIFO output 32 to 47 for diag", + "RX Current and historic minimum eye width", + "RX historic minimum eye width reset control", + "RX dfe clock adjust register", + "RX Per-Group Clk Mode Reg", + "RX Per-Group Spare Mode Reg", + "RX Mode Reg", + "RX Bus Repair Reg", + "RX Clkgrp Repair Lanes 0-15 Reg", + "RX Clkgrp Repair Lanes 16-31 Reg", + "RX Bus Repair Reg", + "RX Reset Control Action Register (RCAR)", + "RX Clock Group Identification 1 Reg", + "RX Clock Group Identification 2 Reg", + "RX Clock Group Identification 3 Reg", + "RX Minikerf Cntl Reg", + "RX BIST Cntl Reg", + "RX Spare Lane Signaling Mode Reg", + "RX Training State Start Reg", + "RX Training State Status Reg", + "RX Recal Status Reg", + "RX Timeout Select Reg", + "RX FIFO Mode Reg", + "RX State Machine Debug Cntl/Status Reg", + "RX State Machine Debug Value Reg", + "RX Spare Lane Signalling Status Reg", + "RX Per-Group FIR Error Source-Isolation Reg", + "RX Per-Group FIR Error Source-Isolation Reg", + "RX Per-Group FIR Error Source-Isolation Mask Reg", + "RX Per-Group FIR Error Source-Isolation Mask Reg", + "RX Per-Group FIR Error Injection Reg", + "RX Per-Group FIR Error Injection Reg", + "RX Per-Group Training FIR Error Reg", + "RX Per-Group Training FIR Error Mask Reg", + "RX Timeout Select Reg 1", + "RX Bad Lanes 0 to 15 Reg", + "RX Bad Lanes 16 to 31 Reg", + "RX Lane Disable(d) 0 to 15 Reg", + "RX Lane Disable(d) 16_31 Reg", + "RX P & N Lanes Swapped 0 to 15 Reg", + "RX P & N Lanes Swapped 16 to 31 Reg", + "RX Init Machine Status", + "RX Wiretest State Machine Reg", + "RX Wiretest Lane Info Reg", + "RX Wiretest GCR Message Reg", + "RX Deskew GCR Message Reg", + "RX Deskew State Machine Status Reg", + "RX Deskew State Machine Control Reg", + "RX Deskew State Machine Status Values", + "RX Bad Lanes Encoded", + "RX Static Repair State Machine Reg", + "TX Bus info for RX Ctl Macs", + "RX SLS Lane Encoded", + "RX Per Group Fence", + "RX Timeout Select Reg 2", + "RX Misc Analog Reg", + "RX Dynamic Repair & Recalibration Status", + "CRC/ECC Dynamic Repair GCR Message Reg", + "CRC/ECC Dynamic Repair Error Frequency Settings", + "RX Final Load to Unload GCR Messages", + "RX SW Initiated GCR Message Destination IDs", + "RX SW Initiated GCR Message Source IDs", + "RX SW Initiated GCR Message Destination Addr", + "RX SW Initiated GCR Message Write Data", + "RX Dynamic Recalibration Status", + "RX Clock Wiretest Status", + "RX Dynamic Recalibration Configuration", + "RX Servo Dynamic Recalibration GCR Messages", + "RX Dynamic Recalibration GCR Messages", + "RX Cleanup PLL Enable ", + "RX Eye optimization step control", + "RX Eye optimization step status", + "RX Eye optimization step fail flags", + "RX Eye optimization Ap working registers", + "RX Eye optimization An working registers", + "RX Eye optimization Amin working registers", + "RX Eye optimization Amax limit registers", + "RX Eye optimization Amp working registers", + "RX Eye optimization Amp Offset limts ", + "RX Eye optimization Convergence control regs", + "RX SLS Handshake Recovery Register", + "RX SLS Handshake Recovery GCR Messages", + "RX: TX Lane Info", + "CRC/ECC Syndrome Tallying GCR Message Reg", + "RX Trace Mode Reg", + "RX Wiretest Per-Pack Shadow Reg", + "RX Mode Per-Pack Shadow Reg", + "RX Cntl Per-Pack Shadow Reg", + "RX Dynamic Recalibration Timeout Selects", + "RX Servo Dynamic Recalibration GCR Messages", + "RX BER Control Reg", + "RX BER Mode Reg", + "RX Servo Timeout Select Regs 1", + "RX Servo Timeout Select Regs 2", + "RX Servo Timeout Select Regs 3", + "RX DFE Configuration Register", + "RX DFE timers Configuration Register", + "RX Configurable Reset Control Register (CRCR)" +}; + + + +// tx_mode_pl Register field name data value Description +#define tx_lane_pdwn 0x8000 //Used to drive inhibit (tristate) and fully power down a lane. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers tx_lane_disabled_vec_0_15 and tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines. +#define tx_lane_pdwn_clear 0x7FFF // Clear mask +#define tx_lane_invert 0x4000 //Used to invert the polarity of a lane. +#define tx_lane_invert_clear 0xBFFF // Clear mask +#define tx_lane_quiesce_p_quiesce_to_0 0x1000 //Used to force the output of the positive differential leg of a lane to a particular value. Quiesce Lane to a Static 0 value +#define tx_lane_quiesce_p_quiesce_to_1 0x2000 //Used to force the output of the positive differential leg of a lane to a particular value. Quiesce Lane to a Static 1 value +#define tx_lane_quiesce_p_quiesce_to_z 0x3000 //Used to force the output of the positive differential leg of a lane to a particular value. Tri-State Lane Output +#define tx_lane_quiesce_p_clear 0xCFFF // Clear mask +#define tx_lane_quiesce_n_quiesce_to_0 0x0400 //Used to force the output of the negative differential leg of a lane to a particular value. Quiesce Lane to a Static 0 value +#define tx_lane_quiesce_n_quiesce_to_1 0x0800 //Used to force the output of the negative differential leg of a lane to a particular value. Quiesce Lane to a Static 1 value +#define tx_lane_quiesce_n_quiesce_to_z 0x0C00 //Used to force the output of the negative differential leg of a lane to a particular value. Tri-State Lane Output +#define tx_lane_quiesce_n_clear 0xF3FF // Clear mask +#define tx_lane_scramble_disable 0x0200 //Used to disable the TX scrambler on a specific lane or all lanes by using a per-lane/per-group global write. +#define tx_lane_scramble_disable_clear 0xFDFF // Clear mask +#define tx_lane_error_inject_mode_single_err_inj 0x0001 //Used to set the error injection rate to a particular value. Single Error Injection +#define tx_lane_error_inject_mode_0 0x0002 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_1 0x0003 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_2 0x0010 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_3 0x0011 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_4 0x0012 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_5 0x0013 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_6 0x0020 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_7 0x0021 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_8 0x0022 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_9 0x0023 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_10 0x0030 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_11 0x0031 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_12 0x0032 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_13 0x0033 //Used to set the error injection rate to a particular value. TBD +#define tx_lane_error_inject_mode_clear 0xF300 // Clear mask + +// tx_cntl_stat_pl Register field name data value Description +#define tx_fifo_err 0x8000 //Indicates an error condition in the TX FIFO. +#define tx_fifo_err_clear 0x7FFF // Clear mask + +// tx_spare_mode_pl Register field name data value Description +#define tx_pl_spare_mode_0 0x8000 //Per-lane spare mode latch +#define tx_pl_spare_mode_0_clear 0x7FFF // Clear mask +#define tx_pl_spare_mode_1 0x4000 //Per-lane spare mode latch +#define tx_pl_spare_mode_1_clear 0xBFFF // Clear mask +#define tx_pl_spare_mode_2 0x2000 //Per-lane spare mode latch +#define tx_pl_spare_mode_2_clear 0xDFFF // Clear mask +#define tx_pl_spare_mode_3 0x1000 //Per-lane spare mode latch +#define tx_pl_spare_mode_3_clear 0xEFFF // Clear mask +#define tx_pl_spare_mode_4 0x0800 //Per-lane spare mode latch +#define tx_pl_spare_mode_4_clear 0xF7FF // Clear mask +#define tx_pl_spare_mode_5 0x0400 //Per-lane spare mode latch +#define tx_pl_spare_mode_5_clear 0xFBFF // Clear mask +#define tx_pl_spare_mode_6 0x0200 //Per-lane spare mode latch +#define tx_pl_spare_mode_6_clear 0xFDFF // Clear mask +#define tx_pl_spare_mode_7 0x0100 //Per-lane spare mode latch +#define tx_pl_spare_mode_7_clear 0xFEFF // Clear mask + +// tx_bist_stat_pl Register field name data value Description +#define tx_lane_bist_err 0x8000 //Indicates a TXBIST error occurred. +#define tx_lane_bist_err_clear 0x7FFF // Clear mask +#define tx_lane_bist_done 0x4000 //Indicates TXBIST has completed. +#define tx_lane_bist_done_clear 0xBFFF // Clear mask + +// tx_prbs_mode_pl Register field name data value Description +#define tx_prbs_tap_id_pattern_b 0x2000 //TX Per-Lane PRBS Tap Selector PRBS tap point B +#define tx_prbs_tap_id_pattern_c 0x4000 //TX Per-Lane PRBS Tap Selector PRBS tap point C +#define tx_prbs_tap_id_pattern_d 0x6000 //TX Per-Lane PRBS Tap Selector PRBS tap point D +#define tx_prbs_tap_id_pattern_e 0x8000 //TX Per-Lane PRBS Tap Selector PRBS tap point E +#define tx_prbs_tap_id_pattern_F 0xA000 //TX Per-Lane PRBS Tap Selector PRBS tap point F +#define tx_prbs_tap_id_pattern_g 0xC000 //TX Per-Lane PRBS Tap Selector PRBS tap point G +#define tx_prbs_tap_id_pattern_h 0xE000 //TX Per-Lane PRBS Tap Selector PRBS tap point H +#define tx_prbs_tap_id_clear 0x1FFF // Clear mask + +// tx_data_cntl_gcrmsg_pl Register field name data value Description +#define tx_drv_data_pattern_gcrmsg_drv_wt 0x1000 //GCR Message: TX Per Data Lane Drive Patterns Drive Wiretest Pattern +#define tx_drv_data_pattern_gcrmsg_drv_1s 0x2000 //GCR Message: TX Per Data Lane Drive Patterns Drive All 1s Pattern +#define tx_drv_data_pattern_gcrmsg_drv_simple_A 0x3000 //GCR Message: TX Per Data Lane Drive Patterns Drive Simple Pattern A +#define tx_drv_data_pattern_gcrmsg_drv_simple_B 0x4000 //GCR Message: TX Per Data Lane Drive Patterns Drive Simple Pattern B +#define tx_drv_data_pattern_gcrmsg_drv_full_prbs23 0x5000 //GCR Message: TX Per Data Lane Drive Patterns PRBS-23 Full Speed Scramble Pattern A thru H +#define tx_drv_data_pattern_gcrmsg_drv_red_prbs23 0x6000 //GCR Message: TX Per Data Lane Drive Patterns PRBS-23 Reduced Density Scramble Pattern A thru H +#define tx_drv_data_pattern_gcrmsg_drv_9th_prbs23 0x7000 //GCR Message: TX Per Data Lane Drive Patterns PRBS-23 9th pattern +#define tx_drv_data_pattern_gcrmsg_drv_ei3_iap 0x8000 //GCR Message: TX Per Data Lane Drive Patterns EI-3 Busy IAP Pattern (EI4 only +#define tx_drv_data_pattern_gcrmsg_drv_ei3_prbs12 0x9000 //GCR Message: TX Per Data Lane Drive Patterns Drive EI-3 PRBS-12 Shifted RDT Pattern (EI4 only +#define tx_drv_data_pattern_gcrmsg_unused_A 0xA000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_B 0xB000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_C 0xC000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_D 0xD000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_E 0xE000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_F 0xF000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_clear 0x0FFF // Clear mask +#define tx_drv_func_data_gcrmsg 0x0800 //GCR Message: Functional Data +#define tx_drv_func_data_gcrmsg_clear 0xF7FF // Clear mask +#define tx_sls_lane_sel_gcrmsg 0x0400 //GCR Message: SLS Commands & Recalibration +#define tx_sls_lane_sel_gcrmsg_clear 0xFBFF // Clear mask + +// tx_sync_pattern_gcrmsg_pl Register field name data value Description +#define tx_sync_pattern_gcrmsg_pl_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED +#define tx_sync_pattern_gcrmsg_pl_spare_clear 0x7FFF // Clear mask +#define tx_drv_sync_patt_gcrmsg 0x4000 //Sync Pattern +#define tx_drv_sync_patt_gcrmsg_clear 0xBFFF // Clear mask + +// tx_fir_pl Register field name data value Description +#define tx_pl_fir_errs 0x8000 //A 1 in this field indicates that a register or state machine parity error has occurred in per-lane logic. +#define tx_pl_fir_errs_clear 0x7FFF // Clear mask + +// tx_fir_mask_pl Register field name data value Description +#define tx_pl_fir_errs_mask 0x8000 //FIR mask for all per-lane register or per-lane state machine parity errors. +#define tx_pl_fir_errs_mask_clear 0x7FFF // Clear mask + +// tx_fir_error_inject_pl Register field name data value Description +#define tx_pl_fir_err_inj 0x8000 //TX Per-Lane Parity Error Injection +#define tx_pl_fir_err_inj_clear 0x7FFF // Clear mask + +// tx_mode_fast_pl Register field name data value Description +#define tx_err_inject_lane0 0x8000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 0. +#define tx_err_inject_lane1 0x4000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 1. +#define tx_err_inject_lane2 0x2000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) inject error on lane 2. +#define tx_err_inject_lane3 0x1000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 3. +#define tx_err_inject_clear 0x0FFF // Clear mask +#define tx_err_inj_A_enable 0x0800 //Control to enable the random bit error injection A.(default) +#define tx_err_inj_A_enable_clear 0xF7FF // Clear mask +#define tx_err_inj_B_enable 0x0400 //Control to enable the random bit error injection B.(default) +#define tx_err_inj_B_enable_clear 0xFBFF // Clear mask + +// tx_clk_mode_pg Register field name data value Description +#define tx_clk_pdwn 0x8000 //Used to disable the TX clock and put it into a low power state. +#define tx_clk_pdwn_clear 0x7FFF // Clear mask +#define tx_clk_invert 0x4000 //Used to invert the polarity of the clock. +#define tx_clk_invert_clear 0xBFFF // Clear mask +#define tx_clk_quiesce_p_quiesce_to_0 0x1000 //Used to force the output of the positive differential leg of the clock lane to a particular value. Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality. Quiesce Clock Lane to a Static 0 value +#define tx_clk_quiesce_p_quiesce_to_1 0x2000 //Used to force the output of the positive differential leg of the clock lane to a particular value. Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality. Quiesce Clock Lane to a Static 1 value +#define tx_clk_quiesce_p_quiesce_to_z 0x3000 //Used to force the output of the positive differential leg of the clock lane to a particular value. Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality. Tri-State Clock Lane Output +#define tx_clk_quiesce_p_clear 0xCFFF // Clear mask +#define tx_clk_quiesce_n_quiesce_to_0 0x0400 //Used to force the output of the negative differential leg of the clock lane to a particular value. Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality. Quiesce Clock Lane to a Static 0 value +#define tx_clk_quiesce_n_quiesce_to_1 0x0800 //Used to force the output of the negative differential leg of the clock lane to a particular value. Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality. Quiesce Clock Lane to a Static 1 value +#define tx_clk_quiesce_n_quiesce_to_z 0x0C00 //Used to force the output of the negative differential leg of the clock lane to a particular value. Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality. Tri-State Clock Lane Output +#define tx_clk_quiesce_n_clear 0xF3FF // Clear mask +#define tx_clk_ddr_mode 0x0200 //Used to select TX clock QDR mode or DDR mode. +#define tx_clk_ddr_mode_clear 0xFDFF // Clear mask + +// tx_spare_mode_pg Register field name data value Description +#define tx_pg_spare_mode_0 0x8000 //Per-group spare mode latch +#define tx_pg_spare_mode_0_clear 0x7FFF // Clear mask +#define tx_pg_spare_mode_1 0x4000 //Per-group spare mode latch +#define tx_pg_spare_mode_1_clear 0xBFFF // Clear mask +#define tx_pg_spare_mode_2 0x2000 //Per-group spare mode latch +#define tx_pg_spare_mode_2_clear 0xDFFF // Clear mask +#define tx_pg_spare_mode_3 0x1000 //Per-group spare mode latch +#define tx_pg_spare_mode_3_clear 0xEFFF // Clear mask +#define tx_pg_spare_mode_4 0x0800 //Per-group spare mode latch +#define tx_pg_spare_mode_4_clear 0xF7FF // Clear mask +#define tx_pg_spare_mode_5 0x0400 //Per-group spare mode latch +#define tx_pg_spare_mode_5_clear 0xFBFF // Clear mask +#define tx_pg_spare_mode_6 0x0200 //Per-group spare mode latch +#define tx_pg_spare_mode_6_clear 0xFDFF // Clear mask +#define tx_pg_spare_mode_7 0x0100 //Per-group spare mode latch +#define tx_pg_spare_mode_7_clear 0xFEFF // Clear mask + +// tx_cntl_stat_pg Register field name data value Description +#define tx_cntl_stat_pg_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED +#define tx_cntl_stat_pg_spare_clear 0x7FFF // Clear mask +#define tx_fifo_init 0x4000 //Used to initialize the TX FIFO and put it into a known reset state. This will cause the load to unload delay of the FIFO to be set to the value in the TX_FIFO_L2U_DLY field of the TX_FIFO_Mode register. +#define tx_fifo_init_clear 0xBFFF // Clear mask + +// tx_mode_pg Register field name data value Description +#define tx_max_bad_lanes 0x0000 //Static Repair, Dynamic Repair & Recal max number of bad lanes per TX bus +#define tx_max_bad_lanes_clear 0x07FF // Clear mask +#define tx_msbswap 0x0400 //Used to enable end-for-end or msb swap of TX lanes. For example, lanes 0 and N-1 swap, lanes 1 and N-2 swap, etc. +#define tx_msbswap_clear 0xFBFF // Clear mask + +// tx_bus_repair_pg Register field name data value Description +#define tx_bus_repair_count 0x0000 //This field is used to TBD. +#define tx_bus_repair_count_clear 0x3FFF // Clear mask +#define tx_bus_repair_pos_0 0x0000 //This field is used to TBD. +#define tx_bus_repair_pos_0_clear 0xC07F // Clear mask +#define tx_bus_repair_pos_1 0x0000 //This field is used to TBD. +#define tx_bus_repair_pos_1_clear 0x3F80 // Clear mask + +// tx_grp_repair_vec_0_15_pg Register field name data value Description +#define tx_grp_repair_vec_0_15 0x0000 //This field is used to TBD. +#define tx_grp_repair_vec_0_15_clear 0x0000 // Clear mask + +// tx_grp_repair_vec_16_31_pg Register field name data value Description +#define tx_grp_repair_vec_16_31 0x0000 //This field is used to TBD. +#define tx_grp_repair_vec_16_31_clear 0x0000 // Clear mask + +// tx_reset_act_pg Register field name data value Description +#define tx_reset_cfg_ena 0x8000 //Enable Configurable Group Reset +#define tx_reset_cfg_ena_clear 0x7FFF // Clear mask +#define tx_clr_par_errs 0x0002 //Clear All TX Parity Error Latches +#define tx_clr_par_errs_clear 0xFFFD // Clear mask +#define tx_fir_reset 0x0001 //FIR Reset +#define tx_fir_reset_clear 0xFFFE // Clear mask + +// tx_bist_stat_pg Register field name data value Description +#define tx_clk_bist_err 0x8000 //Indicates a TXBIST error occurred. +#define tx_clk_bist_err_clear 0x7FFF // Clear mask +#define tx_clk_bist_done 0x4000 //Indicates TXBIST has completed. +#define tx_clk_bist_done_clear 0xBFFF // Clear mask + +// tx_fir_pg Register field name data value Description +#define tx_pg_fir_errs_clear 0x00FF // Clear mask +#define tx_pl_fir_err 0x0001 //Summary bit indicating a TX per-lane register or state machine parity error has occurred in one or more lanes. The tx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane. +#define tx_pl_fir_err_clear 0xFFFE // Clear mask + +// tx_fir_mask_pg Register field name data value Description +#define tx_pg_fir_errs_mask_clear 0x00FF // Clear mask +#define tx_pl_fir_err_mask 0x0001 //FIR mask for the summary bit that indicates a per-lane TX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane TX parity errors from causing a FIR error.\pmt +#define tx_pl_fir_err_mask_clear 0xFFFE // Clear mask + +// tx_fir_error_inject_pg Register field name data value Description +#define tx_pg_fir_err_inj_inj_par_err 0x1000 //TX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define tx_pg_fir_err_inj_clear 0x00FF // Clear mask + +// tx_id1_pg Register field name data value Description +#define tx_bus_id 0x0000 //This field is used to programmably set the bus number that a clkgrp belongs to. +#define tx_bus_id_clear 0x03FF // Clear mask +#define tx_group_id 0x0000 //This field is used to programmably set the clock group number within a bus. +#define tx_group_id_clear 0xFE07 // Clear mask + +// tx_id2_pg Register field name data value Description +#define tx_last_group_id 0x0000 //This field is used to programmably set the last clock group number within a bus. +#define tx_last_group_id_clear 0x03FF // Clear mask + +// tx_id3_pg Register field name data value Description +#define tx_start_lane_id 0x0000 //This field is used to programmably set the first lane position in the group but relative to the bus. +#define tx_start_lane_id_clear 0x80FF // Clear mask +#define tx_end_lane_id 0x0000 //This field is used to programmably set the last lane position in the group but relative to the bus. +#define tx_end_lane_id_clear 0x7F80 // Clear mask + +// tx_minikerf_pg Register field name data value Description +#define tx_minikerf 0x0000 //Used to configure the TX Minikerf for analog characterization. +#define tx_minikerf_clear 0x0000 // Clear mask + +// tx_clk_cntl_gcrmsg_pg Register field name data value Description +#define tx_drv_clk_pattern_gcrmsg_drv_wt 0x4000 //TX Clock Drive Patterns Drive Wiretest Pattern +#define tx_drv_clk_pattern_gcrmsg_drv_c4 0x8000 //TX Clock Drive Patterns Drive Clock Pattern +#define tx_drv_clk_pattern_gcrmsg_unused 0xC000 //TX Clock Drive Patterns Unused +#define tx_drv_clk_pattern_gcrmsg_clear 0x3FFF // Clear mask + +// tx_ffe_mode_pg Register field name data value Description +#define tx_ffe_test_mode_seg_test 0x1000 //Driver Segment Test mode Driver Output Test Mode +#define tx_ffe_test_mode_unused1 0x2000 //Driver Segment Test mode Reserved +#define tx_ffe_test_mode_unused2 0x3000 //Driver Segment Test mode Reserved +#define tx_ffe_test_mode_clear 0xCFFF // Clear mask +#define tx_ffe_test_override1r 0x0200 //Driver Segment Test 1R Override +#define tx_ffe_test_override1r_clear 0xFDFF // Clear mask +#define tx_ffe_test_override2r 0x0100 //Driver Segment Test 2R Override +#define tx_ffe_test_override2r_clear 0xFEFF // Clear mask + +// tx_ffe_main_pg Register field name data value Description +#define tx_ffe_main_p_enc 0x0000 //TBD +#define tx_ffe_main_p_enc_clear 0xC0FF // Clear mask +#define tx_ffe_main_n_enc 0x0000 //TBD +#define tx_ffe_main_n_enc_clear 0x3FC0 // Clear mask + +// tx_ffe_post_pg Register field name data value Description +#define tx_ffe_post_p_enc 0x0000 //TBD +#define tx_ffe_post_p_enc_clear 0x00FF // Clear mask +#define tx_ffe_post_n_enc 0x0000 //TBD +#define tx_ffe_post_n_enc_clear 0x0FF0 // Clear mask + +// tx_ffe_margin_pg Register field name data value Description +#define tx_ffe_margin_p_enc 0x0000 //TBD +#define tx_ffe_margin_p_enc_clear 0x00FF // Clear mask +#define tx_ffe_margin_n_enc 0x0000 //TBD +#define tx_ffe_margin_n_enc_clear 0x0FF0 // Clear mask + +// tx_bad_lane_enc_gcrmsg_pg Register field name data value Description +#define tx_bad_lane1_gcrmsg 0x0000 //GCR Message: Encoded bad lane one in relation to the entire TX bus +#define tx_bad_lane1_gcrmsg_clear 0x01FF // Clear mask +#define tx_bad_lane2_gcrmsg 0x0000 //GCR Message: Encoded bad lane two in relation to the entire TX bus +#define tx_bad_lane2_gcrmsg_clear 0xFE03 // Clear mask +#define tx_bad_lane_code_gcrmsg_bad_ln1_val 0x0001 //GCR Message: TX Bad Lane Code Bad Lane 1 Valid +#define tx_bad_lane_code_gcrmsg_bad_lns12_val 0x0002 //GCR Message: TX Bad Lane Code Bad Lanes 1 and 2 Valid +#define tx_bad_lane_code_gcrmsg_3plus_bad_lns 0x0003 //GCR Message: TX Bad Lane Code 3+ bad lanes +#define tx_bad_lane_code_gcrmsg_clear 0xFFF0 // Clear mask + +// tx_sls_lane_enc_gcrmsg_pg Register field name data value Description +#define tx_sls_lane_gcrmsg 0x0000 //GCR Message: Encoded SLS lane in relation to the entire TX bus +#define tx_sls_lane_gcrmsg_clear 0x01FF // Clear mask +#define tx_sls_lane_val_gcrmsg 0x0100 //GCR Message: TX SLS Lane Valid +#define tx_sls_lane_val_gcrmsg_clear 0xFEFF // Clear mask + +// tx_lane_disabled_vec_0_15_pg Register field name data value Description +#define tx_lane_disabled_vec_0_15 0x0000 //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control). +#define tx_lane_disabled_vec_0_15_clear 0x0000 // Clear mask + +// tx_lane_disabled_vec_16_31_pg Register field name data value Description +#define tx_lane_disabled_vec_16_31 0x0000 //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control). +#define tx_lane_disabled_vec_16_31_clear 0x0000 // Clear mask + +// tx_sls_lane_mux_gcrmsg_pg Register field name data value Description +#define tx_sls_lane_shdw_gcrmsg 0x8000 //GCR Message: SLS lane shadowing or unshadowing functional data (used to set up TX mux controls) +#define tx_sls_lane_shdw_gcrmsg_clear 0x7FFF // Clear mask + +// tx_dyn_rpr_pg Register field name data value Description +#define tx_sls_hndshk_state_clear 0x07FF // Clear mask + +// tx_slv_mv_sls_ln_req_gcrmsg_pg Register field name data value Description +#define tx_slv_mv_sls_shdw_req_gcrmsg 0x8000 //GCR Message: Request to TX Slave to Move SLS Lane +#define tx_slv_mv_sls_shdw_req_gcrmsg_clear 0x7FFF // Clear mask +#define tx_slv_mv_sls_shdw_rpr_req_gcrmsg 0x4000 //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register +#define tx_slv_mv_sls_shdw_rpr_req_gcrmsg_clear 0xBFFF // Clear mask +#define tx_slv_mv_sls_unshdw_req_gcrmsg 0x2000 //GCR Message: Request to TX Slave to Move SLS Lane +#define tx_slv_mv_sls_unshdw_req_gcrmsg_clear 0xDFFF // Clear mask +#define tx_slv_mv_sls_unshdw_rpr_req_gcrmsg 0x1000 //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register +#define tx_slv_mv_sls_unshdw_rpr_req_gcrmsg_clear 0xEFFF // Clear mask +#define tx_bus_width 0x0000 //TX Bus Width +#define tx_bus_width_clear 0xF01F // Clear mask +#define tx_slv_mv_sls_rpr_req_gcrmsg 0x0010 //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register +#define tx_slv_mv_sls_rpr_req_gcrmsg_clear 0xFFEF // Clear mask + +// tx_wiretest_pp Register field name data value Description +#define tx_wt_pattern_length_256 0x4000 //TX Wiretest Pattern Length 256 +#define tx_wt_pattern_length_512 0x8000 //TX Wiretest Pattern Length 512 +#define tx_wt_pattern_length_1024 0xC000 //TX Wiretest Pattern Length 1024 +#define tx_wt_pattern_length_clear 0x3FFF // Clear mask + +// tx_mode_pp Register field name data value Description +#define tx_reduced_scramble_mode_full_1 0x4000 //Enables/Disables and sets reduced density of scramble pattern. Full density +#define tx_reduced_scramble_mode_div2 0x8000 //Enables/Disables and sets reduced density of scramble pattern. Enable Div2 Reduced Density +#define tx_reduced_scramble_mode_div4 0xC000 //Enables/Disables and sets reduced density of scramble pattern. Enable Div4 Reduced Density. +#define tx_reduced_scramble_mode_clear 0x3FFF // Clear mask +#define tx_fifo_l2u_dly_4_to_6_ui 0x0800 //This field is used to read or set the TX FIFO load to unload delay according to the following. 4 to 6 UI (default +#define tx_fifo_l2u_dly_8_to_10_ui 0x1000 //This field is used to read or set the TX FIFO load to unload delay according to the following. 8 to 10 UI +#define tx_fifo_l2u_dly_12_to_14_ui 0x1800 //This field is used to read or set the TX FIFO load to unload delay according to the following. 12 to 14 UI +#define tx_fifo_l2u_dly_16_to_18_ui 0x2000 //This field is used to read or set the TX FIFO load to unload delay according to the following. 16 to 18 UI +#define tx_fifo_l2u_dly_20_to_22_ui 0x2800 //This field is used to read or set the TX FIFO load to unload delay according to the following. 20 to 22 UI +#define tx_fifo_l2u_dly_24_to_26_ui 0x3000 //This field is used to read or set the TX FIFO load to unload delay according to the following. 24 to 26 UI +#define tx_fifo_l2u_dly_28_to_30_ui 0x3800 //This field is used to read or set the TX FIFO load to unload delay according to the following. 28 to 30 UI +#define tx_fifo_l2u_dly_clear 0xC7FF // Clear mask + +// tx_sls_gcrmsg_pp Register field name data value Description +#define tx_snd_sls_cmd_gcrmsg 0x8000 //GCR Message: Send SLS Command or Recalibration Data +#define tx_snd_sls_cmd_gcrmsg_clear 0x7FFF // Clear mask +#define tx_dyn_recal_tsr_ignore_gcrmsg 0x4000 //GCR Message: Send Dynamic Recal SLS Commands all the time (not just during the Status Reporting interval) +#define tx_dyn_recal_tsr_ignore_gcrmsg_clear 0xBFFF // Clear mask +#define tx_sls_cmd_gcrmsg 0x0000 //GCR Message: TX SLS Command +#define tx_sls_cmd_gcrmsg_clear 0xC0FF // Clear mask + +// tx_ber_cntl_a_pp Register field name data value Description +#define tx_err_inj_a_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data. +#define tx_err_inj_a_rand_beat_dis_clear 0x7FFF // Clear mask +#define tx_err_inj_a_fine_sel_0_15 0x1000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-15 +#define tx_err_inj_a_fine_sel_0_7 0x2000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-7 +#define tx_err_inj_a_fine_sel_0_3 0x3000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-3 +#define tx_err_inj_a_fine_sel_0_1 0x4000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-1 +#define tx_err_inj_a_fine_sel_fixed1 0x5000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 1 +#define tx_err_inj_a_fine_sel_fixed3 0x6000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 3 +#define tx_err_inj_a_fine_sel_fixed7 0x7000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 7. +#define tx_err_inj_a_fine_sel_clear 0x8FFF // Clear mask +#define tx_err_inj_a_coarse_sel_8_23 0x0100 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 8-32, mean of 16 +#define tx_err_inj_a_coarse_sel_12_19 0x0200 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 12-19, mean of 16 +#define tx_err_inj_a_coarse_sel_14_17 0x0300 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 14-17, mean of 16 +#define tx_err_inj_a_coarse_sel_min 0x0400 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Min range of 15-16, mean of 16 +#define tx_err_inj_a_coarse_sel_fixed16 0x0500 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 16 +#define tx_err_inj_a_coarse_sel_fixed24 0x0600 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 24 +#define tx_err_inj_a_coarse_sel_fixed20 0x0700 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 20. +#define tx_err_inj_a_coarse_sel_clear 0xF8FF // Clear mask +#define tx_err_inj_a_ber_sel 0x0000 //Used to set the random bit error injection rate to a particular value. See workbook for details. +#define tx_err_inj_a_ber_sel_clear 0x3FC0 // Clear mask + +// tx_ber_cntl_b_pp Register field name data value Description +#define tx_err_inj_b_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data.(default) +#define tx_err_inj_b_rand_beat_dis_clear 0x7FFF // Clear mask +#define tx_err_inj_b_fine_sel_0_15 0x1000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-15 +#define tx_err_inj_b_fine_sel_0_7 0x2000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-7 +#define tx_err_inj_b_fine_sel_0_3 0x3000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-3 +#define tx_err_inj_b_fine_sel_0_1 0x4000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-1 +#define tx_err_inj_b_fine_sel_fixed1 0x5000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 1 +#define tx_err_inj_b_fine_sel_fixed3 0x6000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 3 +#define tx_err_inj_b_fine_sel_fixed7 0x7000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 7. +#define tx_err_inj_b_fine_sel_clear 0x8FFF // Clear mask +#define tx_err_inj_b_coarse_sel_8_23 0x0100 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 8-32, mean of 16 +#define tx_err_inj_b_coarse_sel_12_19 0x0200 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 12-19, mean of 16 +#define tx_err_inj_b_coarse_sel_14_17 0x0300 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 14-17, mean of 16 +#define tx_err_inj_b_coarse_sel_min 0x0400 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Min range of 15-16, mean of 16 +#define tx_err_inj_b_coarse_sel_fixed16 0x0500 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 16 +#define tx_err_inj_b_coarse_sel_fixed24 0x0600 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 24 +#define tx_err_inj_b_coarse_sel_fixed20 0x0700 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 20. +#define tx_err_inj_b_coarse_sel_clear 0xF8FF // Clear mask +#define tx_err_inj_b_ber_sel 0x0000 //Used to set the random bit error injection rate to a particular value. See workbook for details. +#define tx_err_inj_b_ber_sel_clear 0x3FC0 // Clear mask + +// tx_dyn_recal_timeouts_pp Register field name data value Description +#define tx_dyn_recal_interval_timeout_sel_tap1 0x1000 //TX Dynamic Recalibration Interval Timeout Selects 16kUI or 1.7us +#define tx_dyn_recal_interval_timeout_sel_tap2 0x2000 //TX Dynamic Recalibration Interval Timeout Selects 32kUI or 3.4us +#define tx_dyn_recal_interval_timeout_sel_tap3 0x3000 //TX Dynamic Recalibration Interval Timeout Selects 64kUI or 6.8us +#define tx_dyn_recal_interval_timeout_sel_tap4 0x4000 //TX Dynamic Recalibration Interval Timeout Selects 128kUI or 106.5ns +#define tx_dyn_recal_interval_timeout_sel_tap5 0x5000 //TX Dynamic Recalibration Interval Timeout Selects 256kUI or 1.7us +#define tx_dyn_recal_interval_timeout_sel_tap6 0x6000 //TX Dynamic Recalibration Interval Timeout Selects 8192kUI or 872.4us +#define tx_dyn_recal_interval_timeout_sel_tap7 0x7000 //TX Dynamic Recalibration Interval Timeout Selects infinite +#define tx_dyn_recal_interval_timeout_sel_clear 0x8FFF // Clear mask +#define tx_dyn_recal_status_rpt_timeout_sel_tap1 0x0400 //TX Dynamic Recalibration Status Reporting Timeout Selects 1024UI or 106.5ns +#define tx_dyn_recal_status_rpt_timeout_sel_tap2 0x0800 //TX Dynamic Recalibration Status Reporting Timeout Selects 2048UI or 212.9ns +#define tx_dyn_recal_status_rpt_timeout_sel_tap3 0x0C00 //TX Dynamic Recalibration Status Reporting Timeout Selects 4096UI or 426.0ns +#define tx_dyn_recal_status_rpt_timeout_sel_clear 0xF3FF // Clear mask + +// tx_bist_cntl_pp Register field name data value Description +#define tx_bist_en 0x8000 //TBD +#define tx_bist_en_clear 0x7FFF // Clear mask +#define tx_bist_clr 0x4000 //TBD +#define tx_bist_clr_clear 0xBFFF // Clear mask +#define tx_bist_prbs7_en 0x2000 //TBD +#define tx_bist_prbs7_en_clear 0xDFFF // Clear mask + +// tx_ber_cntl_sls_pp Register field name data value Description +#define tx_err_inj_sls_mode 0x8000 //Used to set the random bit error injection during SLS. See workbook for details. +#define tx_err_inj_sls_mode_clear 0x7FFF // Clear mask +#define tx_err_inj_sls_all_cmd 0x4000 //Used to qualify the SLS mode error injection, to inject on all command values. See workbook for details. +#define tx_err_inj_sls_all_cmd_clear 0xBFFF // Clear mask +#define tx_err_inj_sls_cmd 0x0000 //Used to qualify the SLS mode error injection, to only inject on this set command value. See workbook for details. +#define tx_err_inj_sls_cmd_clear 0xFFC0 // Clear mask + +// tx_cntl_pp Register field name data value Description +#define tx_enable_reduced_scramble 0x8000 //Enables reduced density of scramble pattern. +#define tx_enable_reduced_scramble_clear 0x7FFF // Clear mask + +// tx_reset_cfg_pp Register field name data value Description +#define tx_reset_cfg_hld_clear 0x0000 // Clear mask + +// tx_impcal_pb Register field name data value Description +#define tx_zcal_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED. +#define tx_zcal_spare_clear 0x7FFF // Clear mask +#define tx_zcal_req 0x4000 //\bImpedance Calibration Sequence Enable\b +#define tx_zcal_req_clear 0xBFFF // Clear mask +#define tx_zcal_done 0x2000 //\bImpedance Calibration Sequence Complete\b +#define tx_zcal_done_clear 0xDFFF // Clear mask +#define tx_zcal_error 0x1000 //\bImpedance Calibration Sequence Error\b +#define tx_zcal_error_clear 0xEFFF // Clear mask +#define tx_zcal_busy 0x0800 //\bImpedance Calibration Sequence Busy\b +#define tx_zcal_busy_clear 0xF7FF // Clear mask +#define tx_zcal_force_sample 0x0400 //\bImpedance Comparison Sample Force\b +#define tx_zcal_force_sample_clear 0xFBFF // Clear mask +#define tx_zcal_cmp_out 0x0200 //\bCalibration Circuit Unqualified Sample\b +#define tx_zcal_cmp_out_clear 0xFDFF // Clear mask +#define tx_zcal_sample_cnt_clear 0xFE00 // Clear mask + +// tx_impcal_nval_pb Register field name data value Description +#define tx_zcal_n 0x0000 //\bCalibration Circuit NSeg Enable Value\b May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices). +#define tx_zcal_n_clear 0x007F // Clear mask + +// tx_impcal_pval_pb Register field name data value Description +#define tx_zcal_p 0x0000 //\bCalibration Circuit PSeg Enable Value\b May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices). +#define tx_zcal_p_clear 0x007F // Clear mask + +// tx_impcal_p_4x_pb Register field name data value Description +#define tx_zcal_p_4x 0x0000 //\bCalibration Circuit PSeg-4X Enable Value\b May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0x15 is maximum slices). +#define tx_zcal_p_4x_clear 0x07FF // Clear mask + +// tx_impcal_swo1_pb Register field name data value Description +#define tx_zcal_swo_en 0x8000 //\bImpedance Calibration Software Override\b +#define tx_zcal_swo_en_clear 0x7FFF // Clear mask +#define tx_zcal_swo_cal_segs 0x4000 //\bImpedance Calibration Software Bank Select\b +#define tx_zcal_swo_cal_segs_clear 0xBFFF // Clear mask +#define tx_zcal_swo_cmp_inv 0x2000 //\bImpedance Calibration Software Compare Invert\b +#define tx_zcal_swo_cmp_inv_clear 0xDFFF // Clear mask +#define tx_zcal_swo_cmp_offset 0x1000 //\bImpedance Calibration Software Offset Flush\b +#define tx_zcal_swo_cmp_offset_clear 0xEFFF // Clear mask +#define tx_zcal_swo_cmp_reset 0x0800 //\bImpedance Calibration Software Comparator reset\b +#define tx_zcal_swo_cmp_reset_clear 0xF7FF // Clear mask +#define tx_zcal_swo_powerdown 0x0400 //\bImpedance Calibration Software Circuit Powerdown\b +#define tx_zcal_swo_powerdown_clear 0xFBFF // Clear mask +#define tx_zcal_cya_data_inv 0x0200 //\bImpedance Calibration CYA Sample Inversion\b +#define tx_zcal_cya_data_inv_clear 0xFDFF // Clear mask +#define tx_zcal_test_ovr_2r 0x0100 //\bImpedance Calibration Test-Only 2R segment override\b +#define tx_zcal_test_ovr_2r_clear 0xFEFF // Clear mask + +// tx_impcal_swo2_pb Register field name data value Description +#define tx_zcal_sm_min_val 0x0000 //\bImpedance Calibration Minimum Search Threshold\b Low-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices). +#define tx_zcal_sm_min_val_clear 0x01FF // Clear mask +#define tx_zcal_sm_max_val 0x0000 //\bImpedance Calibration Maximum Search Threshold\b High-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices). +#define tx_zcal_sm_max_val_clear 0xFE03 // Clear mask + +// rx_mode_pl Register field name data value Description +#define rx_lane_pdwn 0x8000 //Used to receive inhibit and fully power down a lane. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers rx_lane_disabled_vec_0_15 and rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines. +#define rx_lane_pdwn_clear 0x7FFF // Clear mask +#define rx_lane_scramble_disable 0x0200 //Used to disable the RX descrambler on a specific lane or all lanes by using a per-lane/per-group global write. +#define rx_lane_scramble_disable_clear 0xFDFF // Clear mask + +// rx_cntl_pl Register field name data value Description +#define rx_block_lock_lane 0x8000 //Enables rotation and checking for block lock. +#define rx_block_lock_lane_clear 0x7FFF // Clear mask +#define rx_check_skew_lane 0x4000 //Per-Lane Initialization controls checks skew requst +#define rx_check_skew_lane_clear 0xBFFF // Clear mask +#define rx_cntl_pl_tbd 0x0000 //TBD +#define rx_cntl_pl_tbd_clear 0xC07F // Clear mask + +// rx_spare_mode_pl Register field name data value Description +#define rx_pl_spare_mode_0 0x8000 //Per-lane spare mode latch +#define rx_pl_spare_mode_0_clear 0x7FFF // Clear mask +#define rx_pl_spare_mode_1 0x4000 //Per-lane spare mode latch +#define rx_pl_spare_mode_1_clear 0xBFFF // Clear mask +#define rx_pl_spare_mode_2 0x2000 //Per-lane spare mode latch +#define rx_pl_spare_mode_2_clear 0xDFFF // Clear mask +#define rx_pl_spare_mode_3 0x1000 //Per-lane spare mode latch +#define rx_pl_spare_mode_3_clear 0xEFFF // Clear mask +#define rx_pl_spare_mode_4 0x0800 //Per-lane spare mode latch +#define rx_pl_spare_mode_4_clear 0xF7FF // Clear mask +#define rx_pl_spare_mode_5 0x0400 //Per-lane spare mode latch +#define rx_pl_spare_mode_5_clear 0xFBFF // Clear mask +#define rx_pl_spare_mode_6 0x0200 //Per-lane spare mode latch +#define rx_pl_spare_mode_6_clear 0xFDFF // Clear mask +#define rx_pl_spare_mode_7 0x0100 //Per-lane spare mode latch +#define rx_pl_spare_mode_7_clear 0xFEFF // Clear mask + +// rx_prot_edge_status_pl Register field name data value Description +#define rx_phaserot_left_edge 0x0000 //RX Phase Rotator left edge. +#define rx_phaserot_left_edge_clear 0xC0FF // Clear mask +#define rx_phaserot_right_edge 0x0000 //RX Phase Rotator right edge. +#define rx_phaserot_right_edge_clear 0xFF03 // Clear mask + +// rx_bist_stat_pl Register field name data value Description +#define rx_bist_err 0x8000 //Indicates a RXBIST error occurred. +#define rx_bist_err_clear 0x7FFF // Clear mask +#define rx_bist_done 0x4000 //Indicates a RXBIST has completed. +#define rx_bist_done_clear 0xBFFF // Clear mask + +// rx_eyeopt_mode_pl Register field name data value Description +#define rx_ddc_disable 0x8000 //When set to a 1 this causes the phase detector to stop running which results in the phase rotator value to stop updating. This mode is used for diagnostics and characterization. +#define rx_ddc_disable_clear 0x7FFF // Clear mask + +// rx_eyeopt_stat_pl Register field name data value Description +#define rx_eyeopt_stat_tbd 0x8000 //Eye optimization status. TBD +#define rx_eyeopt_stat_tbd_clear 0x7FFF // Clear mask + +// rx_offset_even_pl Register field name data value Description +#define rx_offset_even_samp1 0x0000 //This is the vertical offset of the even sampling latch. +#define rx_offset_even_samp1_clear 0xC0FF // Clear mask +#define rx_offset_even_samp0 0x0000 //This is the vertical offset of the even sampling latch. +#define rx_offset_even_samp0_clear 0x3FC0 // Clear mask + +// rx_offset_odd_pl Register field name data value Description +#define rx_offset_odd_samp1 0x0000 //This is the vertical offset of the odd sampling latch. +#define rx_offset_odd_samp1_clear 0x00FF // Clear mask +#define rx_offset_odd_samp0 0x0000 //This is the vertical offset of the odd sampling latch. +#define rx_offset_odd_samp0_clear 0x3FC0 // Clear mask + +// rx_amp_val_pl Register field name data value Description +#define rx_amp_peak 0x0000 //This is the vertical offset of the pre-amp. +#define rx_amp_peak_clear 0x0FFF // Clear mask +#define rx_amp_gain 0x0000 //This is the gain setting of the pre-amp. +#define rx_amp_gain_clear 0xF0FF // Clear mask +#define rx_amp_offset 0x0000 //This is the peaking setting of the pre-amp. +#define rx_amp_offset_clear 0x3FC0 // Clear mask + +// rx_amp_cntl_pl Register field name data value Description +#define rx_amp_adj_done 0x8000 //VGA adjust is complete for this lane. +#define rx_amp_adj_done_clear 0x7FFF // Clear mask +#define rx_amp_adj_all_done_b 0x4000 //VGA adjust is complete for this lane--qualified and asserted low for dot-OR reading. +#define rx_amp_adj_all_done_b_clear 0xBFFF // Clear mask + +// rx_prot_status_pl Register field name data value Description +#define rx_phaserot_val 0x0000 //RX Phase Rotator current value. +#define rx_phaserot_val_clear 0xC0FF // Clear mask +#define rx_phaserot_ddc_complete 0x0080 //RX DDC State Machine completion indicator. +#define rx_phaserot_ddc_complete_clear 0xFF7F // Clear mask +#define rx_phaserot_block_lock_err 0x0040 //RX DDC State Machine block lock error indicator. +#define rx_phaserot_block_lock_err_clear 0xFFBF // Clear mask + +// rx_prot_mode_pl Register field name data value Description +#define rx_phaserot_offset 0x0000 //RX Phase Rotator fixed offset from learned value. +#define rx_phaserot_offset_clear 0xC0FF // Clear mask + +// rx_prot_cntl_pl Register field name data value Description +#define rx_bump_left_half_ui 0x8000 //Per-Lane Bump left 1/2 UI control (Self-Clearing) +#define rx_bump_left_half_ui_clear 0x7FFF // Clear mask +#define rx_bump_right_half_ui 0x4000 //Per-Lane Bump right 1/2 UI control (Self-Clearing) +#define rx_bump_right_half_ui_clear 0xBFFF // Clear mask +#define rx_bump_one_ui 0x2000 //Per-Lane Bump 1 UI control (Self-Clearing) +#define rx_bump_one_ui_clear 0xDFFF // Clear mask +#define rx_bump_two_ui 0x1000 //Per-Lane Bump 2 UI control (Self-Clearing) +#define rx_bump_two_ui_clear 0xEFFF // Clear mask +#define rx_ext_sr 0x0800 //RX Manual Phase Rotator Shift Right Pulse +#define rx_ext_sr_clear 0xF7FF // Clear mask +#define rx_ext_sl 0x0400 //RX Manual Phase Rotator Shift Left Pulse +#define rx_ext_sl_clear 0xFBFF // Clear mask + +// rx_fifo_stat_pl Register field name data value Description +#define rx_fifo_l2u_dly 0x0000 //RX FIFO load-to-unload delay, initailed during FIFO init and modified thereafter by the deskew machine. For setting X, the latency is 4*X to 4*X+4 UI. Default is 16-20 UI. +#define rx_fifo_l2u_dly_clear 0x0FFF // Clear mask +#define rx_fifo_init 0x0800 //Initializes the fifo unload counter with the load counter and initializes the fifo load to unload delay +#define rx_fifo_init_clear 0xF7FF // Clear mask + +// rx_ap_pl Register field name data value Description +#define rx_ap_even_samp 0x0000 //TBD +#define rx_ap_even_samp_clear 0x00FF // Clear mask +#define rx_ap_odd_samp 0x0000 //TBD +#define rx_ap_odd_samp_clear 0xFF00 // Clear mask + +// rx_an_pl Register field name data value Description +#define rx_an_even_samp 0x0000 //TBD +#define rx_an_even_samp_clear 0x00FF // Clear mask +#define rx_an_odd_samp 0x0000 //TBD +#define rx_an_odd_samp_clear 0xFF00 // Clear mask + +// rx_amin_pl Register field name data value Description +#define rx_amin_even 0x0000 //TBD +#define rx_amin_even_clear 0x00FF // Clear mask +#define rx_amin_odd 0x0000 //TBD +#define rx_amin_odd_clear 0xFF00 // Clear mask + +// rx_h1_even_pl Register field name data value Description +#define rx_h1_even_samp1 0x0000 //TBD +#define rx_h1_even_samp1_clear 0x00FF // Clear mask +#define rx_h1_even_samp0 0x0000 //TBD +#define rx_h1_even_samp0_clear 0x7F80 // Clear mask + +// rx_h1_odd_pl Register field name data value Description +#define rx_h1_odd_samp1 0x0000 //TBD +#define rx_h1_odd_samp1_clear 0x00FF // Clear mask +#define rx_h1_odd_samp0 0x0000 //TBD +#define rx_h1_odd_samp0_clear 0x7F80 // Clear mask + +// rx_prbs_mode_pl Register field name data value Description +#define rx_prbs_tap_id_pattern_b 0x2000 //Per-Lane PRBS Tap Selector PRBS tap point B +#define rx_prbs_tap_id_pattern_c 0x4000 //Per-Lane PRBS Tap Selector PRBS tap point C +#define rx_prbs_tap_id_pattern_d 0x6000 //Per-Lane PRBS Tap Selector PRBS tap point D +#define rx_prbs_tap_id_pattern_e 0x8000 //Per-Lane PRBS Tap Selector PRBS tap point E +#define rx_prbs_tap_id_pattern_F 0xA000 //Per-Lane PRBS Tap Selector PRBS tap point F +#define rx_prbs_tap_id_pattern_g 0xC000 //Per-Lane PRBS Tap Selector PRBS tap point G +#define rx_prbs_tap_id_pattern_h 0xE000 //Per-Lane PRBS Tap Selector PRBS tap point H +#define rx_prbs_tap_id_clear 0x1FFF // Clear mask + +// rx_stat_pl Register field name data value Description +#define rx_some_block_locked 0x8000 //Per-Lane Block Lock Indicator +#define rx_some_block_locked_clear 0x7FFF // Clear mask +#define rx_all_block_locked_b 0x4000 //Per-Lane Block Lock Indicator +#define rx_all_block_locked_b_clear 0xBFFF // Clear mask +#define rx_some_skew_valid 0x2000 //Per-Lane Deskew Pattern B Detect Indicator +#define rx_some_skew_valid_clear 0xDFFF // Clear mask +#define rx_all_skew_valid_b 0x1000 //Per-Lane Deskew Pattern B Detect Indicato (Active Low)r +#define rx_all_skew_valid_b_clear 0xEFFF // Clear mask +#define rx_some_prbs_synced 0x0800 //Per-Lane PRBS Synchronization Indicator +#define rx_some_prbs_synced_clear 0xF7FF // Clear mask +#define rx_prbs_synced_b 0x0400 //Per-Lane PRBS Synchronization Indicator (Active Low) +#define rx_prbs_synced_b_clear 0xFBFF // Clear mask +#define rx_skew_value 0x0000 //Per-Lane PRBS Synchronization Count +#define rx_skew_value_clear 0xFC0F // Clear mask + +// rx_deskew_stat_pl Register field name data value Description +#define rx_bad_block_lock 0x8000 //Deskew Step block lock not established--lane marked bad +#define rx_bad_block_lock_clear 0x7FFF // Clear mask +#define rx_bad_skew 0x4000 //Deskew Step skew value not detected--lane marked bad +#define rx_bad_skew_clear 0xBFFF // Clear mask +#define rx_bad_deskew 0x2000 //Deskew Step deskew value +#define rx_bad_deskew_clear 0xDFFF // Clear mask + +// rx_fir_pl Register field name data value Description +#define rx_pl_fir_errs_clear 0x3FFF // Clear mask + +// rx_fir_mask_pl Register field name data value Description +#define rx_pl_fir_errs_mask 0x0000 //A 1 in this field indicates that a register or state machine parity error has occurred in per-group logic. +#define rx_pl_fir_errs_mask_clear 0x3FFF // Clear mask + +// rx_fir_error_inject_pl Register field name data value Description +#define rx_pl_fir_err_inj_inj_par_err 0x4000 //RX Per-Lane Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pl_fir_err_inj_clear 0x3FFF // Clear mask + +// rx_sls_pl Register field name data value Description +#define rx_sls_lane_sel 0x8000 //Selects which lane to receive SLS Commands and Recalibration Data on +#define rx_sls_lane_sel_clear 0x7FFF // Clear mask +#define rx_9th_pattern_en 0x4000 //Sets RX Descrabmler to use 9th Scramble Pattern +#define rx_9th_pattern_en_clear 0xBFFF // Clear mask + +// rx_wt_status_pl Register field name data value Description +#define rx_wt_lane_disabled 0x8000 //Per-Lane Wiretest lane disabled status +#define rx_wt_lane_disabled_clear 0x7FFF // Clear mask +#define rx_wt_lane_inverted 0x4000 //Per-Lane Wiretest lane inverted/swapped status +#define rx_wt_lane_inverted_clear 0xBFFF // Clear mask +#define rx_wt_lane_bad_code_n_stuck_1 0x0800 //Per-Lane Wiretest Lane Bad code N-leg stuck at 1. +#define rx_wt_lane_bad_code_n_stuck_0 0x1000 //Per-Lane Wiretest Lane Bad code N-leg stuck at 0. +#define rx_wt_lane_bad_code_p_stuck_1 0x1800 //Per-Lane Wiretest Lane Bad code P-leg stuck at 1. +#define rx_wt_lane_bad_code_p_stuck_0 0x2000 //Per-Lane Wiretest Lane Bad code P-leg stuck at 0. +#define rx_wt_lane_bad_code_n_or_p_floating 0x2800 //Per-Lane Wiretest Lane Bad code N- or P- leg floating-swapping undetermined. +#define rx_wt_lane_bad_code_p_or_n_floating 0x3000 //Per-Lane Wiretest Lane Bad code P or N leg floating--swapping undetermined. +#define rx_wt_lane_bad_code_unknown 0x3800 //Per-Lane Wiretest Lane Bad code Unknown failure. +#define rx_wt_lane_bad_code_clear 0xC7FF // Clear mask + +// rx_fifo_cntl_pl Register field name data value Description +#define rx_fifo_inc_l2u_dly 0x8000 //Increment existing FIFO load-to-unload delay register. +#define rx_fifo_inc_l2u_dly_clear 0x7FFF // Clear mask +#define rx_fifo_dec_l2u_dly 0x4000 //Decrement existing FIFO load-to-unload delay register. +#define rx_fifo_dec_l2u_dly_clear 0xBFFF // Clear mask +#define rx_clr_skew_valid 0x2000 //Clear skew valid registers +#define rx_clr_skew_valid_clear 0xDFFF // Clear mask +#define rx_fifo_cntl_spare 0x1000 //Spare to make cr happy. +#define rx_fifo_cntl_spare_clear 0xEFFF // Clear mask + +// rx_ber_status_pl Register field name data value Description +#define rx_ber_count 0x0000 //Per-Lane (PL) Diagnostic Bit Error Rate (BER) error counter. Increments when in diagnostic BER mode AND the output of the descrambler is non-zero. This counter counts errors on every UI so it is a true BER counter. +#define rx_ber_count_clear 0x80FF // Clear mask +#define rx_ber_count_saturated 0x0080 //PL Diag BER Error Counter saturation indicator. When '1' indicates that the error counter has saturated to the selected max value. A global per-lane read of this field will indicate if any lane error counters in the group are saturated. +#define rx_ber_count_saturated_clear 0xFF7F // Clear mask +#define rx_ber_count_frozen_by_lane 0x0040 //PL Diag BER Error Counter and or PP Timer has been frozen by another lane's error counter being saturated. +#define rx_ber_count_frozen_by_lane_clear 0xFFBF // Clear mask +#define rx_ber_count_frozen_by_timer 0x0020 //PL Diag BER Error Counter has been frozen by a diag BER timer becoming saturated. +#define rx_ber_count_frozen_by_timer_clear 0xFFDF // Clear mask +#define rx_ber_timer_saturated 0x0010 //PL Diag BER Timer saturation indicator. When '1' indicates that the pack BER timer has saturated to the max value. A global per-lane read of this field will indicate if any timer in the group has saturated. +#define rx_ber_timer_saturated_clear 0xFFEF // Clear mask + +// rx_ber_timer_0_15_pl Register field name data value Description +#define rx_ber_timer_value_0_15 0x0000 //PL Diag BER Timer value for this lane, bits 0-15. All lanes in a pack share a timer and will have the same timer value. The value can either be read on one lane in a pack to save data collection time or all lanes can be read. +#define rx_ber_timer_value_0_15_clear 0x0000 // Clear mask + +// rx_ber_timer_16_31_pl Register field name data value Description +#define rx_ber_timer_value_16_31 0x0000 //PL Diag BER Timer value, bits 16-31. +#define rx_ber_timer_value_16_31_clear 0x0000 // Clear mask + +// rx_ber_timer_32_39_pl Register field name data value Description +#define rx_ber_timer_value_32_39 0x0000 //PL Diag BER Timer value, bits 32-39. +#define rx_ber_timer_value_32_39_clear 0x00FF // Clear mask + +// rx_servo_cntl_pl Register field name data value Description +#define rx_servo_op_done 0x8000 //Servo Op completed +#define rx_servo_op_done_clear 0x7FFF // Clear mask +#define rx_servo_op_all_done_b 0x4000 //All Servo Op (asserted low for global dot-Or reading) +#define rx_servo_op_all_done_b_clear 0xBFFF // Clear mask +#define rx_servo_op 0x0000 //Servo Operation code +#define rx_servo_op_clear 0xC1FF // Clear mask + +// rx_fifo_diag_0_15_pl Register field name data value Description +#define rx_fifo_out_0_15 0x0000 //Diag Capture: fifo entries 0 to 15 +#define rx_fifo_out_0_15_clear 0x0000 // Clear mask + +// rx_fifo_diag_16_31_pl Register field name data value Description +#define rx_fifo_out_16_31 0x0000 //Diag Capture: fifo entries 16 to 31 +#define rx_fifo_out_16_31_clear 0x0000 // Clear mask + +// rx_fifo_diag_32_47_pl Register field name data value Description +#define rx_fifo_out_32_47 0x0000 //Diag Capture: fifo entries 32 to 47 +#define rx_fifo_out_32_47_clear 0x0000 // Clear mask + +// rx_eye_width_status_pl Register field name data value Description +#define rx_eye_width 0x0000 //RX Current Eye Width (in PR steps). +#define rx_eye_width_clear 0x00FF // Clear mask +#define rx_hist_min_eye_width_valid 0x0080 //RX Historic Eye Minimum is valid for this lane. +#define rx_hist_min_eye_width_valid_clear 0xFF7F // Clear mask +#define rx_hist_min_eye_width 0x0000 //RX Historic Eye Minimum--per-pack register valid for this lane if rx_hist_eye_min_valid is asserted for this lane. +#define rx_hist_min_eye_width_clear 0xDFC0 // Clear mask + +// rx_eye_width_cntl_pl Register field name data value Description +#define rx_reset_hist_eye_width_min 0x8000 //RX Historic Eye Minimum Reset--reset historic min to maximum value and clears valid bits. +#define rx_reset_hist_eye_width_min_clear 0x7FFF // Clear mask +#define rx_eye_width_cntl_pl_spare 0x4000 //RX Eye width control spare +#define rx_eye_width_cntl_pl_spare_clear 0xBFFF // Clear mask + +// rx_dfe_clkadj_pl Register field name data value Description +#define rx_dfe_clkadj 0x0000 //TBD +#define rx_dfe_clkadj_clear 0x0FFF // Clear mask + +// rx_clk_mode_pg Register field name data value Description +#define rx_clk_pdwn 0x8000 //Used to disable the rx clock and put it into a low power state. +#define rx_clk_pdwn_clear 0x7FFF // Clear mask +#define rx_clk_invert 0x4000 //Used to invert the polarity of the clock. +#define rx_clk_invert_clear 0xBFFF // Clear mask + +// rx_spare_mode_pg Register field name data value Description +#define rx_pg_spare_mode_0 0x8000 //Per-group spare mode latch +#define rx_pg_spare_mode_0_clear 0x7FFF // Clear mask +#define rx_pg_spare_mode_1 0x4000 //Per-group spare mode latch +#define rx_pg_spare_mode_1_clear 0xBFFF // Clear mask +#define rx_pg_spare_mode_2 0x2000 //Per-group spare mode latch +#define rx_pg_spare_mode_2_clear 0xDFFF // Clear mask +#define rx_pg_spare_mode_3 0x1000 //Per-group spare mode latch +#define rx_pg_spare_mode_3_clear 0xEFFF // Clear mask +#define rx_pg_spare_mode_4 0x0800 //Per-group spare mode latch +#define rx_pg_spare_mode_4_clear 0xF7FF // Clear mask +#define rx_pg_spare_mode_5 0x0400 //Per-group spare mode latch +#define rx_pg_spare_mode_5_clear 0xFBFF // Clear mask +#define rx_pg_spare_mode_6 0x0200 //Per-group spare mode latch +#define rx_pg_spare_mode_6_clear 0xFDFF // Clear mask +#define rx_pg_spare_mode_7 0x0100 //Per-group spare mode latch +#define rx_pg_spare_mode_7_clear 0xFEFF // Clear mask + +// rx_mode_pg Register field name data value Description +#define rx_master_mode 0x8000 //Master Mode +#define rx_master_mode_clear 0x7FFF // Clear mask +#define rx_disable_fence_reset 0x4000 //Set to disable clearing of the RX and TX fence controls at the end of training. +#define rx_disable_fence_reset_clear 0xBFFF // Clear mask + +// rx_bus_repair_pg Register field name data value Description +#define rx_bus_repair_count 0x0000 //TBD +#define rx_bus_repair_count_clear 0x3FFF // Clear mask +#define rx_bus_repair_pos_0 0x0000 //TBD +#define rx_bus_repair_pos_0_clear 0xC07F // Clear mask +#define rx_bus_repair_pos_1 0x0000 //TBD +#define rx_bus_repair_pos_1_clear 0x3F80 // Clear mask + +// rx_grp_repair_vec_0_15_pg Register field name data value Description +#define rx_grp_repair_vec_0_15 0x0000 //TBD +#define rx_grp_repair_vec_0_15_clear 0x0000 // Clear mask + +// rx_grp_repair_vec_16_31_pg Register field name data value Description +#define rx_grp_repair_vec_16_31 0x0000 //TBD +#define rx_grp_repair_vec_16_31_clear 0x0000 // Clear mask + +// rx_recal_mode_pg Register field name data value Description +#define rx_recal_disable 0x8000 //TBD +#define rx_recal_disable_clear 0x7FFF // Clear mask + +// rx_reset_act_pg Register field name data value Description +#define rx_reset_cfg_ena 0x8000 //Enable Configurable Group Reset +#define rx_reset_cfg_ena_clear 0x7FFF // Clear mask +#define rx_clr_par_errs 0x0002 //Clear All RX Parity Error Latches +#define rx_clr_par_errs_clear 0xFFFD // Clear mask +#define rx_fir_reset 0x0001 //FIR Reset +#define rx_fir_reset_clear 0xFFFE // Clear mask + +// rx_id1_pg Register field name data value Description +#define rx_bus_id 0x0000 //This field is used to programmably set the bus number that a clkgrp belongs to. +#define rx_bus_id_clear 0x03FF // Clear mask +#define rx_group_id 0x0000 //This field is used to programmably set the clock group number within a bus. +#define rx_group_id_clear 0xFE07 // Clear mask + +// rx_id2_pg Register field name data value Description +#define rx_last_group_id 0x0000 //This field is used to programmably set the last clock group number within a bus. +#define rx_last_group_id_clear 0x03FF // Clear mask + +// rx_id3_pg Register field name data value Description +#define rx_start_lane_id 0x0000 //This field is used to programmably set the first lane position in the group but relative to the bus. +#define rx_start_lane_id_clear 0x80FF // Clear mask +#define rx_end_lane_id 0x0000 //This field is used to programmably set the last lane position in the group but relative to the bus. +#define rx_end_lane_id_clear 0x7F80 // Clear mask + +// rx_minikerf_pg Register field name data value Description +#define rx_minikerf 0x0000 //Used to configure the rx Minikerf for analog characterization. +#define rx_minikerf_clear 0x0000 // Clear mask + +// rx_bist_cntl_pg Register field name data value Description +#define rx_bist_en 0x8000 //TBD +#define rx_bist_en_clear 0x7FFF // Clear mask +#define rx_bist_jitter_pulse_ctl 0x0000 //TBD +#define rx_bist_jitter_pulse_ctl_clear 0x9FFF // Clear mask +#define rx_bist_min_eye_width 0x0000 //TBD +#define rx_bist_min_eye_width_clear 0xF03F // Clear mask + +// rx_sls_mode_pg Register field name data value Description +#define rx_sls_disable 0x8000 //Disables receiving & decoding of SLS commands +#define rx_sls_disable_clear 0x7FFF // Clear mask +#define tx_sls_disable 0x4000 //Disables the sending of SLS commands +#define tx_sls_disable_clear 0xBFFF // Clear mask +#define rx_sls_cntr_tap_pts_tap2 0x1000 //How Long the SLS RX Command Needs to be Stable for. EDI - 32 c8 clks; EI4 - 64 c4 clks +#define rx_sls_cntr_tap_pts_tap3 0x2000 //How Long the SLS RX Command Needs to be Stable for. EDI - 64 c8 clks; EI4 - 128 c4 clks +#define rx_sls_cntr_tap_pts_tap4 0x3000 //How Long the SLS RX Command Needs to be Stable for. EDI - 128 c8 clks; EI4 - 256 c4 clks +#define rx_sls_cntr_tap_pts_clear 0xCFFF // Clear mask +#define rx_nonsls_cntr_tap_pts_tap2 0x0400 //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data). EDI - 64 c8 clks; EI4 - 128 c4 clks +#define rx_nonsls_cntr_tap_pts_tap3 0x0800 //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data). EDI - 128 c8 clks; EI4 - 256 c4 clks +#define rx_nonsls_cntr_tap_pts_tap4 0x0C00 //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data). EDI - 256 c8 clks; EI4 - 512 c4 clks +#define rx_nonsls_cntr_tap_pts_clear 0xF3FF // Clear mask +#define rx_sls_err_chk_run 0x0200 //Run SLS error check counter +#define rx_sls_err_chk_run_clear 0xFDFF // Clear mask + +// rx_training_start_pg Register field name data value Description +#define rx_start_wiretest 0x8000 //When this register is written to a 1 the training state machine will run the wiretest portion of the training states. +#define rx_start_wiretest_clear 0x7FFF // Clear mask +#define rx_start_deskew 0x4000 //When this register is written to a 1 the training state machine will run the deskew portion of the training states. +#define rx_start_deskew_clear 0xBFFF // Clear mask +#define rx_start_eye_opt 0x2000 //When this register is written to a 1 the training state machine will run the data eye optimization portion of the training states. +#define rx_start_eye_opt_clear 0xDFFF // Clear mask +#define rx_start_repair 0x1000 //When this register is written to a 1 the training state machine will run the static lane repair portion of the training states. +#define rx_start_repair_clear 0xEFFF // Clear mask +#define rx_start_func_mode 0x0800 //When this register is written to a 1 the training state machine will run the transition to functional data portion of the training states. +#define rx_start_func_mode_clear 0xF7FF // Clear mask +#define rx_start_bist_helper_1 0x0200 //Starts BIST helper state machine. (wtbyp +#define rx_start_bist_helper_2 0x0400 //Starts BIST helper state machine. (ocal +#define rx_start_bist_helper_3 0x0600 //Starts BIST helper state machine. (bist +#define rx_start_bist_helper_clear 0xF9FF // Clear mask + +// rx_training_status_pg Register field name data value Description +#define rx_wiretest_done 0x8000 //When this bit is read as a 1, the wiretest training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state. +#define rx_wiretest_done_clear 0x7FFF // Clear mask +#define rx_deskew_done 0x4000 //When this bit is read as a 1, the deskew training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state. +#define rx_deskew_done_clear 0xBFFF // Clear mask +#define rx_eye_opt_done 0x2000 //When this bit is read as a 1, the eye optimization training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state. +#define rx_eye_opt_done_clear 0xDFFF // Clear mask +#define rx_repair_done 0x1000 //When this bit is read as a 1, the static lane repair training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state. +#define rx_repair_done_clear 0xEFFF // Clear mask +#define rx_func_mode_done 0x0800 //When this bit is read as a 1, the transition to functional data training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state. +#define rx_func_mode_done_clear 0xF7FF // Clear mask +#define rx_bist_helper_done 0x0400 //When this bit is read as a 1, the BIST helper state machine has completed. +#define rx_bist_helper_done_clear 0xFBFF // Clear mask +#define rx_wiretest_failed 0x0080 //When this bit is read as a 1, the wiretest training state encountered an error. +#define rx_wiretest_failed_clear 0xFF7F // Clear mask +#define rx_deskew_failed 0x0040 //When this bit is read as a 1, the deskew training state encountered an error. +#define rx_deskew_failed_clear 0xFFBF // Clear mask +#define rx_eye_opt_failed 0x0020 //When this bit is read as a 1, the eye optimization training state encountered an error. +#define rx_eye_opt_failed_clear 0xFFDF // Clear mask +#define rx_repair_failed 0x0010 //When this bit is read as a 1, the static lane repair training state encountered an error. +#define rx_repair_failed_clear 0xFFEF // Clear mask +#define rx_func_mode_failed 0x0008 //When this bit is read as a 1, the transition to functional data training state encountered and error. +#define rx_func_mode_failed_clear 0xFFF7 // Clear mask + +// rx_recal_status_pg Register field name data value Description +#define rx_recal_status 0x0000 //\bRX Recalibration Status\b +#define rx_recal_status_clear 0x0000 // Clear mask + +// rx_timeout_sel_pg Register field name data value Description +#define rx_sls_timeout_sel_tap1 0x2000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 64k UI +#define rx_sls_timeout_sel_tap2 0x4000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 128k UI +#define rx_sls_timeout_sel_tap3 0x6000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 256k UI +#define rx_sls_timeout_sel_tap4 0x8000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 512k UI +#define rx_sls_timeout_sel_tap5 0xA000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 1024k UI +#define rx_sls_timeout_sel_tap6 0xC000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 32768k UI +#define rx_sls_timeout_sel_tap7 0xE000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) infinite +#define rx_sls_timeout_sel_clear 0x1FFF // Clear mask +#define rx_ds_bl_timeout_sel_tap1 0x0400 //Selects Deskew Block Lock Timeout value. 128k UI or 13.6us +#define rx_ds_bl_timeout_sel_tap2 0x0800 //Selects Deskew Block Lock Timeout value. 256k UI or 27.3us +#define rx_ds_bl_timeout_sel_tap3 0x0C00 //Selects Deskew Block Lock Timeout value. 1M UI or 109.2us +#define rx_ds_bl_timeout_sel_tap4 0x1000 //Selects Deskew Block Lock Timeout value. 2M UI or 218.5us +#define rx_ds_bl_timeout_sel_tap5 0x1400 //Selects Deskew Block Lock Timeout value. 4M UI or 436.9us +#define rx_ds_bl_timeout_sel_tap6 0x1800 //Selects Deskew Block Lock Timeout value. 8M UI or 873.8us +#define rx_ds_bl_timeout_sel_tap7 0x1C00 //Selects Deskew Block Lock Timeout value. infinite +#define rx_ds_bl_timeout_sel_clear 0xE3FF // Clear mask +#define rx_cl_timeout_sel_tap1 0x0080 //Selects Clock Lock Timeout value. 128k UI or 13.6us +#define rx_cl_timeout_sel_tap2 0x0100 //Selects Clock Lock Timeout value. 256k UI or 27.3us +#define rx_cl_timeout_sel_tap3 0x0180 //Selects Clock Lock Timeout value. 1M UI or 109.2us +#define rx_cl_timeout_sel_tap4 0x0200 //Selects Clock Lock Timeout value. 2M UI or 218.5us +#define rx_cl_timeout_sel_tap5 0x0280 //Selects Clock Lock Timeout value. 4M UI or 436.9us +#define rx_cl_timeout_sel_tap6 0x0300 //Selects Clock Lock Timeout value. 8M UI or 873.8us +#define rx_cl_timeout_sel_tap7 0x0380 //Selects Clock Lock Timeout value. infinite +#define rx_cl_timeout_sel_clear 0xFC7F // Clear mask +#define rx_wt_timeout_sel_tap1 0x0010 //Selects Wiretest Timeout value. 128k UI or 13.6us +#define rx_wt_timeout_sel_tap2 0x0020 //Selects Wiretest Timeout value. 256k UI or 27.3us +#define rx_wt_timeout_sel_tap3 0x0030 //Selects Wiretest Timeout value. 1M UI or 109.2us +#define rx_wt_timeout_sel_tap4 0x0040 //Selects Wiretest Timeout value. 2M UI or 218.5us +#define rx_wt_timeout_sel_tap5 0x0050 //Selects Wiretest Timeout value. 4M UI or 436.9us +#define rx_wt_timeout_sel_tap6 0x0060 //Selects Wiretest Timeout value. 8M UI or 873.8us +#define rx_wt_timeout_sel_tap7 0x0070 //Selects Wiretest Timeout value. infinite +#define rx_wt_timeout_sel_clear 0xC78F // Clear mask +#define rx_ds_timeout_sel_tap1 0x0002 //Selects Deskew Timeout value. 128k UI or 13.6us +#define rx_ds_timeout_sel_tap2 0x0004 //Selects Deskew Timeout value. 256k UI or 27.3us +#define rx_ds_timeout_sel_tap3 0x0006 //Selects Deskew Timeout value. 1M UI or 109.2us +#define rx_ds_timeout_sel_tap4 0x0008 //Selects Deskew Timeout value. 2M UI or 218.5us +#define rx_ds_timeout_sel_tap5 0x000A //Selects Deskew Timeout value. 4M UI or 436.9us +#define rx_ds_timeout_sel_tap6 0x000C //Selects Deskew Timeout value. 8M UI or 873.8us +#define rx_ds_timeout_sel_tap7 0x000E //Selects Deskew Timeout value. infinite +#define rx_ds_timeout_sel_clear 0xFF11 // Clear mask + +// rx_fifo_mode_pg Register field name data value Description +#define rx_fifo_initial_l2u_dly 0x0000 //RX FIFO Initial Load to Unload Delay. For setting X, the latency is 4*X to 4*X+4 UI. Default is 16-20 UI. +#define rx_fifo_initial_l2u_dly_clear 0x0FFF // Clear mask +#define rx_fifo_final_l2u_dly 0x0000 //RX FIFO Final Load to Unload Delay. For setting X, the latency is 4*X to 4*X+4 UI. Default is 8-12 UI. +#define rx_fifo_final_l2u_dly_clear 0xF0FF // Clear mask +#define rx_fifo_max_deskew 0x0000 //RX FIFO Max Deskew Control Value. TBD +#define rx_fifo_max_deskew_clear 0xFF0F // Clear mask +#define rx_fifo_final_l2u_min_err_thresh_tap1 0x0004 //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by rx_eo_final_l2u_timeout_sel. 16 errors +#define rx_fifo_final_l2u_min_err_thresh_tap2 0x0008 //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by rx_eo_final_l2u_timeout_sel. 128 errors +#define rx_fifo_final_l2u_min_err_thresh_tap3 0x000C //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by rx_eo_final_l2u_timeout_sel. 255 errors +#define rx_fifo_final_l2u_min_err_thresh_clear 0xFF33 // Clear mask + +// rx_state_debug_pg Register field name data value Description +#define rx_start_at_state_en 0x8000 //Enable Statemachine to Start +#define rx_start_at_state_en_clear 0x7FFF // Clear mask +#define rx_stop_at_state_en 0x4000 //Enable Statemachine to Stop +#define rx_stop_at_state_en_clear 0xBFFF // Clear mask +#define rx_state_stopped 0x2000 //Statemachine Has Stopped at RX_STOP_STATE +#define rx_state_stopped_clear 0xDFFF // Clear mask +#define rx_cur_state 0x0000 //Current Value of Statemachine Vector +#define rx_cur_state_clear 0xE01F // Clear mask + +// rx_state_val_pg Register field name data value Description +#define rx_start_state 0x0000 //Start Value for Statemachine +#define rx_start_state_clear 0x00FF // Clear mask +#define rx_stop_state 0x0000 //Stop Value for Statemachine +#define rx_stop_state_clear 0xFF00 // Clear mask + +// rx_sls_status_pg Register field name data value Description +#define rx_sls_cmd_val 0x8000 //Current SLS Command Valid +#define rx_sls_cmd_val_clear 0x7FFF // Clear mask +#define rx_sls_cmd_encode_shadow_request 0x0100 //Current SLS Command Driven by the RX side to request shadowing of its receive lane from lane n-1 to lane n +#define rx_sls_cmd_encode_shadow_done 0x0200 //Current SLS Command Driven by the RX side to signal now receiving lane n-1s data on lane n +#define rx_sls_cmd_encode_shadow_repair_request 0x0300 //Current SLS Command Driven by the RX side to request shadowing and repair of its receive lane from lane n-1 to n. +#define rx_sls_cmd_encode_shadow_repair_done 0x0400 //Current SLS Command Driven by the RX side to signal lane n-1 is repaired. +#define rx_sls_cmd_encode_unshadow_request 0x0500 //Current SLS Command Driven by the RX side to request shadowing of receive lane from lane n+1 to lane n. +#define rx_sls_cmd_encode_unshadow_done 0x0600 //Current SLS Command Driven by the RX side to signal now receiving lane n+1 data on lane n +#define rx_sls_cmd_encode_unshadow_repair_request 0x0700 //Current SLS Command Driven by the RX side to request unshadowing and repair of its receive lane from lane n+1 to lane n. +#define rx_sls_cmd_encode_unshadow_repair_done 0x0800 //Current SLS Command Driven by the RX side to signal lane n+1 is repaired. +#define rx_sls_cmd_encode_sls_exception 0x0900 //Current SLS Command Driven by the RX side to indicate to the other side of the bus its RX SLS lane is broken. +#define rx_sls_cmd_encode_init_done 0x0A00 //Current SLS Command Driven to signal the CTLE/DFE/offset (re- +#define rx_sls_cmd_encode_recal_request 0x0B00 //Current SLS Command Driven on recalibration lane x to request a recalibration of its receive recalibration lane y. +#define rx_sls_cmd_encode_recal_running 0x0C00 //Current SLS Command Driven during the status reporting interval of recalibration to indicate recalibration has not completed +#define rx_sls_cmd_encode_recal_done 0x0D00 //Current SLS Command Driven to indicate its recalibration is complete. +#define rx_sls_cmd_encode_recal_failed 0x0E00 //Current SLS Command Driven to indicate recalibration has failed on its receive recalibration lane +#define rx_sls_cmd_encode_recal_abort 0x0F00 //Current SLS Command Abort recalibration. +#define rx_sls_cmd_encode_reserved2 0x1000 //Current SLS Command Reserved.010001 +#define rx_sls_cmd_encode_reserved4 0x1200 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved5 0x1300 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved6 0x1400 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved7 0x1500 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved8 0x1600 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved9 0x1700 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved10 0x1800 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_init_ack_done 0x1900 //Current SLS Command Driven in response to an init_done (not currently used +#define rx_sls_cmd_encode_reserved11 0x1A00 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_recal_ack 0x1B00 //Current SLS Command Driven on recalibration lane y in response to a recal_request on its receive recalibration lane x +#define rx_sls_cmd_encode_reserved12 0x1C00 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved13 0x1D00 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_reserved14 0x1E00 //Current SLS Command Reserved. +#define rx_sls_cmd_encode_recal_abort_ack 0x1F00 //Current SLS Command Abort recalibration acknowledge. +#define rx_sls_cmd_encode_clear 0xC0FF // Clear mask +#define rx_sls_err_chk_cnt 0x0000 //Error count result for SLS error checking mode +#define rx_sls_err_chk_cnt_clear 0xFF00 // Clear mask + +// rx_fir1_pg Register field name data value Description +#define rx_pg_fir1_errs_clear 0x0003 // Clear mask +#define rx_pl_fir_err 0x0001 //Summary bit indicating an RX per-lane register or state machine parity error has occurred in one or more lanes. The rx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane. +#define rx_pl_fir_err_clear 0xFFFE // Clear mask + +// rx_fir2_pg Register field name data value Description +#define rx_pg_fir2_errs_clear 0x1FFF // Clear mask + +// rx_fir1_mask_pg Register field name data value Description +#define rx_pg_fir1_errs_mask_clear 0x0003 // Clear mask +#define rx_pg_chan_fail_mask 0x0002 //FIR mask for generation of channel fail error when Max Spares Exceeded is active. Default is disabled with a value of 1. +#define rx_pg_chan_fail_mask_clear 0xFFFD // Clear mask +#define rx_pl_fir_err_mask 0x0001 //FIR mask for the summary bit that indicates an RX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane parity errors from causing a FIR error. +#define rx_pl_fir_err_mask_clear 0xFFFE // Clear mask + +// rx_fir2_mask_pg Register field name data value Description +#define rx_pg_fir2_errs_mask_clear 0x1FFF // Clear mask + +// rx_fir1_error_inject_pg Register field name data value Description +#define rx_pg_fir1_err_inj_inj_par_err 0x4000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pg_fir1_err_inj_clear 0x0003 // Clear mask + +// rx_fir2_error_inject_pg Register field name data value Description +#define rx_pg_fir2_err_inj_inj_par_err 0x2000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pg_fir2_err_inj_clear 0x1FFF // Clear mask + +// rx_fir_training_pg Register field name data value Description +#define rx_pg_fir_training_error 0x8000 //A Training Error has occurred. The Training Error FFDC registers should be read to help isolate to a particular piece of logic. +#define rx_pg_fir_training_error_clear 0x7FFF // Clear mask +#define rx_pg_fir_static_spare_deployed 0x4000 //A spare lane has been deployed during training to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed +#define rx_pg_fir_static_spare_deployed_clear 0xBFFF // Clear mask +#define rx_pg_fir_static_max_spares_exceeded 0x2000 //A lane has been detected as bad during training but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define rx_pg_fir_static_max_spares_exceeded_clear 0xDFFF // Clear mask +#define rx_pg_fir_dynamic_spare_deployed 0x1000 //A spare lane has been deployed by ECC/CRC logic to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. +#define rx_pg_fir_dynamic_spare_deployed_clear 0xEFFF // Clear mask +#define rx_pg_fir_dynamic_max_spares_exceeded 0x0800 //A lane has been detected as bad by ECC/CRC logic but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define rx_pg_fir_dynamic_max_spares_exceeded_clear 0xF7FF // Clear mask +#define rx_pg_fir_recal_error 0x0400 //A Recalibration Error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic. +#define rx_pg_fir_recal_error_clear 0xFBFF // Clear mask +#define rx_pg_fir_recal_spare_deployed 0x0200 //A spare lane has been deployed during Recal to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. +#define rx_pg_fir_recal_spare_deployed_clear 0xFDFF // Clear mask +#define rx_pg_fir_recal_max_spares_exceeded 0x0100 //A lane has been detected as bad during Recal but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define rx_pg_fir_recal_max_spares_exceeded_clear 0xFEFF // Clear mask + +// rx_fir_training_mask_pg Register field name data value Description +#define rx_pg_fir_training_error_mask 0x8000 //FIR mask for rx_pg_fir_training_error. +#define rx_pg_fir_training_error_mask_clear 0x7FFF // Clear mask +#define rx_pg_fir_static_spare_deployed_mask 0x4000 //FIR mask for rx_pg_fir_static_spare_deployed. +#define rx_pg_fir_static_spare_deployed_mask_clear 0xBFFF // Clear mask +#define rx_pg_fir_static_max_spares_exceeded_mask 0x2000 //FIR mask for rx_pg_fir_static_max_spares_exceeded +#define rx_pg_fir_static_max_spares_exceeded_mask_clear 0xDFFF // Clear mask +#define rx_pg_fir_dynamic_spare_deployed_mask 0x1000 //FIR mask for rx_pg_fir_dynamic_spare_deployed. +#define rx_pg_fir_dynamic_spare_deployed_mask_clear 0xEFFF // Clear mask +#define rx_pg_fir_dynamic_max_spares_exceeded_mask 0x0800 //FIR mask for rx_pg_fir_dynamic_max_spares_exceeded. +#define rx_pg_fir_dynamic_max_spares_exceeded_mask_clear 0xF7FF // Clear mask +#define rx_pg_fir_recal_error_mask 0x0400 //FIR mask for rx_pg_fir_recal_error. +#define rx_pg_fir_recal_error_mask_clear 0xFBFF // Clear mask +#define rx_pg_fir_recal_spare_deployed_mask 0x0200 //FIR mask for rx_pg_fir_recal_spare_deployed. +#define rx_pg_fir_recal_spare_deployed_mask_clear 0xFDFF // Clear mask +#define rx_pg_fir_recal_max_spares_exceeded_mask 0x0100 //FIR mask for rx_pg_fir_recal_max_spares_exceeded. +#define rx_pg_fir_recal_max_spares_exceeded_mask_clear 0xFEFF // Clear mask + +// rx_timeout_sel1_pg Register field name data value Description +#define rx_eo_offset_timeout_sel_tap1 0x2000 //Selects Latch offset timeout. 128k UI or 13.6us +#define rx_eo_offset_timeout_sel_tap2 0x4000 //Selects Latch offset timeout. 256k UI or 27.3us +#define rx_eo_offset_timeout_sel_tap3 0x6000 //Selects Latch offset timeout. 1M UI or 109.2us +#define rx_eo_offset_timeout_sel_tap4 0x8000 //Selects Latch offset timeout. 2M UI or 218.5us +#define rx_eo_offset_timeout_sel_tap5 0xA000 //Selects Latch offset timeout. 4M UI or 436.9us +#define rx_eo_offset_timeout_sel_tap6 0xC000 //Selects Latch offset timeout. 8M UI or 873.8us +#define rx_eo_offset_timeout_sel_tap7 0xE000 //Selects Latch offset timeout. infinite +#define rx_eo_offset_timeout_sel_clear 0x1FFF // Clear mask +#define rx_eo_amp_timeout_sel_tap1 0x0400 //Selects Amplitude measurement watchdog timeout. 128k UI or 13.6us +#define rx_eo_amp_timeout_sel_tap2 0x0800 //Selects Amplitude measurement watchdog timeout. 256k UI or 27.3us +#define rx_eo_amp_timeout_sel_tap3 0x0C00 //Selects Amplitude measurement watchdog timeout. 1M UI or 109.2us +#define rx_eo_amp_timeout_sel_tap4 0x1000 //Selects Amplitude measurement watchdog timeout. 2M UI or 218.5us +#define rx_eo_amp_timeout_sel_tap5 0x1400 //Selects Amplitude measurement watchdog timeout. 4M UI or 436.9us +#define rx_eo_amp_timeout_sel_tap6 0x1800 //Selects Amplitude measurement watchdog timeout. 8M UI or 873.8us +#define rx_eo_amp_timeout_sel_tap7 0x1C00 //Selects Amplitude measurement watchdog timeout. infinite +#define rx_eo_amp_timeout_sel_clear 0xE3FF // Clear mask +#define rx_eo_ctle_timeout_sel_tap1 0x0080 //Selects CTLE ajdust watchdog timeout. 128k UI or 13.6us +#define rx_eo_ctle_timeout_sel_tap2 0x0100 //Selects CTLE ajdust watchdog timeout. 256k UI or 27.3us +#define rx_eo_ctle_timeout_sel_tap3 0x0180 //Selects CTLE ajdust watchdog timeout. 1M UI or 109.2us +#define rx_eo_ctle_timeout_sel_tap4 0x0200 //Selects CTLE ajdust watchdog timeout. 2M UI or 218.5us +#define rx_eo_ctle_timeout_sel_tap5 0x0280 //Selects CTLE ajdust watchdog timeout. 4M UI or 436.9us +#define rx_eo_ctle_timeout_sel_tap6 0x0300 //Selects CTLE ajdust watchdog timeout. 8M UI or 873.8us +#define rx_eo_ctle_timeout_sel_tap7 0x0380 //Selects CTLE ajdust watchdog timeout. infinite +#define rx_eo_ctle_timeout_sel_clear 0xFC7F // Clear mask +#define rx_eo_h1ap_timeout_sel_tap1 0x0010 //Selects H1Ap ajdust watchdog timeout. 128k UI or 13.6us +#define rx_eo_h1ap_timeout_sel_tap2 0x0020 //Selects H1Ap ajdust watchdog timeout. 256k UI or 27.3us +#define rx_eo_h1ap_timeout_sel_tap3 0x0030 //Selects H1Ap ajdust watchdog timeout. 1M UI or 109.2us +#define rx_eo_h1ap_timeout_sel_tap4 0x0040 //Selects H1Ap ajdust watchdog timeout. 2M UI or 218.5us +#define rx_eo_h1ap_timeout_sel_tap5 0x0050 //Selects H1Ap ajdust watchdog timeout. 4M UI or 436.9us +#define rx_eo_h1ap_timeout_sel_tap6 0x0060 //Selects H1Ap ajdust watchdog timeout. 8M UI or 873.8us +#define rx_eo_h1ap_timeout_sel_tap7 0x0070 //Selects H1Ap ajdust watchdog timeout. infinite +#define rx_eo_h1ap_timeout_sel_clear 0xC78F // Clear mask +#define rx_eo_ddc_timeout_sel_tap1 0x0002 //Selects DDC watchdog timeout (EDI ONLY). 128k UI or 13.6us +#define rx_eo_ddc_timeout_sel_tap2 0x0004 //Selects DDC watchdog timeout (EDI ONLY). 256k UI or 27.3us +#define rx_eo_ddc_timeout_sel_tap3 0x0006 //Selects DDC watchdog timeout (EDI ONLY). 1M UI or 109.2us +#define rx_eo_ddc_timeout_sel_tap4 0x0008 //Selects DDC watchdog timeout (EDI ONLY). 2M UI or 218.5us +#define rx_eo_ddc_timeout_sel_tap5 0x000A //Selects DDC watchdog timeout (EDI ONLY). 4M UI or 436.9us +#define rx_eo_ddc_timeout_sel_tap6 0x000C //Selects DDC watchdog timeout (EDI ONLY). 8M UI or 873.8us +#define rx_eo_ddc_timeout_sel_tap7 0x000E //Selects DDC watchdog timeout (EDI ONLY). infinite +#define rx_eo_ddc_timeout_sel_clear 0xFF11 // Clear mask +#define rx_eo_final_l2u_timeout_sel 0x0001 //Selects Final Load to Unload Delay qualification time per step. +#define rx_eo_final_l2u_timeout_sel_clear 0xFFFE // Clear mask + +// rx_lane_bad_vec_0_15_pg Register field name data value Description +#define rx_lane_bad_vec_0_15 0x0000 //Lanes found bad by HW (status) or method to force lane bad from software (control). +#define rx_lane_bad_vec_0_15_clear 0x0000 // Clear mask + +// rx_lane_bad_vec_16_31_pg Register field name data value Description +#define rx_lane_bad_vec_16_31 0x0000 //Lanes found bad by HW (status) or method to force lane bad from software (control). +#define rx_lane_bad_vec_16_31_clear 0x0000 // Clear mask + +// rx_lane_disabled_vec_0_15_pg Register field name data value Description +#define rx_lane_disabled_vec_0_15 0x0000 //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control). +#define rx_lane_disabled_vec_0_15_clear 0x0000 // Clear mask + +// rx_lane_disabled_vec_16_31_pg Register field name data value Description +#define rx_lane_disabled_vec_16_31 0x0000 //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control). +#define rx_lane_disabled_vec_16_31_clear 0x0000 // Clear mask + +// rx_lane_swapped_vec_0_15_pg Register field name data value Description +#define rx_lane_swapped_vec_0_15 0x0000 //Wiretest found that the P & N wire legs have been swapped on the lane indicated. Has the effect of basically inverting the signal. Note that this status is invalid if the lane is marked bad. +#define rx_lane_swapped_vec_0_15_clear 0x0000 // Clear mask + +// rx_lane_swapped_vec_16_31_pg Register field name data value Description +#define rx_lane_swapped_vec_16_31 0x0000 //Wiretest found that the P & N wire legs have been swapped on the lane indicated. Has the effect of basically inverting the signal. Note that this status is invalid if the lane is marked bad. +#define rx_lane_swapped_vec_16_31_clear 0x0000 // Clear mask + +// rx_init_state_pg Register field name data value Description +#define rx_main_init_state_1 0x1000 //Main Initialization State Machine(RJR): Wiretest Running +#define rx_main_init_state_2 0x2000 //Main Initialization State Machine(RJR): Deskew Running +#define rx_main_init_state_3 0x3000 //Main Initialization State Machine(RJR): Eye Optimization Running +#define rx_main_init_state_4 0x4000 //Main Initialization State Machine(RJR): Repair Running +#define rx_main_init_state_5 0x5000 //Main Initialization State Machine(RJR): Go Functional Running +#define rx_main_init_state_6 0x9000 //Main Initialization State Machine(RJR): Wiretest Failed +#define rx_main_init_state_7 0x5000 //Main Initialization State Machine(RJR): Deskew Failed +#define rx_main_init_state_8 0xB000 //Main Initialization State Machine(RJR): Eye Optimization Failed +#define rx_main_init_state_9 0xC000 //Main Initialization State Machine(RJR): Repair Failed +#define rx_main_init_state_10 0xD000 //Main Initialization State Machine(RJR): Go Functional Failed +#define rx_main_init_state_clear 0x0FFF // Clear mask + +// rx_wiretest_state_pg Register field name data value Description +#define rx_wtm_state_clear 0x07FF // Clear mask +#define rx_wtr_state_clear 0xF87F // Clear mask +#define rx_wtl_state_clear 0x0FE0 // Clear mask + +// rx_wiretest_laneinfo_pg Register field name data value Description +#define rx_wtr_cur_lane 0x0000 //Wiretest Current Lane Under Test(RJR) +#define rx_wtr_cur_lane_clear 0x07FF // Clear mask +#define rx_wtr_max_bad_lanes_clear 0xF83F // Clear mask +#define rx_wtr_bad_lane_count 0x0000 //Wiretest Current Number Of Bad Lanes in This Clk Group(RJR) +#define rx_wtr_bad_lane_count_clear 0x07E0 // Clear mask + +// rx_wiretest_gcrmsgs_pg Register field name data value Description +#define rx_wt_prev_done_gcrmsg 0x8000 //GCR Message: Previous Clk Group Has Completed Wiretest +#define rx_wt_prev_done_gcrmsg_clear 0x7FFF // Clear mask +#define rx_wt_all_done_gcrmsg 0x4000 //GCR Message: All Clk Groups Have Completed Wiretest +#define rx_wt_all_done_gcrmsg_clear 0xBFFF // Clear mask + +// rx_deskew_gcrmsgs_pg Register field name data value Description +#define rx_deskew_seq_gcrmsg_dsalldeskewed 0x2000 //GCR Message: RX Deskew Sequencer GCR messages Indicate all groups deskewed. +#define rx_deskew_seq_gcrmsg_dsprevdone 0x4000 //GCR Message: RX Deskew Sequencer GCR messages Indicate prior group completed deskew. +#define rx_deskew_seq_gcrmsg_dsalldone 0x6000 //GCR Message: RX Deskew Sequencer GCR messages Indicate all groups completed deskew. +#define rx_deskew_seq_gcrmsg_dsprevskew 0x8000 //GCR Message: RX Deskew Sequencer GCR messages Transmit skew values from prior group. +#define rx_deskew_seq_gcrmsg_dsmaxskew 0xA000 //GCR Message: RX Deskew Sequencer GCR messages Transmit max skew values to all groups. +#define rx_deskew_seq_gcrmsg_unused 0xC000 //GCR Message: RX Deskew Sequencer GCR messages Unused. +#define rx_deskew_seq_gcrmsg_dsnomsg 0xE000 //GCR Message: RX Deskew Sequencer GCR messages No message. +#define rx_deskew_seq_gcrmsg_clear 0x1FFF // Clear mask +#define rx_deskew_skmin_gcrmsg 0x0000 //GCR Message: Min Skew Value for deskew sequence. +#define rx_deskew_skmin_gcrmsg_clear 0xF03F // Clear mask +#define rx_deskew_skmax_gcrmsg 0x0000 //GCR Message: Max Skew Value for deskew sequence. +#define rx_deskew_skmax_gcrmsg_clear 0x0FC0 // Clear mask + +// rx_deskew_state_pg Register field name data value Description +#define rx_dsm_state_clear 0x00FF // Clear mask +#define rx_rxdsm_state_clear 0x7F80 // Clear mask + +// rx_deskew_mode_pg Register field name data value Description +#define rx_deskew_max_limit 0x0000 //Maximum Deskewable Skew Fail Threshold +#define rx_deskew_max_limit_clear 0x03FF // Clear mask + +// rx_deskew_status_pg Register field name data value Description +#define rx_deskew_minskew_grp 0x0000 //Deskew Per-Group Raw Skew Min +#define rx_deskew_minskew_grp_clear 0x03FF // Clear mask +#define rx_deskew_maxskew_grp 0x0000 //Deskew Per-Group Raw Skew Max +#define rx_deskew_maxskew_grp_clear 0xFC0F // Clear mask + +// rx_bad_lane_enc_gcrmsg_pg Register field name data value Description +#define rx_bad_lane1_gcrmsg 0x0000 //GCR Message: Encoded bad lane one in relation to the entire RX bus +#define rx_bad_lane1_gcrmsg_clear 0x01FF // Clear mask +#define rx_bad_lane2_gcrmsg 0x0000 //GCR Message: Encoded bad lane two in relation to the entire RX bus +#define rx_bad_lane2_gcrmsg_clear 0xFE03 // Clear mask +#define rx_bad_lane_code_gcrmsg_bad_ln1_val 0x0001 //GCR Message: RX Bad Lane Code Bad Lane 1 Valid +#define rx_bad_lane_code_gcrmsg_bad_lns12_val 0x0002 //GCR Message: RX Bad Lane Code Bad Lanes 1 and 2 Valid +#define rx_bad_lane_code_gcrmsg_3plus_bad_lns 0x0003 //GCR Message: RX Bad Lane Code 3+ bad lanes +#define rx_bad_lane_code_gcrmsg_clear 0xFFF0 // Clear mask + +// rx_static_repair_state_pg Register field name data value Description +#define rx_rpr_state_clear 0x03FF // Clear mask + +// rx_tx_bus_info_pg Register field name data value Description +#define rx_tx_bus_width 0x0000 //TX Bus Width +#define rx_tx_bus_width_clear 0x01FF // Clear mask +#define rx_rx_bus_width 0x0000 //RX Bus Width +#define rx_rx_bus_width_clear 0xFE03 // Clear mask + +// rx_sls_lane_enc_gcrmsg_pg Register field name data value Description +#define rx_sls_lane_gcrmsg 0x0000 //GCR Message: Encoded SLS lane in relation to the entire RX bus +#define rx_sls_lane_gcrmsg_clear 0x01FF // Clear mask +#define rx_sls_lane_val_gcrmsg 0x0100 //GCR Message: RX SLS Lane Valid +#define rx_sls_lane_val_gcrmsg_clear 0xFEFF // Clear mask + +// rx_fence_pg Register field name data value Description +#define rx_fence 0x8000 //RX fence bit +#define rx_fence_clear 0x7FFF // Clear mask + +// rx_timeout_sel2_pg Register field name data value Description +#define rx_func_mode_timeout_sel_tap1 0x2000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. 128k UI or 13.7us +#define rx_func_mode_timeout_sel_tap2 0x4000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. 256k UI or 27.3us +#define rx_func_mode_timeout_sel_tap3 0x6000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. 512k UI or 54.6us +#define rx_func_mode_timeout_sel_tap4 0x8000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. 1M UI or 109.2us +#define rx_func_mode_timeout_sel_tap5 0xA000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. 2M UI or 218.5us +#define rx_func_mode_timeout_sel_tap6 0xC000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. 64M UI or 7ms +#define rx_func_mode_timeout_sel_tap7 0xE000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. infinite +#define rx_func_mode_timeout_sel_clear 0x1FFF // Clear mask + +// rx_misc_analog_pg Register field name data value Description +#define rx_c4_sel 0x0000 //Select 1 of 4 possible phases for the C4 clock to send along with the data for integration flexibility and tuning for slack into the Rx FIFO. +#define rx_c4_sel_clear 0x3FFF // Clear mask +#define rx_negz_en 0x2000 //Turns on a gyrator stage in the CTLE pushing up the high freq corner +#define rx_negz_en_clear 0xDFFF // Clear mask +#define rx_prot_speed_slct 0x1000 //TBD (Enable the flux capacitor?) +#define rx_prot_speed_slct_clear 0xEFFF // Clear mask +#define rx_iref_bc 0x0000 //Bias Code for the Iref macros on the RX side. All eight 3 bit codes enable current out. The cml voltage swings of the output current will vary with this code. +#define rx_iref_bc_clear 0xF1FF // Clear mask + +// rx_dyn_rpr_pg Register field name data value Description +#define rx_dyn_rpr_state_clear 0xC0FF // Clear mask +#define rx_sls_hndshk_state_clear 0xFF00 // Clear mask + +// rx_dyn_rpr_gcrmsg_pg Register field name data value Description +#define rx_dyn_rpr_req_gcrmsg 0x8000 //GCR Message: CRC/ECC Tallying logic has a Dynamic Repair Request +#define rx_dyn_rpr_req_gcrmsg_clear 0x7FFF // Clear mask +#define rx_dyn_rpr_lane2rpr_gcrmsg 0x0000 //GCR Message: CRC/ECC Tallying logic bad lane to repair +#define rx_dyn_rpr_lane2rpr_gcrmsg_clear 0x80FF // Clear mask +#define rx_dyn_rpr_ip_gcrmsg 0x0080 //GCR Message: CRC/ECC Bad Lane Repair In Progress +#define rx_dyn_rpr_ip_gcrmsg_clear 0xFF7F // Clear mask +#define rx_dyn_rpr_complete_gcrmsg 0x0040 //GCR Message: CRC/ECC Bad Lane Repaired +#define rx_dyn_rpr_complete_gcrmsg_clear 0xFFBF // Clear mask + +// rx_dyn_rpr_err_tallying_pg Register field name data value Description +#define rx_dyn_rpr_bad_lane_max 0x0000 //CRC/ECC Dynamic Repair: Max number of times a lane can be found bad before repaired +#define rx_dyn_rpr_bad_lane_max_clear 0x07FF // Clear mask +#define rx_dyn_rpr_err_cntr_duration_tap1 0x0100 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 106.6ns +#define rx_dyn_rpr_err_cntr_duration_tap2 0x0200 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 1.7uS +#define rx_dyn_rpr_err_cntr_duration_tap3 0x0300 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 27.3uS +#define rx_dyn_rpr_err_cntr_duration_tap4 0x0400 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 436.7uS +#define rx_dyn_rpr_err_cntr_duration_tap5 0x0500 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 7.0mS +#define rx_dyn_rpr_err_cntr_duration_tap6 0x0600 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 111.8mS +#define rx_dyn_rpr_err_cntr_duration_tap7 0x0700 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 1.8S +#define rx_dyn_rpr_err_cntr_duration_clear 0xF8FF // Clear mask +#define rx_dyn_rpr_clr_err_cntr 0x0080 //CRC/ECC Dynamic Repair: Firmware-based clear of error counter register +#define rx_dyn_rpr_clr_err_cntr_clear 0xFF7F // Clear mask + +// rx_eo_final_l2u_gcrmsgs_pg Register field name data value Description +#define rx_eo_final_l2u_dly_seq_gcrmsg_fl2uallchg 0x4000 //GCR Message: RX Final Load to Unload Delay GCR messages Indicate all groups have calculated max load to unload change. +#define rx_eo_final_l2u_dly_seq_gcrmsg_unused 0x8000 //GCR Message: RX Final Load to Unload Delay GCR messages Unused. +#define rx_eo_final_l2u_dly_seq_gcrmsg_fl2unomsg 0xC000 //GCR Message: RX Final Load to Unload Delay GCR messages No message. +#define rx_eo_final_l2u_dly_seq_gcrmsg_clear 0x3FFF // Clear mask +#define rx_eo_final_l2u_dly_maxchg_gcrmsg 0x0000 //GCR Message: Max change in miniumum load to unload delay. +#define rx_eo_final_l2u_dly_maxchg_gcrmsg_clear 0xC0FF // Clear mask +#define rx_eo_final_l2u_dly_chg 0x0000 //GCR Message: Local change in miniumum load to unload delay. +#define rx_eo_final_l2u_dly_chg_clear 0x3FC0 // Clear mask + +// rx_gcr_msg_debug_dest_ids_pg Register field name data value Description +#define rx_gcr_msg_debug_dest_bus_id_clear 0x03FF // Clear mask +#define rx_gcr_msg_debug_dest_group_id_clear 0xFC0F // Clear mask + +// rx_gcr_msg_debug_src_ids_pg Register field name data value Description +#define rx_gcr_msg_debug_src_bus_id_clear 0x03FF // Clear mask +#define rx_gcr_msg_debug_src_group_id_clear 0xFC0F // Clear mask + +// rx_gcr_msg_debug_dest_addr_pg Register field name data value Description +#define rx_gcr_msg_debug_dest_addr_clear 0x007F // Clear mask +#define rx_gcr_msg_debug_send_msg 0x0001 //GCR Messaging Debug: Send GCR Message on rising edge of this bit. +#define rx_gcr_msg_debug_send_msg_clear 0xFFFE // Clear mask + +// rx_gcr_msg_debug_write_data_pg Register field name data value Description +#define rx_gcr_msg_debug_write_data_clear 0x0000 // Clear mask + +// rx_dyn_recal_pg Register field name data value Description +#define rx_dyn_recal_main_state_clear 0x00FF // Clear mask +#define rx_dyn_recal_hndshk_state_clear 0x7F80 // Clear mask + +// rx_wt_clk_status_pg Register field name data value Description +#define rx_wt_clk_lane_inverted 0x4000 //Clock Wiretest lane inverted/swapped status +#define rx_wt_clk_lane_inverted_clear 0xBFFF // Clear mask +#define rx_wt_clk_lane_bad_code_n_stuck_1 0x0800 //Clock Wiretest Lane Bad code N leg stuck at 1 +#define rx_wt_clk_lane_bad_code_n_stuck_0 0x1000 //Clock Wiretest Lane Bad code N leg stuck at 0 +#define rx_wt_clk_lane_bad_code_p_stuck_1 0x1800 //Clock Wiretest Lane Bad code P leg stuck at 1 +#define rx_wt_clk_lane_bad_code_p_stuck_0 0x2000 //Clock Wiretest Lane Bad code P leg stuck at 0 +#define rx_wt_clk_lane_bad_code_n_or_p_floating 0x2800 //Clock Wiretest Lane Bad code N or P leg floating or swapping undetermined +#define rx_wt_clk_lane_bad_code_NOT_USED_110 0x3000 //Clock Wiretest Lane Bad code Unused. +#define rx_wt_clk_lane_bad_code_NOT_USED_111 0x3800 //Clock Wiretest Lane Bad code Unused. +#define rx_wt_clk_lane_bad_code_clear 0xC7FF // Clear mask + +// rx_dyn_recal_config_pg Register field name data value Description +#define rx_dyn_recal_overall_timeout_sel_tap1 0x2000 //Dynamic Recalibration Overall Timeout Selects 436.73us - smallest value for normal operation +#define rx_dyn_recal_overall_timeout_sel_tap2 0x4000 //Dynamic Recalibration Overall Timeout Selects 873.46uS +#define rx_dyn_recal_overall_timeout_sel_tap3 0x6000 //Dynamic Recalibration Overall Timeout Selects 1.75mS +#define rx_dyn_recal_overall_timeout_sel_tap4 0x8000 //Dynamic Recalibration Overall Timeout Selects 3.49mS - Recal should be around 2mS +#define rx_dyn_recal_overall_timeout_sel_tap5 0xA000 //Dynamic Recalibration Overall Timeout Selects 13.97mS +#define rx_dyn_recal_overall_timeout_sel_tap6 0xC000 //Dynamic Recalibration Overall Timeout Selects 55.90mS - largest value for normal operation +#define rx_dyn_recal_overall_timeout_sel_tap7 0xE000 //Dynamic Recalibration Overall Timeout Selects Infinite- For debug purposes +#define rx_dyn_recal_overall_timeout_sel_clear 0x1FFF // Clear mask +#define rx_dyn_recal_suspend 0x1000 //Suspend Dynamic Recalibration; otherwise starts automatically after link training +#define rx_dyn_recal_suspend_clear 0xEFFF // Clear mask +#define rx_dyn_recal_latch_offset 0x0200 //RX Dynamic Recalibration latch offset adjustment enable (EDI only) +#define rx_dyn_recal_latch_offset_clear 0xFDFF // Clear mask +#define rx_dyn_recal_ctle 0x0100 //RX Dynamic Recalibration CTLE/Peakin enable (EDI only) +#define rx_dyn_recal_ctle_clear 0xFEFF // Clear mask +#define rx_dyn_recal_vga 0x0080 //RX Dynamic Recalibration VGA gain and offset adjust enable (EDI only) +#define rx_dyn_recal_vga_clear 0xFF7F // Clear mask +#define rx_dyn_recal_dfe_h1 0x0040 //RX Dynamic Recalibration DFE H1 adjust enable (EDI only) +#define rx_dyn_recal_dfe_h1_clear 0xFFBF // Clear mask +#define rx_dyn_recal_h1ap_tweak 0x0020 //RX Dynamic Recalibration H1/AN PR adjust enable (EDI only) +#define rx_dyn_recal_h1ap_tweak_clear 0xFFDF // Clear mask +#define rx_dyn_recal_ddc 0x0010 //RX Dynamic Recalibration Dynamic data centering enable (EDI only) +#define rx_dyn_recal_ddc_clear 0xFFEF // Clear mask +#define rx_dyn_recal_ber_test 0x0008 //RX Dynamic Recalibration Dynamic data centering enable (EDI only) +#define rx_dyn_recal_ber_test_clear 0xFFF7 // Clear mask +#define rx_dyn_recal_ber_test_timeout 0x0000 //RX Dynamic Recalibration Bit Error Rate test timeout (EDI only) +#define rx_dyn_recal_ber_test_timeout_clear 0xFFB8 // Clear mask + +// rx_servo_recal_gcrmsg_pg Register field name data value Description +#define rx_servo_recal_done_gcrmsg 0x8000 //GCR Message: RX Servo Done Calibrating Lane for Dynamic Recal +#define rx_servo_recal_done_gcrmsg_clear 0x7FFF // Clear mask + +// rx_dyn_recal_gcrmsg_pg Register field name data value Description +#define rx_dyn_recal_ip_gcrmsg 0x8000 //GCR Message: RX Dynamic Recalibration In Progress +#define rx_dyn_recal_ip_gcrmsg_clear 0x7FFF // Clear mask +#define rx_dyn_recal_failed_gcrmsg 0x4000 //GCR Message: RX Dynamic Recalibration Failed +#define rx_dyn_recal_failed_gcrmsg_clear 0xBFFF // Clear mask +#define rx_dyn_recal_ripple_gcrmsg 0x2000 //GCR Message: RX Dynamic Recalibration: Reached end of bus...ripple back down to the beginning +#define rx_dyn_recal_ripple_gcrmsg_clear 0xDFFF // Clear mask +#define rx_dyn_recal_timeout_gcrmsg 0x1000 //GCR Message: RX Dynamic Recalibration: Recal Handshake Timed Out +#define rx_dyn_recal_timeout_gcrmsg_clear 0xEFFF // Clear mask + +// rx_wiretest_pll_cntl_pg Register field name data value Description +#define rx_wt_cu_pll_pgood 0x8000 //RX cleanup PLL Enable +#define rx_wt_cu_pll_pgood_clear 0x7FFF // Clear mask +#define rx_wt_cu_pll_reset 0x4000 //RX cleanup PLL Enable Request +#define rx_wt_cu_pll_reset_clear 0xBFFF // Clear mask +#define rx_wt_cu_pll_pgooddly_50ns 0x0800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Nominal 50ns Reset per PLL Spec +#define rx_wt_cu_pll_pgooddly_100ns 0x1000 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Double Nominal 50ns Reset per PLL Spec +#define rx_wt_cu_pll_pgooddly_960ui 0x1800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Typical simulation delay exceeding TX PLL 40-refclk locking period +#define rx_wt_cu_pll_pgooddly_unused_100 0x2000 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Reserved +#define rx_wt_cu_pll_pgooddly_unused_101 0x2800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Reserved +#define rx_wt_cu_pll_pgooddly_MAX 0x3000 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. 1024 UI +#define rx_wt_cu_pll_pgooddly_disable 0x3800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Disable rx_wt_cu_pll_reset +#define rx_wt_cu_pll_pgooddly_clear 0xC7FF // Clear mask +#define rx_wt_cu_pll_lock 0x0400 //RX cleanup PLL Locked +#define rx_wt_cu_pll_lock_clear 0xFBFF // Clear mask + +// rx_eo_step_cntl_pg Register field name data value Description +#define rx_eo_enable_latch_offset_cal 0x8000 //RX eye optimization latch offset adjustment enable +#define rx_eo_enable_latch_offset_cal_clear 0x7FFF // Clear mask +#define rx_eo_enable_ctle_cal 0x4000 //RX eye optimization CTLE/Peakin enable +#define rx_eo_enable_ctle_cal_clear 0xBFFF // Clear mask +#define rx_eo_enable_vga_cal 0x2000 //RX eye optimization VGA gainand offset adjust enable +#define rx_eo_enable_vga_cal_clear 0xDFFF // Clear mask +#define rx_eo_enable_dfe_h1_cal 0x0800 //RX eye optimization DFE H1 adjust enable +#define rx_eo_enable_dfe_h1_cal_clear 0xF7FF // Clear mask +#define rx_eo_enable_h1ap_tweak 0x0400 //RX eye optimization H1/AN PR adjust enable +#define rx_eo_enable_h1ap_tweak_clear 0xFBFF // Clear mask +#define rx_eo_enable_ddc 0x0200 //RX eye optimization Dynamic data centering enable +#define rx_eo_enable_ddc_clear 0xFDFF // Clear mask +#define rx_eo_enable_final_l2u_adj 0x0080 //RX eye optimization Final RX FIFO load-to-unload delay adjustment enable +#define rx_eo_enable_final_l2u_adj_clear 0xFF7F // Clear mask + +// rx_eo_step_stat_pg Register field name data value Description +#define rx_eo_latch_offset_done 0x8000 //RX eye optimization latch offset adjustment done +#define rx_eo_latch_offset_done_clear 0x7FFF // Clear mask +#define rx_eo_ctle_done 0x4000 //RX eye optimization CTLE/Peaking done +#define rx_eo_ctle_done_clear 0xBFFF // Clear mask +#define rx_eo_vga_done 0x2000 //RX eye optimization VGA gain/offset adjust done +#define rx_eo_vga_done_clear 0xDFFF // Clear mask +#define rx_eo_dfe_h1_done 0x0800 //RX eye optimization DFE H1 adjust done +#define rx_eo_dfe_h1_done_clear 0xF7FF // Clear mask +#define rx_eo_h1ap_tweak_done 0x0400 //RX eye optimization H1/AN PR adjust done +#define rx_eo_h1ap_tweak_done_clear 0xFBFF // Clear mask +#define rx_eo_ddc_done 0x0200 //RX eye optimization Dynamic data centering done +#define rx_eo_ddc_done_clear 0xFDFF // Clear mask +#define rx_eo_final_l2u_adj_done 0x0080 //RX eye optimization Final RX FIFO load-to-unload adjust done +#define rx_eo_final_l2u_adj_done_clear 0xFF7F // Clear mask +#define rx_eo_dfe_flag 0x0040 //RX eye optimization DFE mode flag +#define rx_eo_dfe_flag_clear 0xFFBF // Clear mask + +// rx_eo_step_fail_pg Register field name data value Description +#define rx_eo_latch_offset_failed 0x8000 //RX eye optimization latch offset adjustment failed +#define rx_eo_latch_offset_failed_clear 0x7FFF // Clear mask +#define rx_eo_ctle_failed 0x4000 //RX eye optimization CTLE/Peaking failed +#define rx_eo_ctle_failed_clear 0xBFFF // Clear mask +#define rx_eo_vga_failed 0x2000 //RX eye optimization VGA gain/offset adjust failed +#define rx_eo_vga_failed_clear 0xDFFF // Clear mask +#define rx_eo_dfe_h1_failed 0x0800 //RX eye optimization DFE H1 adjust failed +#define rx_eo_dfe_h1_failed_clear 0xF7FF // Clear mask +#define rx_eo_h1ap_tweak_failed 0x0400 //RX eye optimization H1/AN PR adjust failed +#define rx_eo_h1ap_tweak_failed_clear 0xFBFF // Clear mask +#define rx_eo_ddc_failed 0x0200 //RX eye optimization Dynamic data centering failed +#define rx_eo_ddc_failed_clear 0xFDFF // Clear mask +#define rx_eo_final_l2u_adj_failed 0x0080 //RX eye optimization Final RX FIFO load-to-unload adjust failed +#define rx_eo_final_l2u_adj_failed_clear 0xFF7F // Clear mask + +// rx_ap_pg Register field name data value Description +#define rx_ap_even_work 0x0000 //RX Ap even working register +#define rx_ap_even_work_clear 0x00FF // Clear mask +#define rx_ap_odd_work 0x0000 //Rx Ap odd working register +#define rx_ap_odd_work_clear 0xFF00 // Clear mask + +// rx_an_pg Register field name data value Description +#define rx_an_even_work 0x0000 //RX An even working register +#define rx_an_even_work_clear 0x00FF // Clear mask +#define rx_an_odd_work 0x0000 //Rx An odd working register +#define rx_an_odd_work_clear 0xFF00 // Clear mask + +// rx_amin_pg Register field name data value Description +#define rx_amin_even_work 0x0000 //RX Amin even working register +#define rx_amin_even_work_clear 0x00FF // Clear mask +#define rx_amin_odd_work 0x0000 //Rx Amin odd working register +#define rx_amin_odd_work_clear 0xFF00 // Clear mask + +// rx_amax_pg Register field name data value Description +#define rx_amax_high 0x0000 //RX Amax high limit default 125 +#define rx_amax_high_clear 0x00FF // Clear mask +#define rx_amax_low 0x0000 //Rx Amax low limit default 75 +#define rx_amax_low_clear 0xFF00 // Clear mask + +// rx_amp_val_pg Register field name data value Description +#define rx_amp_peak_work 0x0000 //Rx amp peak working register +#define rx_amp_peak_work_clear 0x0FFF // Clear mask +#define rx_amp_gain_work 0x0000 //Rx Amp gain working register +#define rx_amp_gain_work_clear 0xF0FF // Clear mask +#define rx_amp_offset_work 0x0000 //Rx amp offset working register +#define rx_amp_offset_work_clear 0x3FC0 // Clear mask + +// rx_amp_offset_pg Register field name data value Description +#define rx_amp_offset_max 0x0000 //Rx amp maximum allowable offset +#define rx_amp_offset_max_clear 0x03FF // Clear mask +#define rx_amp_offset_min 0x0000 //Rx Amp minimum allowable offset +#define rx_amp_offset_min_clear 0xFC0F // Clear mask + +// rx_eo_convergence_pg Register field name data value Description +#define rx_eo_converged_count 0x0000 //RX eye optimization Convergence counter current value +#define rx_eo_converged_count_clear 0x0FFF // Clear mask +#define rx_eo_converged_end_count 0x0000 //RX eye optimization Covergence counter end value +#define rx_eo_converged_end_count_clear 0xF0FF // Clear mask + +// rx_sls_rcvy_pg Register field name data value Description +#define rx_sls_rcvy_state_clear 0xE0FF // Clear mask + +// rx_sls_rcvy_gcrmsg_pg Register field name data value Description +#define rx_slv_shdw_done_fin_gcrmsg 0x8000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_done +#define rx_slv_shdw_done_fin_gcrmsg_clear 0x7FFF // Clear mask +#define rx_slv_shdw_nop_fin_gcrmsg 0x4000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_shdw_nop_fin_gcrmsg_clear 0xBFFF // Clear mask +#define rx_slv_shdw_rpr_done_fin_gcrmsg 0x2000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_rpr_done +#define rx_slv_shdw_rpr_done_fin_gcrmsg_clear 0xDFFF // Clear mask +#define rx_slv_shdw_rpr_nop_fin_gcrmsg 0x1000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_shdw_rpr_nop_fin_gcrmsg_clear 0xEFFF // Clear mask +#define rx_slv_unshdw_done_fin_gcrmsg 0x0800 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_done +#define rx_slv_unshdw_done_fin_gcrmsg_clear 0xF7FF // Clear mask +#define rx_slv_unshdw_nop_fin_gcrmsg 0x0400 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_unshdw_nop_fin_gcrmsg_clear 0xFBFF // Clear mask +#define rx_slv_unshdw_rpr_done_fin_gcrmsg 0x0200 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_rpr_done +#define rx_slv_unshdw_rpr_done_fin_gcrmsg_clear 0xFDFF // Clear mask +#define rx_slv_unshdw_rpr_nop_fin_gcrmsg 0x0100 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_unshdw_rpr_nop_fin_gcrmsg_clear 0xFEFF // Clear mask +#define rx_slv_recal_done_nop_fin_gcrmsg 0x0080 //GCR Message: Slave Recal Done; Need to finish slave recal handshake starting with waiting for nop +#define rx_slv_recal_done_nop_fin_gcrmsg_clear 0xFF7F // Clear mask +#define rx_slv_recal_fail_nop_fin_gcrmsg 0x0040 //GCR Message: Slave Recal Fail; Need to finish slave recal handshake starting with waiting for nop +#define rx_slv_recal_fail_nop_fin_gcrmsg_clear 0xFFBF // Clear mask +#define rx_sls_rcvy_rx_ip_gcrmsg 0x0020 //GCR Message: SLS Rcvy; RX Lane Repair IP +#define rx_sls_rcvy_rx_ip_gcrmsg_clear 0xFFDF // Clear mask +#define rx_sls_rcvy_rx_rpred_gcrmsg 0x0010 //GCR Message: SLS Rcvy; RX Lane Repair Done +#define rx_sls_rcvy_rx_rpred_gcrmsg_clear 0xFFEF // Clear mask + +// rx_tx_lane_info_gcrmsg_pg Register field name data value Description +#define rx_tx_bad_lane_cntr_gcrmsg 0x0000 //GCR Message: RX Side TX Bad Lane Counter +#define rx_tx_bad_lane_cntr_gcrmsg_clear 0x3FFF // Clear mask + +// rx_err_tallying_gcrmsg_pg Register field name data value Description +#define rx_dis_synd_tallying_gcrmsg 0x8000 //GCR Message: Disable Syndrome Tallying +#define rx_dis_synd_tallying_gcrmsg_clear 0x7FFF // Clear mask + +// rx_trace_pg Register field name data value Description +#define rx_trc_mode_tap1 0x1000 //RX Trace Mode Dynamic Repair State Machines +#define rx_trc_mode_tap2 0x2000 //RX Trace Mode SLS Handshake State Machines with Recovery +#define rx_trc_mode_tap3 0x3000 //RX Trace Mode Dynamic Recal State Machines +#define rx_trc_mode_tap4 0x4000 //RX Trace Mode Recal Handshake State Machine with Recovery +#define rx_trc_mode_tap5 0x5000 //RX Trace Mode CRC/ECC Tallying Logic +#define rx_trc_mode_tap6 0x6000 //RX Trace Mode RX SLS Commands +#define rx_trc_mode_tap7 0x7000 //RX Trace Mode RX Bad Lanes +#define rx_trc_mode_tap8 0x8000 //RX Trace Mode RX SLS Lanes +#define rx_trc_mode_tap9 0x9000 //RX Trace Mode TBD +#define rx_trc_mode_tap10 0xA000 //RX Trace Mode TBD +#define rx_trc_mode_tap11 0xB000 //RX Trace Mode TBD +#define rx_trc_mode_tap12 0xC000 //RX Trace Mode TBD +#define rx_trc_mode_tap13 0xD000 //RX Trace Mode TBD +#define rx_trc_mode_tap14 0xE000 //RX Trace Mode TBD +#define rx_trc_mode_tap15 0xF000 //RX Trace Mode TBD +#define rx_trc_mode_clear 0x0FFF // Clear mask +#define rx_trc_grp_clear 0xFC0F // Clear mask + +// rx_wiretest_pp Register field name data value Description +#define rx_wt_pattern_length_256 0x4000 //RX Wiretest Pattern Length 256 +#define rx_wt_pattern_length_512 0x8000 //RX Wiretest Pattern Length 512 +#define rx_wt_pattern_length_1024 0xC000 //RX Wiretest Pattern Length 1024 +#define rx_wt_pattern_length_clear 0x3FFF // Clear mask + +// rx_mode_pp Register field name data value Description +#define rx_reduced_scramble_mode_disable_1 0x4000 //Sets reduced density of scramble pattern. Disable reduced density +#define rx_reduced_scramble_mode_enable_div2 0x8000 //Sets reduced density of scramble pattern. Enable Div2 Reduced Density +#define rx_reduced_scramble_mode_enable_div4 0xC000 //Sets reduced density of scramble pattern. Enable Div4 Reduced Density +#define rx_reduced_scramble_mode_clear 0x3FFF // Clear mask +#define rx_act_check_timeout_sel_128ui 0x0800 //Sets Activity check timeout value. 128 UI +#define rx_act_check_timeout_sel_256ui 0x1000 //Sets Activity check timeout value. 256 UI +#define rx_act_check_timeout_sel_512ui 0x1800 //Sets Activity check timeout value. 512 UI +#define rx_act_check_timeout_sel_1024ui 0x2000 //Sets Activity check timeout value. 1024 UI +#define rx_act_check_timeout_sel_2048ui 0x2800 //Sets Activity check timeout value. 2048 UI +#define rx_act_check_timeout_sel_4096ui 0x3000 //Sets Activity check timeout value. 4096 UI +#define rx_act_check_timeout_sel_infinite 0x3800 //Sets Activity check timeout value. Infinite +#define rx_act_check_timeout_sel_clear 0xC7FF // Clear mask +#define rx_block_lock_timeout_sel_1024ui 0x0100 //Sets block lock timeout value. 1024 UI +#define rx_block_lock_timeout_sel_2048ui 0x0200 //Sets block lock timeout value. 2048 UI +#define rx_block_lock_timeout_sel_4096ui 0x0300 //Sets block lock timeout value. 4096 UI +#define rx_block_lock_timeout_sel_8192ui 0x0400 //Sets block lock timeout value. 8192 UI +#define rx_block_lock_timeout_sel_16384ui 0x0500 //Sets block lock timeout value. 16384 UI +#define rx_block_lock_timeout_sel_32768ui 0x0600 //Sets block lock timeout value. 32768 UI +#define rx_block_lock_timeout_sel_infinite 0x0700 //Sets block lock timeout value. Infinite +#define rx_block_lock_timeout_sel_clear 0xF8FF // Clear mask +#define rx_bit_lock_timeout_sel_512ui 0x0020 //Sets bit lock/edge detect timeout value. 512 UI +#define rx_bit_lock_timeout_sel_1024ui 0x0040 //Sets bit lock/edge detect timeout value. 1024 UI +#define rx_bit_lock_timeout_sel_2048ui 0x0060 //Sets bit lock/edge detect timeout value. 2048 UI +#define rx_bit_lock_timeout_sel_4096ui 0x0080 //Sets bit lock/edge detect timeout value. 4096 UI +#define rx_bit_lock_timeout_sel_8192ui 0x00A0 //Sets bit lock/edge detect timeout value. 8192 UI +#define rx_bit_lock_timeout_sel_16384ui 0x00C0 //Sets bit lock/edge detect timeout value. 16384 UI +#define rx_bit_lock_timeout_sel_infinite 0x00E0 //Sets bit lock/edge detect timeout value. Infinite +#define rx_bit_lock_timeout_sel_clear 0x1F1F // Clear mask + +// rx_cntl_pp Register field name data value Description +#define rx_prbs_check_sync 0x4000 //Enables checking for the 12 ui scramble sync pattern. +#define rx_prbs_check_sync_clear 0xBFFF // Clear mask +#define rx_enable_reduced_scramble 0x2000 //Enables reduced density of scramble pattern. +#define rx_enable_reduced_scramble_clear 0xDFFF // Clear mask +#define rx_prbs_inc 0x1000 //Shift the PRBS pattern forward in time by one extra local cycle (4ui for EDI, 2ui for EI4). +#define rx_prbs_inc_clear 0xEFFF // Clear mask +#define rx_prbs_dec 0x0800 //Shift the PRBS pattern back in time by holding it one local cycle (4ui for EDI, 2ui for EI4). +#define rx_prbs_dec_clear 0xF7FF // Clear mask + +// rx_dyn_recal_timeouts_pp Register field name data value Description +#define rx_dyn_recal_interval_timeout_sel_tap1 0x1000 //RX Dynamic Recalibration Interval Timeout Selects 16kUI or 1.7us +#define rx_dyn_recal_interval_timeout_sel_tap2 0x2000 //RX Dynamic Recalibration Interval Timeout Selects 32kUI or 3.4us +#define rx_dyn_recal_interval_timeout_sel_tap3 0x3000 //RX Dynamic Recalibration Interval Timeout Selects 64kUI or 6.8us +#define rx_dyn_recal_interval_timeout_sel_tap4 0x4000 //RX Dynamic Recalibration Interval Timeout Selects 128kUI or 106.5ns +#define rx_dyn_recal_interval_timeout_sel_tap5 0x5000 //RX Dynamic Recalibration Interval Timeout Selects 256kUI or 1.7us +#define rx_dyn_recal_interval_timeout_sel_tap6 0x6000 //RX Dynamic Recalibration Interval Timeout Selects 8192kUI or 872.4us +#define rx_dyn_recal_interval_timeout_sel_tap7 0x7000 //RX Dynamic Recalibration Interval Timeout Selects infinite +#define rx_dyn_recal_interval_timeout_sel_clear 0x8FFF // Clear mask +#define rx_dyn_recal_status_rpt_timeout_sel_tap1 0x0400 //RX Dynamic Recalibration Status Reporting Timeout Selects 1024UI or 106.5ns +#define rx_dyn_recal_status_rpt_timeout_sel_tap2 0x0800 //RX Dynamic Recalibration Status Reporting Timeout Selects 2048UI or 212.9ns +#define rx_dyn_recal_status_rpt_timeout_sel_tap3 0x0C00 //RX Dynamic Recalibration Status Reporting Timeout Selects 4096UI or 426.0ns +#define rx_dyn_recal_status_rpt_timeout_sel_clear 0xF3FF // Clear mask + +// rx_servo_recal_gcrmsg_pp Register field name data value Description +#define rx_servo_recal_ip_gcrmsg 0x8000 //GCR Message: RX Servo Lane Calibration In Progress +#define rx_servo_recal_ip_gcrmsg_clear 0x7FFF // Clear mask + +// rx_ber_cntl_pp Register field name data value Description +#define rx_ber_en 0x8000 //Per-Pack (PP) Diagnostic Bit Error Rate (BER) error checking enable control. When 1 enables error checking. When 0 the error checking is disabled. This control enables the BER timer as well as enables the error checker and BER counters. The assumption is that the driver(s) are currently driving PRBS23 and the link has been trained before enabling BER checking. +#define rx_ber_en_clear 0x7FFF // Clear mask +#define rx_ber_count_clr 0x4000 //PP Diag BER error counter clear pulse. When written to a 1 the per-lane error counters are cleared to all zeroes. Writing both this bit and the timer clear bit to a 1 will clear both and allow a new set of measurements to be run. +#define rx_ber_count_clr_clear 0xBFFF // Clear mask +#define rx_ber_timer_clr 0x2000 //PP Diag BER timer clear pulse. When written to a 1 the per-pack timers are cleared to all zeroes. Writing both this bit and the error counter clear bit to a 1 will clear both and allow a new set of measurements to be run. +#define rx_ber_timer_clr_clear 0xDFFF // Clear mask + +// rx_ber_mode_pp Register field name data value Description +#define rx_ber_timer_freeze_en 0x8000 //Per-Pack (PP) Diagnostic Bit Error Rate (BER) Timer freeze enable. When set to a 1 the per-pack timer is frozen when any lane error count saturates in that pack. +#define rx_ber_timer_freeze_en_clear 0x7FFF // Clear mask +#define rx_ber_count_freeze_en 0x4000 //PP Diag BER Lane Error Counter freeze enable. When set to a 1 the per-lane error counters are frozen when the timer saturates in that pack. +#define rx_ber_count_freeze_en_clear 0xBFFF // Clear mask +#define rx_ber_count_sel_2 0x0400 //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event. 2 +#define rx_ber_count_sel_4 0x0800 //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event. 4 +#define rx_ber_count_sel_8 0x0C00 //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event. 8 +#define rx_ber_count_sel_16 0x1000 //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event. 16 +#define rx_ber_count_sel_32 0x1400 //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event. 32 +#define rx_ber_count_sel_64 0x1800 //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event. 64 +#define rx_ber_count_sel_128 0x1C00 //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event. 128 +#define rx_ber_count_sel_clear 0xE3FF // Clear mask +#define rx_ber_timer_sel_2tothe36th 0x0080 //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event. 2^36 +#define rx_ber_timer_sel_2tothe32nd 0x0100 //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event. 2^32 +#define rx_ber_timer_sel_2tothe28th 0x0180 //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event. 2^28 +#define rx_ber_timer_sel_2tothe24th 0x0200 //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event. 2^24 +#define rx_ber_timer_sel_2tothe20th 0x0280 //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event. 2^20 +#define rx_ber_timer_sel_2tothe16th 0x0300 //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event. 2^16 +#define rx_ber_timer_sel_2tothe12th 0x0380 //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event. 2^12 +#define rx_ber_timer_sel_clear 0xFC7F // Clear mask +#define rx_ber_clr_count_on_read_en 0x0040 //PP Diag BER Lane Error Counter clear on read. When set to a 1 this enables the clearing of a lanes error counter when it is read. +#define rx_ber_clr_count_on_read_en_clear 0xFFBF // Clear mask +#define rx_ber_clr_timer_on_read_en 0x0020 //PP Diag BER Timer clear on read. When set to a 1 this enables the clearing of a lanes per-pack timer when it is read from any lane in the pack. +#define rx_ber_clr_timer_on_read_en_clear 0xFFDF // Clear mask + +// rx_servo_to1_pp Register field name data value Description +#define rx_servo_timeout_sel_A_512ui 0x1000 //RX servo operation timeout A. 512 UI +#define rx_servo_timeout_sel_A_1Kui 0x2000 //RX servo operation timeout A. 1K UI +#define rx_servo_timeout_sel_A_2Kui 0x3000 //RX servo operation timeout A. 2K UI +#define rx_servo_timeout_sel_A_4Kui 0x4000 //RX servo operation timeout A. 4096 UI +#define rx_servo_timeout_sel_A_8Kui 0x5000 //RX servo operation timeout A. 8K UI +#define rx_servo_timeout_sel_A_16Kui 0x6000 //RX servo operation timeout A. 16K UI +#define rx_servo_timeout_sel_A_32Kui 0x7000 //RX servo operation timeout A. 32K UI +#define rx_servo_timeout_sel_A_64Kui 0x8000 //RX servo operation timeout A. 64K UI +#define rx_servo_timeout_sel_A_128Kui 0x9000 //RX servo operation timeout A. 128K UI +#define rx_servo_timeout_sel_A_256Kui 0xA000 //RX servo operation timeout A. 256K UI +#define rx_servo_timeout_sel_A_512Kui 0xB000 //RX servo operation timeout A. 512K UI +#define rx_servo_timeout_sel_A_1Mui 0xC000 //RX servo operation timeout A. 1M UI +#define rx_servo_timeout_sel_A_2Mui 0xD000 //RX servo operation timeout A. 2M UI +#define rx_servo_timeout_sel_A_4Mui 0xE000 //RX servo operation timeout A. 4M UI +#define rx_servo_timeout_sel_A_Infinite 0xF000 //RX servo operation timeout A. Infinite +#define rx_servo_timeout_sel_A_clear 0x0FFF // Clear mask +#define rx_servo_timeout_sel_B_512ui 0x0100 //RX servo operation timeout B. 512 UI +#define rx_servo_timeout_sel_B_1Kui 0x0200 //RX servo operation timeout B. 1K UI +#define rx_servo_timeout_sel_B_2Kui 0x0300 //RX servo operation timeout B. 2K UI +#define rx_servo_timeout_sel_B_4Kui 0x0400 //RX servo operation timeout B. 4096 UI +#define rx_servo_timeout_sel_B_8Kui 0x0500 //RX servo operation timeout B. 8K UI +#define rx_servo_timeout_sel_B_16Kui 0x0600 //RX servo operation timeout B. 16K UI +#define rx_servo_timeout_sel_B_32Kui 0x0700 //RX servo operation timeout B. 32K UI +#define rx_servo_timeout_sel_B_64Kui 0x0800 //RX servo operation timeout B. 64K UI +#define rx_servo_timeout_sel_B_128Kui 0x0900 //RX servo operation timeout B. 128K UI +#define rx_servo_timeout_sel_B_256Kui 0x0A00 //RX servo operation timeout B. 256K UI +#define rx_servo_timeout_sel_B_512Kui 0x0B00 //RX servo operation timeout B. 512K UI +#define rx_servo_timeout_sel_B_1Mui 0x0C00 //RX servo operation timeout B. 1M UI +#define rx_servo_timeout_sel_B_2Mui 0x0D00 //RX servo operation timeout B. 2M UI +#define rx_servo_timeout_sel_B_4Mui 0x0E00 //RX servo operation timeout B. 4M UI +#define rx_servo_timeout_sel_B_Infinite 0x0F00 //RX servo operation timeout B. Infinite +#define rx_servo_timeout_sel_B_clear 0xF0FF // Clear mask +#define rx_servo_timeout_sel_C_512ui 0x0010 //RX servo operation timeout C. 512 UI +#define rx_servo_timeout_sel_C_1Kui 0x0020 //RX servo operation timeout C. 1K UI +#define rx_servo_timeout_sel_C_2Kui 0x0030 //RX servo operation timeout C. 2K UI +#define rx_servo_timeout_sel_C_4Kui 0x0040 //RX servo operation timeout C. 4096 UI +#define rx_servo_timeout_sel_C_8Kui 0x0050 //RX servo operation timeout C. 8K UI +#define rx_servo_timeout_sel_C_16Kui 0x0060 //RX servo operation timeout C. 16K UI +#define rx_servo_timeout_sel_C_32Kui 0x0070 //RX servo operation timeout C. 32K UI +#define rx_servo_timeout_sel_C_64Kui 0x0080 //RX servo operation timeout C. 64K UI +#define rx_servo_timeout_sel_C_128Kui 0x0090 //RX servo operation timeout C. 128K UI +#define rx_servo_timeout_sel_C_256Kui 0x00A0 //RX servo operation timeout C. 256K UI +#define rx_servo_timeout_sel_C_512Kui 0x00B0 //RX servo operation timeout C. 512K UI +#define rx_servo_timeout_sel_C_1Mui 0x00C0 //RX servo operation timeout C. 1M UI +#define rx_servo_timeout_sel_C_2Mui 0x00D0 //RX servo operation timeout C. 2M UI +#define rx_servo_timeout_sel_C_4Mui 0x00E0 //RX servo operation timeout C. 4M UI +#define rx_servo_timeout_sel_C_Infinite 0x00F0 //RX servo operation timeout C. Infinite +#define rx_servo_timeout_sel_C_clear 0x0F0F // Clear mask +#define rx_servo_timeout_sel_D_512ui 0x0001 //RX servo operation timeout D. 512 UI +#define rx_servo_timeout_sel_D_1Kui 0x0002 //RX servo operation timeout D. 1K UI +#define rx_servo_timeout_sel_D_2Kui 0x0003 //RX servo operation timeout D. 2K UI +#define rx_servo_timeout_sel_D_4Kui 0x0004 //RX servo operation timeout D. 4096 UI +#define rx_servo_timeout_sel_D_8Kui 0x0005 //RX servo operation timeout D. 8K UI +#define rx_servo_timeout_sel_D_16Kui 0x0006 //RX servo operation timeout D. 16K UI +#define rx_servo_timeout_sel_D_32Kui 0x0007 //RX servo operation timeout D. 32K UI +#define rx_servo_timeout_sel_D_64Kui 0x0008 //RX servo operation timeout D. 64K UI +#define rx_servo_timeout_sel_D_128Kui 0x0009 //RX servo operation timeout D. 128K UI +#define rx_servo_timeout_sel_D_256Kui 0x000A //RX servo operation timeout D. 256K UI +#define rx_servo_timeout_sel_D_512Kui 0x000B //RX servo operation timeout D. 512K UI +#define rx_servo_timeout_sel_D_1Mui 0x000C //RX servo operation timeout D. 1M UI +#define rx_servo_timeout_sel_D_2Mui 0x000D //RX servo operation timeout D. 2M UI +#define rx_servo_timeout_sel_D_4Mui 0x000E //RX servo operation timeout D. 4M UI +#define rx_servo_timeout_sel_D_Infinite 0x000F //RX servo operation timeout D. Infinite +#define rx_servo_timeout_sel_D_clear 0xFF00 // Clear mask + +// rx_servo_to2_pp Register field name data value Description +#define rx_servo_timeout_sel_E_512ui 0x1000 //RX servo operation timeout E. 512 UI +#define rx_servo_timeout_sel_E_1Kui 0x2000 //RX servo operation timeout E. 1K UI +#define rx_servo_timeout_sel_E_2Kui 0x3000 //RX servo operation timeout E. 2K UI +#define rx_servo_timeout_sel_E_4Kui 0x4000 //RX servo operation timeout E. 4096 UI +#define rx_servo_timeout_sel_E_8Kui 0x5000 //RX servo operation timeout E. 8K UI +#define rx_servo_timeout_sel_E_16Kui 0x6000 //RX servo operation timeout E. 16K UI +#define rx_servo_timeout_sel_E_32Kui 0x7000 //RX servo operation timeout E. 32K UI +#define rx_servo_timeout_sel_E_64Kui 0x8000 //RX servo operation timeout E. 64K UI +#define rx_servo_timeout_sel_E_128Kui 0x9000 //RX servo operation timeout E. 128K UI +#define rx_servo_timeout_sel_E_256Kui 0xA000 //RX servo operation timeout E. 256K UI +#define rx_servo_timeout_sel_E_512Kui 0xB000 //RX servo operation timeout E. 512K UI +#define rx_servo_timeout_sel_E_1Mui 0xC000 //RX servo operation timeout E. 1M UI +#define rx_servo_timeout_sel_E_2Mui 0xD000 //RX servo operation timeout E. 2M UI +#define rx_servo_timeout_sel_E_4Mui 0xE000 //RX servo operation timeout E. 4M UI +#define rx_servo_timeout_sel_E_Infinite 0xF000 //RX servo operation timeout E. Infinite +#define rx_servo_timeout_sel_E_clear 0x0FFF // Clear mask +#define rx_servo_timeout_sel_F_512ui 0x0100 //RX servo operation timeout F. 512 UI +#define rx_servo_timeout_sel_F_1Kui 0x0200 //RX servo operation timeout F. 1K UI +#define rx_servo_timeout_sel_F_2Kui 0x0300 //RX servo operation timeout F. 2K UI +#define rx_servo_timeout_sel_F_4Kui 0x0400 //RX servo operation timeout F. 4096 UI +#define rx_servo_timeout_sel_F_8Kui 0x0500 //RX servo operation timeout F. 8K UI +#define rx_servo_timeout_sel_F_16Kui 0x0600 //RX servo operation timeout F. 16K UI +#define rx_servo_timeout_sel_F_32Kui 0x0700 //RX servo operation timeout F. 32K UI +#define rx_servo_timeout_sel_F_64Kui 0x0800 //RX servo operation timeout F. 64K UI +#define rx_servo_timeout_sel_F_128Kui 0x0900 //RX servo operation timeout F. 128K UI +#define rx_servo_timeout_sel_F_256Kui 0x0A00 //RX servo operation timeout F. 256K UI +#define rx_servo_timeout_sel_F_512Kui 0x0B00 //RX servo operation timeout F. 512K UI +#define rx_servo_timeout_sel_F_1Mui 0x0C00 //RX servo operation timeout F. 1M UI +#define rx_servo_timeout_sel_F_2Mui 0x0D00 //RX servo operation timeout F. 2M UI +#define rx_servo_timeout_sel_F_4Mui 0x0E00 //RX servo operation timeout F. 4M UI +#define rx_servo_timeout_sel_F_Infinite 0x0F00 //RX servo operation timeout F. Infinite +#define rx_servo_timeout_sel_F_clear 0xF0FF // Clear mask +#define rx_servo_timeout_sel_G_512ui 0x0010 //RX servo operation timeout G. 512 UI +#define rx_servo_timeout_sel_G_1Kui 0x0020 //RX servo operation timeout G. 1K UI +#define rx_servo_timeout_sel_G_2Kui 0x0030 //RX servo operation timeout G. 2K UI +#define rx_servo_timeout_sel_G_4Kui 0x0040 //RX servo operation timeout G. 4096 UI +#define rx_servo_timeout_sel_G_8Kui 0x0050 //RX servo operation timeout G. 8K UI +#define rx_servo_timeout_sel_G_16Kui 0x0060 //RX servo operation timeout G. 16K UI +#define rx_servo_timeout_sel_G_32Kui 0x0070 //RX servo operation timeout G. 32K UI +#define rx_servo_timeout_sel_G_64Kui 0x0080 //RX servo operation timeout G. 64K UI +#define rx_servo_timeout_sel_G_128Kui 0x0090 //RX servo operation timeout G. 128K UI +#define rx_servo_timeout_sel_G_256Kui 0x00A0 //RX servo operation timeout G. 256K UI +#define rx_servo_timeout_sel_G_512Kui 0x00B0 //RX servo operation timeout G. 512K UI +#define rx_servo_timeout_sel_G_1Mui 0x00C0 //RX servo operation timeout G. 1M UI +#define rx_servo_timeout_sel_G_2Mui 0x00D0 //RX servo operation timeout G. 2M UI +#define rx_servo_timeout_sel_G_4Mui 0x00E0 //RX servo operation timeout G. 4M UI +#define rx_servo_timeout_sel_G_Infinite 0x00F0 //RX servo operation timeout G. Infinite +#define rx_servo_timeout_sel_G_clear 0x0F0F // Clear mask +#define rx_servo_timeout_sel_H_512ui 0x0001 //RX servo operation timeout H. 512 UI +#define rx_servo_timeout_sel_H_1Kui 0x0002 //RX servo operation timeout H. 1K UI +#define rx_servo_timeout_sel_H_2Kui 0x0003 //RX servo operation timeout H. 2K UI +#define rx_servo_timeout_sel_H_4Kui 0x0004 //RX servo operation timeout H. 4096 UI +#define rx_servo_timeout_sel_H_8Kui 0x0005 //RX servo operation timeout H. 8K UI +#define rx_servo_timeout_sel_H_16Kui 0x0006 //RX servo operation timeout H. 16K UI +#define rx_servo_timeout_sel_H_32Kui 0x0007 //RX servo operation timeout H. 32K UI +#define rx_servo_timeout_sel_H_64Kui 0x0008 //RX servo operation timeout H. 64K UI +#define rx_servo_timeout_sel_H_128Kui 0x0009 //RX servo operation timeout H. 128K UI +#define rx_servo_timeout_sel_H_256Kui 0x000A //RX servo operation timeout H. 256K UI +#define rx_servo_timeout_sel_H_512Kui 0x000B //RX servo operation timeout H. 512K UI +#define rx_servo_timeout_sel_H_1Mui 0x000C //RX servo operation timeout H. 1M UI +#define rx_servo_timeout_sel_H_2Mui 0x000D //RX servo operation timeout H. 2M UI +#define rx_servo_timeout_sel_H_4Mui 0x000E //RX servo operation timeout H. 4M UI +#define rx_servo_timeout_sel_H_Infinite 0x000F //RX servo operation timeout H. Infinite +#define rx_servo_timeout_sel_H_clear 0xFF00 // Clear mask + +// rx_servo_to3_pp Register field name data value Description +#define rx_servo_timeout_sel_I_512ui 0x1000 //RX servo operation timeout I. 512 UI +#define rx_servo_timeout_sel_I_1Kui 0x2000 //RX servo operation timeout I. 1K UI +#define rx_servo_timeout_sel_I_2Kui 0x3000 //RX servo operation timeout I. 2K UI +#define rx_servo_timeout_sel_I_4Kui 0x4000 //RX servo operation timeout I. 4096 UI +#define rx_servo_timeout_sel_I_8Kui 0x5000 //RX servo operation timeout I. 8K UI +#define rx_servo_timeout_sel_I_16Kui 0x6000 //RX servo operation timeout I. 16K UI +#define rx_servo_timeout_sel_I_32Kui 0x7000 //RX servo operation timeout I. 32K UI +#define rx_servo_timeout_sel_I_64Kui 0x8000 //RX servo operation timeout I. 64K UI +#define rx_servo_timeout_sel_I_128Kui 0x9000 //RX servo operation timeout I. 128K UI +#define rx_servo_timeout_sel_I_256Kui 0xA000 //RX servo operation timeout I. 256K UI +#define rx_servo_timeout_sel_I_512Kui 0xB000 //RX servo operation timeout I. 512K UI +#define rx_servo_timeout_sel_I_1Mui 0xC000 //RX servo operation timeout I. 1M UI +#define rx_servo_timeout_sel_I_2Mui 0xD000 //RX servo operation timeout I. 2M UI +#define rx_servo_timeout_sel_I_4Mui 0xE000 //RX servo operation timeout I. 4M UI +#define rx_servo_timeout_sel_I_Infinite 0xF000 //RX servo operation timeout I. Infinite +#define rx_servo_timeout_sel_I_clear 0x0FFF // Clear mask +#define rx_servo_timeout_sel_J_512ui 0x0100 //RX servo operation timeout J. 512 UI +#define rx_servo_timeout_sel_J_1Kui 0x0200 //RX servo operation timeout J. 1K UI +#define rx_servo_timeout_sel_J_2Kui 0x0300 //RX servo operation timeout J. 2K UI +#define rx_servo_timeout_sel_J_4Kui 0x0400 //RX servo operation timeout J. 4096 UI +#define rx_servo_timeout_sel_J_8Kui 0x0500 //RX servo operation timeout J. 8K UI +#define rx_servo_timeout_sel_J_16Kui 0x0600 //RX servo operation timeout J. 16K UI +#define rx_servo_timeout_sel_J_32Kui 0x0700 //RX servo operation timeout J. 32K UI +#define rx_servo_timeout_sel_J_64Kui 0x0800 //RX servo operation timeout J. 64K UI +#define rx_servo_timeout_sel_J_128Kui 0x0900 //RX servo operation timeout J. 128K UI +#define rx_servo_timeout_sel_J_256Kui 0x0A00 //RX servo operation timeout J. 256K UI +#define rx_servo_timeout_sel_J_512Kui 0x0B00 //RX servo operation timeout J. 512K UI +#define rx_servo_timeout_sel_J_1Mui 0x0C00 //RX servo operation timeout J. 1M UI +#define rx_servo_timeout_sel_J_2Mui 0x0D00 //RX servo operation timeout J. 2M UI +#define rx_servo_timeout_sel_J_4Mui 0x0E00 //RX servo operation timeout J. 4M UI +#define rx_servo_timeout_sel_J_Infinite 0x0F00 //RX servo operation timeout J. Infinite +#define rx_servo_timeout_sel_J_clear 0xF0FF // Clear mask +#define rx_servo_timeout_sel_K_512ui 0x0010 //RX servo operation timeout K. 512 UI +#define rx_servo_timeout_sel_K_1Kui 0x0020 //RX servo operation timeout K. 1K UI +#define rx_servo_timeout_sel_K_2Kui 0x0030 //RX servo operation timeout K. 2K UI +#define rx_servo_timeout_sel_K_4Kui 0x0040 //RX servo operation timeout K. 4096 UI +#define rx_servo_timeout_sel_K_8Kui 0x0050 //RX servo operation timeout K. 8K UI +#define rx_servo_timeout_sel_K_16Kui 0x0060 //RX servo operation timeout K. 16K UI +#define rx_servo_timeout_sel_K_32Kui 0x0070 //RX servo operation timeout K. 32K UI +#define rx_servo_timeout_sel_K_64Kui 0x0080 //RX servo operation timeout K. 64K UI +#define rx_servo_timeout_sel_K_128Kui 0x0090 //RX servo operation timeout K. 128K UI +#define rx_servo_timeout_sel_K_256Kui 0x00A0 //RX servo operation timeout K. 256K UI +#define rx_servo_timeout_sel_K_512Kui 0x00B0 //RX servo operation timeout K. 512K UI +#define rx_servo_timeout_sel_K_1Mui 0x00C0 //RX servo operation timeout K. 1M UI +#define rx_servo_timeout_sel_K_2Mui 0x00D0 //RX servo operation timeout K. 2M UI +#define rx_servo_timeout_sel_K_4Mui 0x00E0 //RX servo operation timeout K. 4M UI +#define rx_servo_timeout_sel_K_Infinite 0x00F0 //RX servo operation timeout K. Infinite +#define rx_servo_timeout_sel_K_clear 0x0F0F // Clear mask +#define rx_servo_timeout_sel_L_512ui 0x0001 //RX servo operation timeout L. 512 UI +#define rx_servo_timeout_sel_L_1Kui 0x0002 //RX servo operation timeout L. 1K UI +#define rx_servo_timeout_sel_L_2Kui 0x0003 //RX servo operation timeout L. 2K UI +#define rx_servo_timeout_sel_L_4Kui 0x0004 //RX servo operation timeout L. 4096 UI +#define rx_servo_timeout_sel_L_8Kui 0x0005 //RX servo operation timeout L. 8K UI +#define rx_servo_timeout_sel_L_16Kui 0x0006 //RX servo operation timeout L. 16K UI +#define rx_servo_timeout_sel_L_32Kui 0x0007 //RX servo operation timeout L. 32K UI +#define rx_servo_timeout_sel_L_64Kui 0x0008 //RX servo operation timeout L. 64K UI +#define rx_servo_timeout_sel_L_128Kui 0x0009 //RX servo operation timeout L. 128K UI +#define rx_servo_timeout_sel_L_256Kui 0x000A //RX servo operation timeout L. 256K UI +#define rx_servo_timeout_sel_L_512Kui 0x000B //RX servo operation timeout L. 512K UI +#define rx_servo_timeout_sel_L_1Mui 0x000C //RX servo operation timeout L. 1M UI +#define rx_servo_timeout_sel_L_2Mui 0x000D //RX servo operation timeout L. 2M UI +#define rx_servo_timeout_sel_L_4Mui 0x000E //RX servo operation timeout L. 4M UI +#define rx_servo_timeout_sel_L_Infinite 0x000F //RX servo operation timeout L. Infinite +#define rx_servo_timeout_sel_L_clear 0xFF00 // Clear mask + +// rx_dfe_config_pp Register field name data value Description +#define rx_peak_cfg 0x0000 //RX DFE Peaking settings +#define rx_peak_cfg_clear 0x3FFF // Clear mask +#define rx_amin_cfg 0x0000 //RX DFE Amin settings +#define rx_amin_cfg_clear 0xC7FF // Clear mask +#define rx_anap_cfg 0x0000 //RX DFE An-Ap settings +#define rx_anap_cfg_clear 0xF9FF // Clear mask +#define rx_h1_cfg 0x0000 //RX DFE H1 settings +#define rx_h1_cfg_clear 0xFE7F // Clear mask +#define rx_h1ap_cfg 0x0000 //RX DFE H1 over Ap settings +#define rx_h1ap_cfg_clear 0x3F8F // Clear mask +#define rx_dfe_ca_cfg 0x0000 //RX DFE clock adjust settings +#define rx_dfe_ca_cfg_clear 0xF8F3 // Clear mask +#define rx_spmux_cfg 0x0000 //RX DFE speculation mux toggle settings +#define rx_spmux_cfg_clear 0xE3CC // Clear mask + +// rx_dfe_timers_pp Register field name data value Description +#define rx_init_tmr_cfg 0x0000 //RX clock init timer settings +#define rx_init_tmr_cfg_clear 0x1FFF // Clear mask +#define rx_ber_cfg 0x0000 //RX DDC Bit error rate timer settings +#define rx_ber_cfg_clear 0xE3FF // Clear mask +#define rx_fifo_dly_cfg 0x0000 //RX Fifo Delay Blackout settings +#define rx_fifo_dly_cfg_clear 0xFCFF // Clear mask +#define rx_ddc_cfg 0x0000 //RX DDC config settings +#define rx_ddc_cfg_clear 0xFF3F // Clear mask +#define rx_dac_bo_cfg 0x0000 //RX DAC black out period settings +#define rx_dac_bo_cfg_clear 0xCFC7 // Clear mask +#define rx_prot_cfg 0x0000 //RX phase rotator filter settings +#define rx_prot_cfg_clear 0x7E39 // Clear mask + +// rx_reset_cfg_pp Register field name data value Description +#define rx_reset_cfg_hld_clear 0x0000 // Clear mask + + +#endif
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/gcr_funcs.C b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/gcr_funcs.C new file mode 100644 index 000000000..cd43cbe81 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/gcr_funcs.C @@ -0,0 +1,247 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_io_run_training/gcr_funcs.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 1997, 1998
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME : gcr_funcs.C
+// *! TITLE :
+// *! DESCRIPTION :
+// *! CONTEXT :
+// *!
+// *! OWNER NAME : Varghese, Varkey Email: varkeykv@in.ibm.com
+// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date: | Comment:
+// --------|--------|--------|--------------------------------------------------
+// 1.0 |varkeykv|01/19/12| Initial check in to solve hostboot linker
+//------------------------------------------------------------------------------
+#include "gcr_funcs.H"
+using namespace fapi;
+ReturnCode GCR_read(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase &databuf_16bit)
+{
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase set_bits(16), clear_bits(16);
+ rc_ecmd|=set_bits.flushTo0();
+ rc_ecmd|=clear_bits.flushTo1();
+
+ if(rc_ecmd){
+ FAPI_ERR("Unexpected error in buffer manipulation\n");
+ rc=rc_ecmd;
+ }
+ else{
+ rc=doGCRop(chip_target, interface, gcr_op_read, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit);
+ if(!rc.ok())
+ {
+ FAPI_ERR("Unexpected error while performing GCR OP \n");
+ }
+ }
+
+ return rc;
+}
+//------------------------------------------------------------------------------------------------------------------------------------
+// GCR SCOM WRITE - main api for write - do not use doGCRop directly
+//------------------------------------------------------------------------------------------------------------------------------------
+ReturnCode GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, int skipCheck)
+{
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase databuf_16bit(16);
+ rc_ecmd|=databuf_16bit.flushTo0();
+ if(rc_ecmd){
+ FAPI_ERR("Unexpected error in buffer manipulation\n");
+ rc=rc_ecmd;
+ }
+ else{
+ rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck);
+ if(!rc.ok())
+ {
+ FAPI_ERR("Unexpected error while performing GCR OP \n");
+ }
+ }
+ return rc;
+}
+
+// UPPER LAYER FUNCTIONS
+
+//------------------------------------------------------------------------------------------------------------------------------------
+// generate the 64 bit scom address for the GCR
+//------------------------------------------------------------------------------------------------------------------------------------
+uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) {
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase reg_scom_address(64), temp(64);
+ temp.flushTo0();
+ temp.setDoubleWord(0,gcr_data);
+
+ // 64 bit address
+ rc_ecmd|= reg_scom_address.setWord(0,temp.getWord(0));
+ rc_ecmd |= reg_scom_address.setWord(1,gcr_addr);
+ rc_ecmd |= reg_scom_address.setBit(0);
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("io_run_training: Unexpected failure in scom_address_64bit helper func");
+ }
+ return(reg_scom_address.getDoubleWord(0));
+}
+
+
+// use GCR_read and GCR_write for reg access - not this function!!!!
+/*************************************************************************************************************************/
+/* gcr2 is pgp mailbox format */
+/* gcr2 0 0 64 # total length */
+/* gcr2 wr 0 1 # gcr register read/write bit (read=1, write=0, opposite of gcr0) */
+/* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */
+/* gcr2 rxtx 21 1 # =1 for a tx group */
+/* gcr2 group 22 5 # does NOT include tx/rx as leading bit */
+/* gcr2 lane 27 5 # lane address */
+/* gcr2 data 48 16 # data */
+/* gcr2 readvalid 39 1 # read data valid bit */
+/*************************************************************************************************************************/
+
+ReturnCode doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck) {
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ uint64_t scom_address64=0;
+ ecmdDataBufferBase getscom_data64(64), putscom_data64(64), local_data16(16);
+ rc_ecmd |=getscom_data64.flushTo0();
+ rc_ecmd |=putscom_data64.flushTo0();
+ rc_ecmd |=local_data16.flushTo0();
+
+ // Generate the gcr2_register_data putscom data
+ /* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */
+ // align the extended address to bit (12:20)
+ rc_ecmd |= getscom_data64.insert( GCR_sub_reg_ext_addr[target_io_reg], 12, 9, 23 );
+ /* gcr2 group 22 5 # does NOT include tx/rx as leading bit */
+ // align the group address to bit (22:26)
+ rc_ecmd |= getscom_data64.insert( group_address, 22, 5, 27); // does not include leading TX bit now since we are using only RX
+
+ /* gcr2 lane 27 5 # lane address */
+ // align the lane address to bit (27:31)
+ rc_ecmd |= getscom_data64.insert( lane_address, 27, 5, 27 );
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
+ rc=rc_ecmd;
+ }
+ else
+ {
+ FAPI_DBG("ei_reg_addr_GCR_scom[interface]=%x\n",ei_reg_addr_GCR_scom[interface]);
+ scom_address64 =scom_address_64bit(ei_reg_addr_GCR_scom[interface], getscom_data64.getDoubleWord(0));
+ rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );
+ if(!rc.ok())
+ {
+ FAPI_ERR("IO gcr_funcs:GETSCOM error occurred ********\n");
+ FAPI_ERR( "IO GCR FUNCS \tRead GCR %s, @ = %X, Data = %X Failed group_address=%d\n",
+ GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1),group_address);
+ }
+ else
+ {
+ FAPI_DBG( "\tRead GCR2 %s: GETSCOM 0x%X %X \n",
+ GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1) );
+ rc_ecmd|=getscom_data64.extract( local_data16, 48, 16 ); // return data on read ops -- for 54/52 onwards
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
+ rc=rc_ecmd;
+ }
+ else
+ {
+ // register write operation
+ if (read_or_write == gcr_op_read) {
+ databuf_16bit = local_data16;
+ }
+ else
+ { // write
+ // write operation
+ putscom_data64 = getscom_data64;
+
+ // clear the desired bits first
+ databuf_16bit = databuf_16bit & clear_bits;
+
+ // now set desired bits
+ databuf_16bit = databuf_16bit | set_bits;
+
+ // data is now 64 bits and only last 16 bits are used 48:63 = 16bits # data
+ rc_ecmd|=putscom_data64.insert( databuf_16bit, 48, 16); //-- for model 54/52 onwards
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred");
+ rc=rc_ecmd;
+ }
+ else
+ {
+ FAPI_DBG( "\tWrite GCR2 %s: PUTSCOM 0x%X 0x%X",
+ GCR_sub_reg_names[target_io_reg], scom_address64, putscom_data64.getWord(0), putscom_data64.getWord(1) );
+ rc = fapiPutScom( chip_target, scom_address64, putscom_data64);
+ if(!rc.ok())
+ {
+ FAPI_ERR("IO gcr_funcs: PUTSCOM error occurred\n");
+ }
+ else
+ {
+ // check the write
+ rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );
+ if(!rc.ok()){
+ FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n");
+ return(rc);
+ }
+ rc_ecmd=local_data16.insert(getscom_data64,0,16,48); //-- for 54/52 onwards
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
+ rc=rc_ecmd;
+ }
+ else{
+ if ( !skipCheck )
+ { //add skipCheck for tx_err_inj since self resetting -- djd 2/11/11
+ if ( local_data16 != databuf_16bit )
+ {
+ FAPI_ERR( "\t %s VALIDATE write failed: read=0x%04X write=%04X\n",
+ GCR_sub_reg_names[target_io_reg], local_data16.getHalfWord(0), databuf_16bit.getHalfWord(0) );
+ ecmdDataBufferBase &READ_BUF=local_data16;
+ ecmdDataBufferBase &WRITE_BUF=databuf_16bit;
+ FAPI_SET_HWP_ERROR(rc, IO_GCR_WRITE_MISMATCH_RC);
+ }
+ }
+
+ }
+ }
+
+ }
+ }
+ }
+
+ }
+ }
+
+ return(rc);
+}
+
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/gcr_funcs.H b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/gcr_funcs.H new file mode 100644 index 000000000..218feded0 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/gcr_funcs.H @@ -0,0 +1,151 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_io_run_training/gcr_funcs.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 1997, 1998
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME : gcr_funcs.H
+// *! TITLE :
+// *! DESCRIPTION :
+// *! CONTEXT :
+// *!
+// *! OWNER NAME : Varghese, Varkey Email: varkeykv@in.ibm.com
+// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date: | Comment:
+// --------|--------|--------|--------------------------------------------------
+// 1.0 |jaswamin|09/13/11|
+// 2.0 |varkeykv|01/12/12| Post GFW review changes
+//------------------------------------------------------------------------------
+
+#ifndef GCR_FUNCS
+#define GCR_FUNCS
+
+/* Include some system headers */
+#include <list>
+#include <stdint.h>
+#include <fapi.H>
+using namespace fapi;
+#include "edi_regs.h"
+
+enum io_interface_t { CP_PSI,
+ CP_FABRIC_X0, CP_FABRIC_X1, CP_FABRIC_X2, CP_FABRIC_X3,
+ CP_FABRIC_A0, CP_FABRIC_A1, CP_FABRIC_A2,
+ CP_IOMC0_P0, CP_IOMC0_P1, CP_IOMC0_P2, CP_IOMC0_P3,
+ CP_IOMC1_P0, CP_IOMC1_P1, CP_IOMC1_P2, CP_IOMC1_P3,
+ S1_FABRIC_SX0,
+ S1_FABRIC_SA0, S1_FABRIC_SA1, S1_FABRIC_SA2,
+ CEN_DMI,
+ };
+
+// P8 chip interfaces
+const uint32_t NUM_INTERFACES=21;
+const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI",
+ "CP_FABRIC_X0", "CP_FABRIC_X1", "CP_FABRIC_X2", "CP_FABRIC_X3",
+ "CP_FABRIC_A0", "CP_FABRIC_A1", "CP_FABRIC_A2",
+ "CP_IOMC0_P0", "CP_IOMC0_P1", "CP_IOMC0_P2", "CP_IOMC0_P3",
+ "CP_IOMC1_P0", "CP_IOMC1_P1", "CP_IOMC1_P2", "CP_IOMC1_P3",
+ "S1_FABRIC_SX0",
+ "S1_FABRIC_SA0", "S1_FABRIC_SA1", "S1_FABRIC_SA2",
+ "CEN_DMI" };
+// EDI register addresses for CP
+const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000,
+ 0x0401103F, 0x0401103f, 0x0401183f, 0x0401183f,
+ 0x08010c3f, 0x08010c3f, 0x08010c3f,
+ 0x02011a3F, 0x02011a3F, 0x02011a3F, 0x02011a3F,
+ 0x02011e3F, 0x02011e3F, 0x02011e3F, 0x02011e3F,
+ 0x03010c3f,
+ 0x08010c3f, 0x08010c3f, 0x08010c3f,
+ 0x0201043F };
+const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000,
+ 0x04011020, 0x04011020, 0x04011020, 0x04011020,
+ 0x08010c20, 0x08010c20, 0x08010c20,
+ 0x02011a20, 0x02011a20, 0x02011a20, 0x02011a20,
+ 0x02011e20, 0x02011e20, 0x02011e20, 0x02011e20,
+ 0x03010c20,
+ 0x08010c20, 0x08010c20, 0x08010c20,
+ 0x02010420 };
+
+
+// Register type
+typedef enum { tx_per_lane, tx_per_group, tx_per_pack, tx_per_bus, rx_per_lane, rx_per_group, rx_per_pack, rx_per_bus, num_register_type } register_type;
+
+typedef enum { gcr_op_read, gcr_op_write } gcr_op;
+
+
+
+//// clock groups per bus for A bus
+//uint32_t clk_groups_per_bus[NUM_INTERFACES] = { 1, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+//// Lanes per Group
+//uint32_t rx_lanes_per_clk_group[NUM_INTERFACES] = { 1, 20, 20, 20, 20, 23, 23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 17 };
+//uint32_t tx_lanes_per_clk_group[NUM_INTERFACES] = { 1, 20, 20, 20, 20, 23, 23, 23, 17, 17, 17, 17, 17, 17, 17, 17, 24 };
+//uint32_t spares_per_interface[NUM_INTERFACES] = { 1, 2, 2, 2, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2 };
+
+// Lane Bit Defintions
+// 0x00 (lane 0), 0x01 (lane 1) , etc
+const uint8_t SELECT_ALL_LANES=0x1F; // The lane address is a 5 bit value 0b 11111 selects all lanes
+
+// Group Bit Definitions 0x00 group 0 , 0x01 group1 , etc
+const uint8_t RX_GROUP_BROADCAST =0x0F ; // (Write Only) The group address is a 6 bit value to select all groups ,
+const uint8_t TX_GROUP_BROADCAST =0x2F ; // (Write Only) The group address is a 6 bit value to select all groups ,
+
+// ROUTINES
+//------------------------------------------------------------------------------------------------------------------------------------
+// generate the 64 bit scom address for the GCR
+//------------------------------------------------------------------------------------------------------------------------------------
+uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data );
+
+//------------------------------------------------------------------------------------------------------------------------------------
+// handle GCR operations - do not use directly!
+// use GCR_read and GCR_write for reg access - not this function!!!!
+//------------------------------------------------------------------------------------------------------------------------------------
+ReturnCode doGCRop(const Target& chip_target, io_interface_t interface,
+ gcr_op read_or_write, GCR_sub_registers target_io_reg,
+ uint32_t group_address, uint32_t lane_address,
+ ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits,
+ ecmdDataBufferBase &databuf_16bit, int skipCheck=0);
+
+//------------------------------------------------------------------------------------------------------------------------------------
+// GCR SCOM READ - main api for read - do not use doGCRop directly
+//------------------------------------------------------------------------------------------------------------------------------------
+ReturnCode GCR_read(const Target& chip_target, io_interface_t interface,
+ GCR_sub_registers target_io_reg, uint32_t group_address,
+ uint32_t lane_address, ecmdDataBufferBase &databuf_16bit);
+
+//------------------------------------------------------------------------------------------------------------------------------------
+// GCR SCOM WRITE - main api for write - do not use doGCRop directly
+//------------------------------------------------------------------------------------------------------------------------------------
+ReturnCode GCR_write(const Target& chip_target, io_interface_t interface,
+ GCR_sub_registers target_io_reg, uint32_t group_address,
+ uint32_t lane_address, ecmdDataBufferBase set_bits,
+ ecmdDataBufferBase clear_bits, int skipCheck=0);
+
+
+
+
+#endif
+
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_funcs.C b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_funcs.C new file mode 100644 index 000000000..e8fc9ed4d --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_funcs.C @@ -0,0 +1,449 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_io_run_training/io_funcs.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 1997, 1998
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME : IO_funcs.C
+// *! TITLE :
+// *! DESCRIPTION : IO training common functions
+// *! CONTEXT :
+// *!
+// *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com
+// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date: | Comment:
+// --------|--------|--------|--------------------------------------------------
+// 1.0 |varkeykv|01/19/12| Initial check in to solve linker problems in host
+// boot..moved in from io_run_training
+//------------------------------------------------------------------------------
+#include "io_funcs.H"
+
+extern "C"
+{
+ using namespace fapi;
+
+/****************************************************************************************/
+/* edi_training.C - functions of edi_training class */
+/****************************************************************************************/
+
+
+//! Wrapper to Run W,D,E,R , F based on bus_status (selected on);
+ReturnCode edi_training::run_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group) {
+ ReturnCode rc;
+ // bool master_chip_found=false; -- maybe for fabric ...need to test later
+
+ FAPI_DBG("io_run_training: Starting training on SLAVE side");
+ // Set the slave rx_start_wderf
+ rc=run_training_functions(slave_target,slave_interface,slave_group);
+ if (!rc.ok()) {
+ FAPI_ERR("io_run_training: Failed starting slave side training");
+ }
+ else{
+ FAPI_DBG("io_run_training: Starting training on MASTER side\n");
+ // Set the master rx_start_wderf
+ rc=run_training_functions(master_target, master_interface,master_group);
+ if (!rc.ok()) {
+ FAPI_ERR("io_run_training: Failed starting master side training");
+ }
+ else{
+ // Get training function status for Master Chip (poll on the master chip's rx_wderf_done)
+ rc=training_function_status(master_target , master_interface ,master_group, slave_target , slave_interface ,slave_group);
+ if(!rc.ok()){
+ FAPI_ERR("io_run_training : Failed Training");
+ }
+ }
+ }
+ return(rc);
+}
+
+
+// Run selected training function(s)
+ReturnCode edi_training::run_training_functions(const Target& target, io_interface_t interface,uint32_t current_group) {
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ uint16_t bits=0;
+
+ ecmdDataBufferBase set_bits, clear_bits,status_data;
+ rc_ecmd|=set_bits.setBitLength(16);
+ rc_ecmd|=clear_bits.setBitLength(16);
+ rc_ecmd|=set_bits.flushTo0();
+ rc_ecmd|=clear_bits.flushTo1();
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("io_run_training:Data Buffer initiatlization failed !!\n");
+ rc=rc_ecmd; // As per Mike rc_ecmd can be added to rc
+ }
+ else
+ {// Successful databuffer initialization ..we can proceed
+ if (wire_test_status==SELECTED)
+ {
+ bits=rx_start_wiretest;
+ if(endpoints_set==1)
+ {
+ wire_test_status = RUNNING;
+ }
+ rx_wderf_start[WIRE_TEST]=1;
+ }
+ if (desckew_status==SELECTED)
+ {
+ bits|=rx_start_deskew;
+ rx_wderf_start[DESKEW]=1;
+ if(endpoints_set==1)
+ {
+ desckew_status = RUNNING;
+ }
+ }
+ if (eye_opt_status==SELECTED)
+ {
+ bits|=rx_start_eye_opt;
+ rx_wderf_start[EYE_OPT]=1;
+ if(endpoints_set==1)
+ {
+ eye_opt_status= RUNNING;
+ }
+ }
+ if (repair_status==SELECTED)
+ {
+ bits|=rx_start_repair;
+ rx_wderf_start[REPAIR]=1;
+ if(endpoints_set==1)
+ {
+ repair_status = RUNNING;
+ }
+ }
+ if (functional_status==SELECTED)
+ {
+ bits|=rx_start_func_mode;
+ rx_wderf_start[FUNCTIONAL]=1;
+ if(endpoints_set==1)
+ {
+ functional_status = RUNNING;
+ }
+ }
+ endpoints_set++; // Count number of endpoints we have set for training... when its 2 then we set the status to RUNNING
+
+ // No need to do group wise loops , since for every end point there will be a separate thread of training code run
+ // Set Start Bits for group
+ // Group address is set to 0 , since according to Discussion with Dean ,this code will run once per group.
+ rc_ecmd|=set_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ FAPI_ERR("io_run_training:Data Buffer insertion failed !!\n");
+ rc=rc_ecmd;
+ }
+ else
+ {
+ FAPI_DBG("io_run_training:Setting Training start bit on intereface %d group=%d\n",interface,current_group);
+ rc=GCR_write(target , interface, rx_training_start_pg, current_group,0, set_bits, clear_bits);
+ if (rc) {
+ FAPI_ERR("io_run_training: Failed to write training start bits \n");
+ }
+ }
+ }
+ return(rc);
+ }
+
+
+// Checks Status of Training Functions on Master Chip and also captures failure data on failure
+ReturnCode edi_training::training_function_status(const Target& master_chip_target, io_interface_t master_chip_interface , uint32_t master_group, const Target& slave_chip_target ,
+ io_interface_t slave_chip_interface,uint32_t slave_group)
+{
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase status_data;
+ rc_ecmd|=status_data.setBitLength(16);
+ rc_ecmd|=status_data.flushTo0();
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("io_run_training: Failed buffer intialization in training_function_status\n");
+ rc=rc_ecmd;
+ }
+ else
+ {
+ uint64_t curr_cyc = 0; // start time
+ uint64_t end_cycle=max_poll_cycles ;
+
+ int state,fail_bit;
+
+ while ( curr_cyc < end_cycle )
+ {
+ // Reads Status Register for interface
+ rc=GCR_read(master_chip_target , master_chip_interface, rx_training_status_pg, master_group,0, status_data);
+ if (rc) {
+ FAPI_DBG("io_run_training:Failed reading training status on master chip\n");
+ return(rc);
+ }
+
+ if (wire_test_status== RUNNING )
+ {
+ state=WIRE_TEST;
+ fail_bit=rx_wiretest_failed;
+ if( status_data.isBitSet(state) )
+ {
+ rx_wderf_done[WIRE_TEST]=true;
+ if (status_data.getHalfWord(0) & fail_bit)
+ {
+ FAPI_ERR("io_run_training: the wiretest training state reported a fail \n");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC);
+ wire_test_status = FAILED ;
+ rx_wderf_failed[WIRE_TEST]=true;
+ // Run First FAILED Data Capture for Wire Test for FAILED bus
+ dump_ffdc_wiretest(master_chip_target, master_chip_interface ,master_group, slave_chip_target , slave_chip_interface , slave_group);
+ break;
+ }
+ else
+ {
+ FAPI_DBG("io_run_training: the wiretest training function completed successfully \n") ;
+ wire_test_status = SUCCESSFULL ;
+ }
+ }
+ }
+
+ if (desckew_status == RUNNING )
+ {
+ state=DESKEW;
+ fail_bit=rx_deskew_failed;
+ if( status_data.isBitSet(state))
+ {
+ rx_wderf_done[DESKEW]=1;
+ if (status_data.getHalfWord(0) & fail_bit)
+ {
+ rx_wderf_failed[DESKEW]=true;
+ FAPI_ERR("io_run_training : deskew training state reported a fail \n");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC);
+ desckew_status = FAILED ;
+ break;
+ }
+ else
+ {
+ FAPI_DBG("io_run_training: deskew training function completed successfully \n") ;
+ desckew_status = SUCCESSFULL ;
+ }
+ }
+ }
+
+ if (eye_opt_status == RUNNING )
+ {
+ state=EYE_OPT;
+ fail_bit=rx_eye_opt_failed;
+ if( status_data.isBitSet(state))
+ {
+ rx_wderf_done[EYE_OPT]=1;
+ if (status_data.getHalfWord(0) & fail_bit)
+ {
+ FAPI_ERR("io_run_training : eye_opt_ training state reported a fail\n");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC);
+ rx_wderf_failed[EYE_OPT]=true;
+ eye_opt_status = FAILED ;
+ break;
+ }
+ else
+ {
+ FAPI_DBG("io_run_training: eye_opt_ training function completed successfully \n") ;
+ eye_opt_status = SUCCESSFULL ;
+ }
+ }
+ }
+
+ if (repair_status == RUNNING )
+ {
+ state=REPAIR;
+ fail_bit=rx_repair_failed;
+ if( status_data.isBitSet(state))
+ {
+ rx_wderf_done[REPAIR]=1;
+ if (status_data.getHalfWord(0) & fail_bit)
+ {
+ FAPI_DBG("io_run_training: static repair encountered an error \n");
+ rx_wderf_failed[REPAIR]=true;
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC);
+ repair_status = FAILED ;
+ break;
+ }
+ else
+ {
+ FAPI_DBG("io_run_training: the rx_repair function completed successfully \n") ;
+ repair_status = SUCCESSFULL ;
+ }
+ }
+ }
+
+
+ if (functional_status == RUNNING)
+ {
+ state=FUNCTIONAL;
+ fail_bit=rx_func_mode_failed;
+ if( status_data.isBitSet(state))
+ {
+ rx_wderf_done[FUNCTIONAL]=1;
+ if (status_data.getHalfWord(0) & fail_bit)
+ {
+ FAPI_DBG("io_run_training: rx_func_mode_failed \n");
+ rx_wderf_failed[FUNCTIONAL]=true;
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC);
+ functional_status = FAILED ;
+ break;
+ }
+ else
+ {
+ FAPI_DBG("io_run_training: rx_func_mode_function completed successfully \n") ;
+ functional_status = SUCCESSFULL ;
+ }
+ }
+ }
+
+
+ if ((wire_test_selected && wire_test_status== RUNNING) || (desckew_selected && desckew_status == RUNNING) ||
+ (repair_selected && repair_status == RUNNING ) || (eye_opt_selected && eye_opt_status == RUNNING) ||
+ (functional_selected && functional_status == RUNNING ) )
+ {
+ // Training still running , continue checking status
+ curr_cyc++;
+ FAPI_DBG("\n\t io_run_training: Cycles into polling = %lld\n", curr_cyc);
+ FAPI_DBG("\n\t io_run_training: Cycles remaining in polling = %lld\n", end_cycle - curr_cyc );
+ rc=fapiDelay(1,increment_poll_cycles);
+ if(!rc.ok())
+ {
+ FAPI_ERR("io_run_training : Unexpected error in fapiDelay routine\n");
+ return(rc);
+ }
+ }
+ else
+ {
+ // Training Completed Exit cuurent Loop
+ break;
+ }
+
+ if ( curr_cyc >= end_cycle )
+ {
+ dump_ffdc_wiretest(master_chip_target, master_chip_interface ,master_group, slave_chip_target , slave_chip_interface, slave_group);
+
+ if (wire_test_selected && wire_test_status== RUNNING)
+ {
+ FAPI_ERR("io_run_training: wiretest timeout");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC);
+ }
+ else if (desckew_selected && desckew_status == RUNNING)
+ {
+ FAPI_ERR("io_run_training: deskew timeout");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC);
+ }
+ else if (repair_selected && repair_status == RUNNING)
+ {
+ FAPI_ERR("io_run_training: repair timeout");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC);
+ }
+ else if (eye_opt_selected && eye_opt_status == RUNNING)
+ {
+ FAPI_ERR("io_run_training: eyeopt timeout");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC);
+ }
+ else
+ {
+ FAPI_ERR("io_run_training: func timeout");
+ FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC);
+ }
+ break;
+ }
+ } // polling loop
+ }
+ return(rc);
+}
+
+// Determines if target is a master...currently not used , but could be used in Fabric(EI4) but i assume PLAT code will know which side is master and which is slave
+ReturnCode edi_training::isChipMaster(const Target& chip_target, io_interface_t chip_interface, bool & masterchip_found ,uint32_t current_group ) {
+ ReturnCode rc;
+ ecmdDataBufferBase mode_data(16);
+ masterchip_found=false;
+
+ // Check if rx_master_mode bit is set for chip
+ // Read rx_master_mode for chip
+ rc=GCR_read(chip_target , chip_interface, rx_mode_pg, current_group,0, mode_data);
+ if (rc) {
+ FAPI_DBG("io_run_training: Error reading master mode bit\n");
+ }
+ // Check if chip is master
+ if (mode_data.isBitSet(0)) {
+ masterchip_found =true;
+ }
+ return(rc);
+}
+
+
+
+// First Fail Data Capture (wire_test)
+// FFDC functions have not been tested in detail ..
+// Will need to tie this into the eRepair/PRD conversation that we are having with Zane
+ReturnCode edi_training::dump_ffdc_wiretest(const Target& master_chip_target, io_interface_t master_chip_interface , uint32_t master_group, const Target& slave_chip_target ,
+ io_interface_t slave_chip_interface, uint32_t slave_group)
+{
+ ReturnCode rc;
+
+ ecmdDataBufferBase master_lane_bad_vec_0_15_data(16);
+ ecmdDataBufferBase master_lane_bad_vec_16_31_data(16);
+ ecmdDataBufferBase slave_lane_bad_vec_0_15_data(16);
+ ecmdDataBufferBase slave_lane_bad_vec_16_31_data(16);
+
+ ecmdDataBufferBase master_lane_bad_data(16);
+
+ FAPI_DBG("dump_ffdc_wiretest function entered \n");
+
+ // DO MASTER HERE
+ // Read rx_lane_bad_vec_0_15_pg & rx_lane_bad_vec_16_32_pg
+ rc=GCR_read(master_chip_target , master_chip_interface, rx_lane_bad_vec_0_15_pg, master_group,0, master_lane_bad_vec_0_15_data);
+ if (rc)
+ {
+ FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_0_15");
+ }
+ //avoiding else on purpose.. I want to try reading the second registe if first one on master fails
+
+ rc=GCR_read(master_chip_target , master_chip_interface, rx_lane_bad_vec_16_31_pg, master_group,0, master_lane_bad_vec_16_31_data);
+ if (rc) {
+ FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_16_31");
+ }
+ // Not doing the else here on purpose.. if read on master fails .. we want to try reading slave side
+
+ // DO SLAVE HERE
+ rc=GCR_read(slave_chip_target , slave_chip_interface, rx_lane_bad_vec_0_15_pg, slave_group,0, slave_lane_bad_vec_0_15_data);
+ if (rc)
+ {
+ FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_0_15 on slave chip");
+
+ }
+ rc=GCR_read(slave_chip_target , slave_chip_interface, rx_lane_bad_vec_16_31_pg, slave_group,0, slave_lane_bad_vec_16_31_data);
+ if (rc) {
+ FAPI_ERR("io_run_training : Error Reading rx_lane_bad_vec_16_31 on slave chip");
+ }
+ return(rc);
+}
+
+
+
+}
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_funcs.H b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_funcs.H new file mode 100644 index 000000000..1b47f5c73 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_funcs.H @@ -0,0 +1,156 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_io_run_training/io_funcs.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// *!*************************************************************************** +// *! (C) Copyright International Business Machines Corp. 1997, 1998 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!*************************************************************************** +// *! FILENAME : IO_funcs.H +// *! TITLE : +// *! DESCRIPTION : IO training comomon functions +// *! CONTEXT : +// *! +// *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com +// *! BACKUP NAME : Vijay S Kantanavar Email: vijaysk@in.ibm.com +// *! +// *!*************************************************************************** +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:|Author: | Date: | Comment: +// --------|--------|--------|-------------------------------------------------- +// 1.0 |varkeykv|11/17/11| Combined other header files into one common file +//------------------------------------------------------------------------------ + +/****************************************************************************************/ +/* IO_funcs.H */ +/****************************************************************************************/ +#ifndef IO_funcs +#define IO_funcs +#include <fapi.H> +#include "gcr_funcs.H" +#include "edi_regs.h" + +using namespace fapi; + +class edi_training { +public: + + // Training enums for Wire test , Deskew , Eye Opt ,Repair , Functional --- + typedef enum { WIRE_TEST , DESKEW , EYE_OPT , REPAIR , FUNCTIONAL + , TRAINING_TYPES} training_function; + // Bus Status State + typedef enum { NOT_RUNNING, SELECTED, RUNNING, SUCCESSFULL , + FAILED} bus_status; + // Selection + bus_status wire_test_selected; + bus_status desckew_selected; + bus_status eye_opt_selected; + bus_status repair_selected; + bus_status functional_selected; + + // Current Training States + bus_status wire_test_status; + bus_status desckew_status; + bus_status eye_opt_status; + bus_status repair_status; + bus_status functional_status; + + static const uint32_t max_poll_cycles=100; + static const uint32_t increment_poll_cycles=1; + uint32_t endpoints_set; // How many end points have we accessed so far + + bool rx_wderf_timeout[6]; // Summary 5 bit timout status + bool rx_wderf_start[6]; // Summary 5 bit status + bool rx_wderf_done[6]; // Summary 5 bit done + bool rx_wderf_failed[6]; // Summary 5 bit failed + + // Constructor Initializes default states for status variables + edi_training( ) + { + wire_test_selected = SELECTED; + desckew_selected = SELECTED; + eye_opt_selected = SELECTED; + repair_selected = SELECTED; + functional_selected = SELECTED; + + wire_test_status = SELECTED; + desckew_status = SELECTED; + eye_opt_status = SELECTED; + repair_status = SELECTED; + functional_status = SELECTED; + + for(int i=0;i<6;++i) + { + rx_wderf_timeout[i]=false; + rx_wderf_start[i]=false; + rx_wderf_done[i]=false; + rx_wderf_failed[i]=false; + } + endpoints_set=0; // reset this for multi endpoint pair runs + } + + //! Destructor + ~edi_training() { + } + + // Training Functions + // Run Wirtest,Deskew,Repair and Functional mode on selected target(endpoint) pair + ReturnCode run_training(const Target& master_target, io_interface_t + master_interface,uint32_t master_group, + const Target& slave_target, io_interface_t + slave_interface,uint32_t slave_group); + // Runs the selected training function(s) + ReturnCode run_training_functions(const Target& target, + io_interface_t interface, + uint32_t current_group); + // Checks the status of the training selected function(s) + ReturnCode training_function_status(const Target& master_target, + io_interface_t master_interface, + uint32_t master_group, + const Target& slave_target, + io_interface_t slave_interface, + uint32_t slave_group ); + + // First Fail Data Capture Routines + // Wire Test First Fail Data Capture + ReturnCode dump_ffdc_wiretest(const Target& master_chip_target, + io_interface_t master_chip_interface , + uint32_t master_group, + const Target& slave_chip_target , + io_interface_t slave_chip_interface, + uint32_t slave_group); + + // Utility functions + // Determines if target chip is a Master (reads rx_master_mode bit) + ReturnCode isChipMaster(const Target& target, io_interface_t interface, + bool& master_chip_found, + uint32_t current_group ); +}; + + + + + + +/* functions */ +#endif diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training.C new file mode 100644 index 000000000..f8cf41217 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training.C @@ -0,0 +1,68 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_io_run_training/io_run_training.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// *!*************************************************************************** +// *! (C) Copyright International Business Machines Corp. 1997, 1998 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!*************************************************************************** +// *! FILENAME : io_run_training.C +// *! TITLE : +// *! DESCRIPTION : IO Wiretest,Deskew ,Eye Opt training procedure +// *! CONTEXT : +// *! +// *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com +// *! BACKUP NAME : Vijay S Kantanavar Email: vijaysk@in.ibm.com +// *! +// *!*************************************************************************** +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:|Author: | Date: | Comment: +// --------|--------|--------|-------------------------------------------------- +// 1.0 |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK +// 1.1 |varkeykv|11/16/11|Fixed header files & dependencies +//------------------------------------------------------------------------------ +#define EDI_IO + +#include <fapi.H>
+#include "io_run_training.H"
+ + +extern "C" {
+ using namespace fapi; +// These functions work on a pair of targets. One is the master side of the bus interface, the other the slave side. For eg; in EDI(DMI2)PU is the master and Centaur is the slave +// In EI4 both sides have pu targets . After the talk with Dean , my understanding is that targets are configured down upto the endpoints of a particular bus. eg; pu 0 A0 --> pu 1 A3 could be a combination on EI4 +// In a EDI(DMI) bus the targets are considered to be one pu and one centaur pair . The overall code is same for EDI and EI4 and the run_training function handles both bus types ( X ,A or MC ) . +ReturnCode io_run_training(const Target &master_target,io_interface_t master_interface,uint32_t master_group,const Target &slave_target,io_interface_t slave_interface,uint32_t slave_group){ + ReturnCode rc; + edi_training init; + + FAPI_DBG("io_run_training:Running training on interface %d on master side and %d on slave side with master_group set to %d and slave group=%d",master_interface,slave_interface,master_group,slave_group); + + rc=init.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + + return rc; +}
+
+
+ +} // extern diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training.H b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training.H new file mode 100644 index 000000000..35219aa3d --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training.H @@ -0,0 +1,59 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_io_run_training/io_run_training.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +#ifndef IO_RUN_TRAINING_H_
+#define IO_RUN_TRAINING_H_
+
+#include <fapi.H>
+#include "io_funcs.H"
+
+using namespace fapi;
+
+/**
+ * io_run_training func pointer Typedef for hostboot
+ *
+ */
+typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,io_interface_t ,uint32_t ,const fapi::Target &,io_interface_t ,uint32_t );
+
+extern "C"
+{
+
+/**
+ * io_run_training
+ *
+ * master_target is the master side of a bus ..p8 in a DMI .. or a p8 master on fabric
+ * master_interface - since this code is generic across bus types master interface tells the code which bus interface is selected. This maps to a BUS GCR SCOM address base
+ * master_group - clock group on master side ..since fAPI code runs only on a single clock group
+ * slave_target - slave side of the bus .. Centaur in DMI .. or p8 slaves
+ * slave_interface - same as the master interface defn
+ * slave_group - clock group on the slave side since fAPI code runs only on a single clock group
+ *
+ * @return ReturnCode
+ */
+fapi::ReturnCode io_run_training(const fapi::Target &master_target,io_interface_t master_interface,uint32_t master_group,const fapi::Target & slave_target,io_interface_t slave_interface,uint32_t slave_group);
+
+
+
+
+} // extern "C"
+
+#endif // IO_RUN_TRAINING_H
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training_errors.xml b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training_errors.xml new file mode 100644 index 000000000..7672a4789 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/io_run_training_errors.xml @@ -0,0 +1,98 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/io_run_training_errors.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END --> +<!-- Error definitions for io_run_training procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_INVALID_ARGS_RC</rc> + <description>Invalid or out-of-range argument value(s) presented to IO_RUN_TRAINING HWP.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_INTERNAL_ERR_RC</rc> + <description>Unexpected internal program logic error.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FAIL_ERR_RC</rc> + <description>Training fail was reported in a P8 or Centaur status register</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FAIL_WIRETEST_RC</rc> + <description>Wiretest Training fail was reported in a P8 or Centaur status register</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FAIL_DESKEW_RC</rc> + <description>Deskew Training fail was reported in a P8 or Centaur status register</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FAIL_EYE_OPT_RC</rc> + <description>Eye Optimization Training fail was reported in a P8 or Centaur status register</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FAIL_REPAIR_RC</rc> + <description>Static Repair Training fail was reported in a P8 or Centaur status register</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FAIL_FUNC_MODE_RC</rc> + <description>Functional mode Training fail was reported in a P8 or Centaur status register</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC</rc> + <description>io run training wiretest timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_DESKEW_TIMEOUT_RC</rc> + <description>io run training deskew timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC</rc> + <description>io run training eye opt timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_REPAIR_TIMEOUT_RC</rc> + <description>io run training repair timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC</rc> + <description>io run training functional mode timed out waiting for pass/fail indication in the p8 or centaur Status Registers</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_GCR_WRITE_MISMATCH_RC</rc> + <description>IO GCR write operation failed to readback data that was written</description> + <ffdc>READ_BUF</ffdc> + <ffdc>WRITE_BUF</ffdc> + </hwpError> + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C new file mode 100644 index 000000000..2893a6d2c --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C @@ -0,0 +1,524 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_training.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END + +/** + * @file dmi_training.C // @ + * + * Support file for hardware procedure: + * DMI Training // @ + * + */ + +/** + * @note "// @" comments denote lines that should be built from the HWP + * tag block. See the preliminary design in dmi_training.H + * Please save. + */ + + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +// #include <kernel/console.H> +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +// targeting support. +#include <targeting/attributes.H> +#include <targeting/entitypath.H> +#include <targeting/target.H> +#include <targeting/targetservice.H> +#include <targeting/iterators/rangefilter.H> +#include <targeting/predicates/predicatectm.H> + +// fapi support +#include <fapi.H> +#include <fapiPlatHwpInvoker.H> + +// -- prototype includes -- +#include "dmi_training.H" // @ +#include "proc_cen_framelock.H" // @ +#include "io_run_training.H" // @ + +namespace DMI_TRAINING +{ +trace_desc_t *g_trac_dmi_training = NULL; // @ +TRAC_INIT(&g_trac_dmi_training, "DMI_TRAINING", 2048 ); // @ + +using namespace fapi; +using namespace TARGETING; + + +/** + * @brief isTargetGood + * test if the target can be used by the HWP. + * for now, assume that functional implies present, etc. + * + */ +bool isTargetGood( const TARGETING::Target* &i_rtargetHandle ) +{ + bool l_rc = false; + + if ( i_rtargetHandle->getAttr<ATTR_HWAS_STATE>().functional ) + { + l_rc = true; + } + + + return l_rc; +} + + + + +// +// Wrapper function to call 11.1 dmi_scominit +// +void call_dmi_scominit( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + + TRACDCOMP( g_trac_dmi_training, "call_dmi_scominit entry" ); //@ + + + TRACDCOMP( g_trac_dmi_training, "dmi_scominit exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + + +// +// Wrapper function to call 11.2 : dmi_erepair +// +void call_dmi_erepair( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + + TRACDCOMP( g_trac_dmi_training, "call_dmi_erepair entry" ); //@ + + + TRACDCOMP( g_trac_dmi_training, "dmi_erepair exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + +// +// Wrapper function to call 11.3 : dmi_io_dccal +// +void call_dmi_io_dccal( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + + TRACDCOMP( g_trac_dmi_training, "call_dmi_io_dccal entry" ); //@ + + + TRACDCOMP( g_trac_dmi_training, "dmi_io_dccal exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + + +// +// Wrapper function to call 11.4 : dmi_io_run_training +// +void call_dmi_io_run_training( void *io_pArgs ) //@ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + fapi::ReturnCode l_fapirc; + TARGETING::TargetService& l_targetService = targetService(); + uint8_t l_cpuNum = 0; + + TRACDCOMP( g_trac_dmi_training, "dmi_io_run_training entry" ); //@ + + // figure out what targets we need + TARGETING::PredicateCTM l_procChipFilter( CLASS_CHIP, TYPE_PROC ); + TARGETING::TargetRangeFilter l_cpuFilter( + l_targetService.begin(), + l_targetService.end(), + &l_procChipFilter ); + + for ( l_cpuNum=0; l_cpuFilter; ++l_cpuFilter, l_cpuNum++ ) + { + // make a local copy of the CPU target + const TARGETING::Target* l_cpu_target = *l_cpuFilter; + + // Test if the CPU is functional + if ( ! isTargetGood( l_cpu_target ) ) + { + // if not functional skip to the next CPU + continue; + } + + // get the mcs chiplets associated with this cpu + TARGETING::PredicateCTM l_mcsChipFilter(CLASS_UNIT, TYPE_MCS); + TARGETING::TargetHandleList l_mcsTargetList; + l_targetService.getAssociated( + l_mcsTargetList, + l_cpu_target, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::IMMEDIATE, + &l_mcsChipFilter ); + + for ( uint8_t j=0; j < l_mcsTargetList.size(); j++ ) + { + // make a local copy of the MCS target + const TARGETING::Target* l_mcs_target = l_mcsTargetList[j]; + uint8_t l_mcsNum = l_mcs_target->getAttr<ATTR_CHIP_UNIT>(); + + // assuming that functional implies present, poweredOn, etc. + if ( ! isTargetGood( l_mcs_target ) ) + { + // if not functional skip to the next CPU + + continue; + } + + // find all the Centaurs that are associated with this MCS + TARGETING::PredicateCTM l_membufChips(CLASS_CHIP, TYPE_MEMBUF); + TARGETING::TargetHandleList l_memTargetList; + l_targetService.getAssociated(l_memTargetList, + l_mcs_target, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_membufChips); + + for ( uint8_t k=0, l_memNum=0; k < l_memTargetList.size(); k++, l_memNum++ ) + { + // make a local copy of the MEMBUF target + const TARGETING::Target* l_mem_target = l_memTargetList[k]; + + if ( ! isTargetGood( l_mem_target ) ) + { + // if not functional skip to the next CPU + continue; + } + + + + //@@@@@ Customized block for dmi_io_run_training @@@@@ + // struct containing custom parameters that is fed to HWP + struct DmiIORunTrainingParms { + io_interface_t master_interface; + uint32_t master_group; + io_interface_t slave_interface; + uint32_t slave_group; + } l_CustomParms[] = + { { /*MCS0*/ CP_IOMC0_P0, 3, CEN_DMI, 0 }, + { /*MCS1*/ CP_IOMC0_P1, 2, CEN_DMI, 0 }, + { /*MCS2*/ CP_IOMC0_P2, 1, CEN_DMI, 0 }, + { /*MCS3*/ CP_IOMC0_P3, 0, CEN_DMI, 0 }, + { /*MCS4*/ CP_IOMC1_P0, 3, CEN_DMI, 0 }, + { /*MCS5*/ CP_IOMC1_P1, 2, CEN_DMI, 0 }, + { /*MCS6*/ CP_IOMC1_P2, 1, CEN_DMI, 0 }, + { /*MCS7*/ CP_IOMC1_P3, 0, CEN_DMI, 0 }, + }; + // call the HWP with each target ( if parallel, spin off a task ) + const fapi::Target l_fapi_master_target( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + ( const_cast<TARGETING::Target*>(l_cpu_target) ) + ); + const fapi::Target l_fapi_slave_target( + TARGET_TYPE_MEMBUF_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_mem_target)) + ); + + TRACDCOMP( g_trac_dmi_training, + "===== Call dmi_io_run_training HWP( cpu 0x%x, mcs 0x%x, master 0x%x 0x%x, mem 0x%x, slave 0x%x 0x%x ) : ", + l_cpuNum, + l_mcsNum, + l_CustomParms[l_mcsNum].master_interface, + l_CustomParms[l_mcsNum].master_group, + l_memNum, + l_CustomParms[l_mcsNum].slave_interface, + l_CustomParms[l_mcsNum].slave_group + ); + EntityPath l_path; + l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_mcs_target->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_mem_target->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + TRACDCOMP( g_trac_dmi_training, "===== " ); + + l_fapirc = io_run_training( + l_fapi_master_target, + l_CustomParms[l_mcsNum].master_interface, + l_CustomParms[l_mcsNum].master_group, + l_fapi_slave_target, + l_CustomParms[l_mcsNum].slave_interface, + l_CustomParms[l_mcsNum].slave_group ); + //@@@@@ + + // process return code. + if ( l_fapirc != fapi::FAPI_RC_SUCCESS ) + { + /** + * @todo fapi error - just print out for now... + */ + TRACFCOMP( g_trac_dmi_training, + "ERROR: io_run_training HWP( cpu 0x%x, mcs 0x%x, master 0x%x 0x%x, mem 0x%x, slave 0x%x 0x%x ) returned %d ", + l_cpuNum, + l_mcsNum, + l_CustomParms[l_mcsNum].master_interface, + l_CustomParms[l_mcsNum].master_group, + l_memNum, + l_CustomParms[l_mcsNum].slave_interface, + l_CustomParms[l_mcsNum].slave_group, + static_cast<uint32_t>(l_fapirc) ); + } + } //end for l_mem_target + + } // end for l_mcs_target + + } // end for l_cpu_target + + + TRACDCOMP( g_trac_dmi_training, "call_io_run_training exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + + +// +// Wrapper function to call 11.5 : host_startPRD_dmi +// +void call_host_startPRD_dmi( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + + TRACDCOMP( g_trac_dmi_training, "call_host_startPRD_dmi entry" ); //@ + + + TRACDCOMP( g_trac_dmi_training, "host_startPRD_dmi exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + + +// +// Wrapper function to call 11.6 : host_attnlisten_cen +// +void call_host_attnlisten_cen( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + + TRACDCOMP( g_trac_dmi_training, "call_host_attnlisten_cen entry" ); //@ + + + TRACDCOMP( g_trac_dmi_training, "<host_attnlisten_cen exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + +// +// Wrapper function to call 11.7 : proc_cen_framelock +// +void call_proc_cen_framelock( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + fapi::ReturnCode l_fapirc; + proc_cen_framelock_args l_args; + TARGETING::TargetService& l_targetService = targetService(); + uint8_t l_cpuNum = 0; + + TRACDCOMP( g_trac_dmi_training, "call_proc_cen_framework entry" ); //@ + + TARGETING::PredicateCTM l_procChipFilter( CLASS_CHIP, TYPE_PROC ); + TARGETING::TargetRangeFilter l_cpuFilter( + l_targetService.begin(), + l_targetService.end(), + &l_procChipFilter ); + + for ( l_cpuNum=0; l_cpuFilter; ++l_cpuFilter, l_cpuNum++ ) + { + // make a local copy of the CPU target + const TARGETING::Target* l_cpu_target = *l_cpuFilter; + + // Test if the CPU is functional + if ( ! isTargetGood( l_cpu_target ) ) + { + // if not functional skip to the next CPU + + continue; + } + + // get the mcs chiplets associated with this cpu + TARGETING::PredicateCTM l_mcsChipFilter(CLASS_UNIT, TYPE_MCS); + TARGETING::TargetHandleList l_mcsTargetList; + l_targetService.getAssociated( + l_mcsTargetList, + l_cpu_target, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::IMMEDIATE, + &l_mcsChipFilter ); + + for ( uint8_t j=0; j < l_mcsTargetList.size(); j++ ) + { + // make a local copy of the MCS target + const TARGETING::Target* l_mcs_target = l_mcsTargetList[j]; + + uint8_t l_mcsNum = l_mcs_target->getAttr<ATTR_CHIP_UNIT>(); + + // assuming that functional implies present, poweredOn, etc. + if ( ! isTargetGood( l_mcs_target ) ) + { + // if not functional skip to the next CPU + continue; + } + + + // find all the Centaurs that are associated with this MCS + TARGETING::PredicateCTM l_membufChips(CLASS_CHIP, TYPE_MEMBUF); + TARGETING::TargetHandleList l_memTargetList; + l_targetService.getAssociated(l_memTargetList, + l_mcs_target, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_membufChips); + + for ( uint8_t k=0, l_memNum=0; k < l_memTargetList.size(); k++, l_memNum++ ) + { + // make a local copy of the MEMBUF target + const TARGETING::Target* l_mem_target = l_memTargetList[k]; + + + if ( ! isTargetGood( l_mem_target ) ) + { + // if not functional skip to the next CPU + continue; + } + //@@@@@ Customized block for proc_cen_framelock @@@@@@ + + // fill out the args struct. + l_args.mcs_pu = l_mcsNum; + l_args.in_error_state = false; + l_args.channel_init_timeout = CHANNEL_INIT_TIMEOUT_NO_TIMEOUT; + l_args.frtl_auto_not_manual = true; + l_args.frtl_manual_pu = 0; + l_args.frtl_manual_mem = 0; + + // Create compatable FAPI Targets from the vanilla targets, + // and invoke the HWP. + fapi::Target l_fapiCpuTarget( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + ( const_cast<TARGETING::Target*>(l_cpu_target) ) + ); + fapi::Target l_fapiMemTarget( + TARGET_TYPE_MEMBUF_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_mem_target)) + ); + + TRACFCOMP( g_trac_dmi_training, + "===== Call proc_cen_framelock HWP( cpu 0x%x, mcs 0x%x, mem 0x%x ) : ", + l_cpuNum, + l_mcsNum, + l_memNum ); + EntityPath l_path; + l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_mcs_target->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_mem_target->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + TRACDCOMP( g_trac_dmi_training, "===== " ); + + // finally! + l_fapirc = proc_cen_framelock( + l_fapiCpuTarget, + l_fapiMemTarget, + l_args ); + + //@@@@@ + if ( l_fapirc != fapi::FAPI_RC_SUCCESS ) + { + /** + * @todo fapi error - just print out for now... + */ + TRACFCOMP( g_trac_dmi_training, + "ERROR %d : proc_cen_framelock HWP( cpu 0x%x, mcs 0x%x, mem 0x%x )", + static_cast<uint32_t>(l_fapirc), + l_cpuNum, + l_mcsNum, + l_memNum ); + } + } // end mem + } // end mcs + } // end cpu + + //@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + TRACDCOMP( g_trac_dmi_training, "call_proc_cen_framework exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + + +// +// Wrapper function to call 11.8 : cen_set_inband_addr +// +void call_cen_set_inband_addr( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + + TRACDCOMP( g_trac_dmi_training, "call_cen_set_inband_addr entry" ); //@ + + + TRACDCOMP( g_trac_dmi_training, "cen_set_inband_addr exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + + +}; // end namespace + diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.H b/src/usr/hwpf/hwp/dmi_training/dmi_training.H new file mode 100644 index 000000000..dc729cc71 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.H @@ -0,0 +1,320 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/dmi_training.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END + +#ifndef __DMI_TRAINING_DMI_TRAINING_H +#define __DMI_TRAINING_DMI_TRAINING_H +/** + * @file dmi_training.H + * + * All of the following routines are "named isteps" - they are invoked as + * tasks by the @ref IStepDispatcher. + * + */ + +/** + * @subpage Generating new HWP + * + * Hopefully we can automate this, if not, the tag file should still be + * generated by the HWP writer. + * template files for istep<@istepnum>list.H, and <@istepname.H> have have + * been provided. + * + * Please consult the latest version of Dean's document + * HostBoot IPL Flow for VPL and PgP + * to get IStep names, IStep numbers, substep numbers, etc. + * + * Note: + * <@istepname> is the IStep name stated in Dean's document, with + * '_' substituted for spaces. + * For example, dmi_training. + * <@substepname> is the substep name stated in Dean's document, with '_' + * substituted for spaces. + * for example, proc_cen_framelock + * + * To set up to run a new HWP, follow these directions + * ( or have your perlscript do it from the tag block ) + * + * Make up a new directory src/usr/HWPs/<@istepname> + * Make up a new directory src/usr/HWPs/<@istepname>/<@substepname> + * Copy code for new HWP to src/usr/HWPs/<@istepname>/<@substepname>. using git. + * For example, to set up for istep 11.7, proc_gen_framelock : + * ## cutNpaste the fetch comand from Gerrit. See the webpage at + * ## http://gfw160.austin.ibm.com:8080/gerrit/#change,597 + * git fetch ssh://wenning@gfw160.austin.ibm.com:29418/hwp_review_centaur refs/changes/97/597/3 + * ## then run the git command to put the code in the right directory: + * git diff FETCH_HEAD FETCH_HEAD~1 -R | git apply --directory=src/usr/HWPs/dmi_training/proc_gen_framelock + * + * Part of the HWP source should be a <@substep>.xml file . + * Add the <@substep>.xml file (actually any xml files) to src/usr/hwpf/hwp + * and update hwpf/makefile to process the xml file + * + * Make up a new file src/usr/HWPs/<@istepname>/<@istepname.H> (use src/usr/HWPs/template.H as a template) + * Make up a new file src/usr/HWPs/<@istepname>/<@istepname.C> (use src/usr/HWPs/template.C as a template) + * Make up new makefile src/usr/HWPs/<@istepname>/makefile to compile the HWP and wrapper + * Make sure you add the lines + * ## pointer to common HWP files + * EXTRAINCDIR += ${ROOTPATH}/src/usr/HWPs/include + * to the makefiles. + * + * + * * Update all the other makefiles: + * src/usr/HWPs/makefile + * src/usr/makefile + * src/makefile + * + * + * Add a tag block inside <@istepname>.H ( for now, I would like to see this + * inside the HWP source) with all the information on the + * istep. An example tag block for IStep 11.7, DMI Training, proc_cen_framelock + * is below. + * The tag block will be used to modify and create framework files + * to support the hardware procedure. + * + * Modify: + * src/include/usr/istepmasterlist.H + * src/usr/HWPs/<@istepname>/<@istepname>.H + * src/usr/HWPs/<@istepname>/<@istepname>.C + * Create: + * src/include/usr/istep<@istepname>list.H + * + * The tag block keywords, with explanations, are as follows: + * * @tag isteplist + * - should be at the beginning of the block to tell the (mythical) perl + * script that this will generate an IStep wrapper for an HWP + * + * * @docversion (version # of Dean's IPL document) + * - adds a comment to istep<@istepname>list.H + * + * * @istepname ( istep name from Dean's IPL document ) + * - creates a namespace ISTEP_NAME, i.e. uppercased <@istepame> + * in <@istepname>.C and <@istepname>.H + * - creates a new module id in src/include/usr/initsvcreasoncodes.H + * - creates a modulename string "<@istepname>.so" for istep<@istepnum>list.H + * - ? + * + * * @istepnum (istep number from Dean's IPL document) + * - creates a new istep<@istepnum>list.H file in /usr/include/isteps/ + * - adds the new istep<@istepnum>list.H file to src/include/usr/istepmasterlist.H + * in the correct place in the master istep list. + * - sets the istep number in the ISTEPNAME() macro in istep<@istepnum>list.H + * * @istepdesc ( description of istep from Dean's document ) + * - creates comments in istep<@istepnum>list.H file + * + * -- one or more substep blocks: + * * @substepname (substepname from Dean's document) + * - creates a prototype for <@substepname> + * + * * @substepnum ( number of substep from Dean's document ) + * - sets the istep number in the ISTEPNAME() macro in istep<@istepnum>list.H + * + * @target_scheduling ( serial or parallel ) + * - will attempt to run each target either serially or in parallel + * + * -- 0 or more target types to be used as parameters to HWP + * TBD needs work + * @target_type (type or class of targets that this HWP should run under) + * - adds code to find the targets used in TARGETING + * -- + * + * -- + */ + +// +// * list of functions called for DMI Training - ISTEP 11 according to Dean's +// * HostBoot IPL Flow v982 +// * +// * 11.1. dmi_scominit : Scom setup on centaur +// * 11.2. dmi_erepair : Restore EDI Bus eRepair data +// * 11.3. dmi_io_dccal : Calibrate DMI interfaces +// * 11.4. dmi_io_run_training : Run training on MC buses +// * 11.5. host_startPRD_dmi : Load PRD for DMI domain +// * 11.6. host_attnlisten_cen : Start listening for attentions +// * 11.7. proc_cen_framelock : Initialize EDI Frame +// * 11.8. cen_set_inband_addr : Set the Inband base addresses +// + +/* @tag isteplist + * @docversion v0.982 (01/11/12) + * @istepname dmi_training + * @istepnum 11 + * @istepdesc DMI Training + * + * @substepnum 1 + * @substepname dmi_scominit + * @substepdesc : Scom setup on centaur + * @target_sched serial + * + * @substepnum 2 + * @substepname dmi_erepair + * @substepdesc : Restore EDI Bus eRepair data + * @target_sched serial + * + * @substepnum 3 + * @substepname dmi_io_dccal + * @substepdesc : Calibrate DMI interfaces + * @target_sched serial + * + * @substepnum 4 + * @substepname dmi_io_run_training + * @substepdesc : Run training on MC buses + * @target_sched serial + * + * @substepnum 5 + * @substepname host_startPRD_dmi + * @substepdesc : Load PRD for DMI domain + * @target_sched serial + * + * @substepnum 6 + * @substepname host_attnlisten_cen + * @substepdesc : Start listening for attentions + * @target_sched serial + * + * @substepnum 7 + * @substepname proc_cen_framelock + * @substepdesc : Initialize EDI Frame + * @target_sched serial + * + * @substepnum 8 + * @substepname cen_set_inband_addr + * @substepdesc : Set the Inband base addresses + * @target_sched serial + * + */ + + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + + +namespace DMI_TRAINING +{ + +/** + * @brief dmi_scominit + * + * 11.1 : Scom setup on centaur + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_dmi_scominit( void * io_pArgs ); + + +/** + * @brief dmi_erepair + * + * 11.2 : Restore EDI Bus eRepair data<@substepdesc> + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_dmi_erepair( void * io_pArgs ); + + +/** + * @brief dmi_io_dccal + * + * 11.3 : Calibrate DMI interfaces + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_dmi_io_dccal( void * io_pArgs ); + + +/** + * @brief dmi_io_run_training + * + * 11.4 : Run training on MC buses + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_dmi_io_run_training( void * io_pArgs ); + + +/** + * @brief host_startPRD_dmi + * + * 11.5 : Start listening for attentions + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_host_startPRD_dmi( void * io_pArgs ); + + +/** + * @brief attnlisten_cen + * + * 11.6 : Set the Inband base addresses + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_host_attnlisten_cen( void * io_pArgs ); + + +/** + * @brief proc_cen_framelock + * + * 11.7 : Initialize EDI Frame + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_proc_cen_framelock( void *io_pArgs ); + + +/** + * @brief cen_set_inband_addr + * + * 11.6 : Set the Inband base addresses + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ +void call_cen_set_inband_addr( void * io_pArgs ); + + +}; // end namespace + +#endif diff --git a/src/usr/hwpf/hwp/dmi_training/makefile b/src/usr/hwpf/hwp/dmi_training/makefile new file mode 100644 index 000000000..3f7c2e213 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/makefile @@ -0,0 +1,52 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/hwas/makefile $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2011 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or other- +# wise divested of its trade secrets, irrespective of what has +# been deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END + +ROOTPATH = ../../../../.. + +MODULE = dmi_training + +## support for Targeting and fapi +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp + +## pointer to common HWP files +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include + +## Include sub dirs +## NOTE: add a new EXTRAINCDIR when you add a new HWP +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training + +OBJS = dmi_training.o \ + proc_cen_framelock.o \ + io_run_training.o gcr_funcs.o io_funcs.o + +## NOTE: add a new directory onto the vpaths when you add a new HWP +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training +## vpath %.C proc_cen_framelock:io_run_training +## vpath %.H proc_cen_framelock:io_run_training + +include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/cen_scom_addresses.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/cen_scom_addresses.H new file mode 100755 index 000000000..1689c244e --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/cen_scom_addresses.H @@ -0,0 +1,421 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/cen_scom_addresses.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: cen_scom_addresses.H,v 1.11 2012/01/06 22:34:45 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : cen_scom_addresses.H +// *! DESCRIPTION : Defines for Centaur chip scom addresses +// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com +// *! BACKUP NAME : Email: @us.ibm.com +// #! ADDITIONAL COMMENTS : +// +// The purpose of this header is to define scom addresses for use by procedures. +// This will help catch address typos at compile time, and will make it easy +// to track down which procedures use each address +// + +#ifndef CEN_SCOM_ADDRESSES +#define CEN_SCOM_ADDRESSES + +//---------------------------------------------------------------------- +// Scom address overview +//---------------------------------------------------------------------- +// Centaur uses 64-bit scom addresses, which are classified into two formats: +// +// "Normal" (legacy) format +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 00000000 00000000 00000000 00000000 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// || | | +// || | `-> Local Address* +// || | +// || `-> Port +// || +// |`-> Chiplet ID** +// | +// `-> Multicast bit +// +// * Local address is composed of "00" + 4-bit ring + 10-bit ID +// The 10-bit ID is usually 4-bit sat_id and 6-bit reg_id +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// +// "Indirect" format +// +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 10000000 0000IIII IIIIIGGG GGGLLLLL 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// | | | || | | +// | | | || | `-> Local Address* +// | | | || | +// | | | || `-> Port +// | | | || +// | | | |`-> Chiplet ID** +// | | | | +// | | | `-> Multicast bit +// | | | +// | | `-> Lane ID +// | | +// | `-> RX or TX Group ID +// | +// `-> Indirect Register Address +// +// * Local address is composed of "00" + 4-bit ring + 4-bit sat_id + "111111" +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// + +#include "common_scom_addresses.H" +#include "fapi_sbe_common.h" + + +/******************************************************************************/ +/********************************** CHIPLET *********************************/ +/******************************************************************************/ +// use for lpcs P0, <chipletID> +CONST_UINT64_T( MEM_CHIPLET_0x03000000 , ULL(0x03000000) ); + + +/******************************************************************************/ +/******************************** TP CHIPLET ********************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// CENTAUR REPAIR LOADER REGISTERS +//------------------------------------------------------------------------------ +CONST_UINT64_T( CEN_WRITE_ARRAY_REPAIR_REG_0x00050000, ULL(0x00050000) ); +CONST_UINT64_T( CEN_WRITE_ARRAY_REPAIR_CMD_0x00050002, ULL(0x00050002) ); +CONST_UINT64_T( CEN_READ_ARRAY_REPAIR_STATUS_0x00050003, ULL(0x00050003) ); +CONST_UINT64_T( CEN_READ_ECC_TRAP_REGISTER_0x00050004, ULL(0x00050004) ); + + +/******************************************************************************/ +/******************************* NEST CHIPLET *******************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// MBU +//------------------------------------------------------------------------------ +// MBI +CONST_UINT64_T( MBI_FIR_0x02010800 , ULL(0x02010800) ); +CONST_UINT64_T( MBI_CFG_0x0201080A , ULL(0x0201080A) ); +CONST_UINT64_T( MBI_STAT_0x0201080B , ULL(0x0201080B) ); + + +/******************************************************************************/ +/****************************** MEM CHIPLET *********************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// MEM GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( MEM_GP0_0x03000000 , ULL(0x03000000) ); +CONST_UINT64_T( MEM_GP1_0x03000001 , ULL(0x03000001) ); +CONST_UINT64_T( MEM_GP2_0x03000002 , ULL(0x03000002) ); +CONST_UINT64_T( MEM_GP4_0x03000003 , ULL(0x03000003) ); +CONST_UINT64_T( MEM_GP0_AND_0x03000004 , ULL(0x03000004) ); +CONST_UINT64_T( MEM_GP0_OR_0x03000005 , ULL(0x03000005) ); +CONST_UINT64_T( MEM_GP4_AND_0x03000006 , ULL(0x03000006) ); +CONST_UINT64_T( MEM_GP4_OR_0x03000007 , ULL(0x03000007) ); + +//------------------------------------------------------------------------------ +// MEM SCOM +//------------------------------------------------------------------------------ +CONST_UINT64_T( MEM_SCOM_0x03010000 , ULL(0x03010000) ); + +CONST_UINT64_T( MEM_MBA01_CCS_MODEQ_0x030106A7 , ULL(0x030106A7) ); +CONST_UINT64_T( MEM_MBA23_CCS_MODEQ_0x03010EA7 , ULL(0x03010EA7) ); + +//------------------------------------------------------------------------------ +// MEM CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( MEM_OPCG_CNTL0_0x03030002 , ULL(0x03030002) ); +CONST_UINT64_T( MEM_OPCG_CNTL1_0x03030003 , ULL(0x03030003) ); +CONST_UINT64_T( MEM_OPCG_CNTL2_0x03030004 , ULL(0x03030004) ); +CONST_UINT64_T( MEM_OPCG_CNTL3_0x03030005 , ULL(0x03030005) ); +CONST_UINT64_T( MEM_CLK_REGION_0x03030006 , ULL(0x03030006) ); +CONST_UINT64_T( MEM_CLK_SCANSEL_0x03030007 , ULL(0x03030007) ); +CONST_UINT64_T( MEM_CLK_STATUS_0x03030008 , ULL(0x03030008) ); + +//------------------------------------------------------------------------------ +// MEM FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( MEM_XSTOP_0x03040000 , ULL(0x03040000) ); +CONST_UINT64_T( MEM_RECOV_0x03040001 , ULL(0x03040001) ); +CONST_UINT64_T( MEM_FIR_MASK_0x03040002 , ULL(0x03040002) ); +CONST_UINT64_T( MEM_SPATTN_0x03040004 , ULL(0x03040004) ); +CONST_UINT64_T( MEM_SPATTN_AND_0x03040005 , ULL(0x03040005) ); +CONST_UINT64_T( MEM_SPATTN_OR_0x03040006 , ULL(0x03040006) ); +CONST_UINT64_T( MEM_SPATTN_MASK_0x03040007 , ULL(0x03040007) ); +CONST_UINT64_T( MEM_FIR_MODE_0x03040008 , ULL(0x03040008) ); +CONST_UINT64_T( MEM_PERV_LFIR_0x0304000A , ULL(0x0304000A) ); +CONST_UINT64_T( MEM_PERV_LFIR_AND_0x0304000B , ULL(0x0304000B) ); +CONST_UINT64_T( MEM_PERV_LFIR_OR_0x0304000C , ULL(0x0304000C) ); +CONST_UINT64_T( MEM_PERV_LFIR_MASK_0x0304000D , ULL(0x0304000D) ); +CONST_UINT64_T( MEM_PERV_LFIR_MASK_AND_0x0304000E , ULL(0x0304000E) ); +CONST_UINT64_T( MEM_PERV_LFIR_MASK_OR_0x0304000F , ULL(0x0304000F) ); +CONST_UINT64_T( MEM_PERV_LFIR_ACT0_0x03040010 , ULL(0x03040010) ); +CONST_UINT64_T( MEM_PERV_LFIR_ACT1_0x03040011 , ULL(0x03040011) ); + +//------------------------------------------------------------------------------ +// MEM THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( MEM_THERM_0x03050000 , ULL(0x03050000) ); + +//------------------------------------------------------------------------------ +// MEM PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( MEM_MCGR1_0x030F0001 , ULL(0x030F0001) ); +CONST_UINT64_T( MEM_MCGR2_0x030F0002 , ULL(0x030F0002) ); +CONST_UINT64_T( MEM_MCGR3_0x030F0003 , ULL(0x030F0003) ); +CONST_UINT64_T( MEM_MCGR4_0x030F0004 , ULL(0x030F0004) ); +//GP3 Register +CONST_UINT64_T( MEM_GP3_0x030F0012 , ULL(0x030F0012) ); +CONST_UINT64_T( MEM_GP3_AND_0x030F0013 , ULL(0x030F0013) ); +CONST_UINT64_T( MEM_GP3_OR_0x030F0014 , ULL(0x030F0014) ); + +//------------------------------------------------------------------------------ +// MEM CHIPLET INDIRECT SCOM ADDRESSES (DPHY REGISTERS) +//------------------------------------------------------------------------------ +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, ULL(0x800000070301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, ULL(0x800100070301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301183F, ULL(0x800000070301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301183F, ULL(0x800100070301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_0_0x800000760301143F, ULL(0x800000760301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_0_0x800100760301143F, ULL(0x800100760301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_0_0x800000760301183F, ULL(0x800000760301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_0_0x800100760301183F, ULL(0x800100760301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_0_0x800000770301143F, ULL(0x800000770301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_0_0x800100770301143F, ULL(0x800100770301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_0_0x800000770301183F, ULL(0x800000770301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_0_0x800100770301183F, ULL(0x800100770301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, ULL(0x800004070301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, ULL(0x800104070301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301183F, ULL(0x800004070301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301183F, ULL(0x800104070301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_1_0x800004760301143F, ULL(0x800004760301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_1_0x800104760301143F, ULL(0x800104760301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_1_0x800004760301183F, ULL(0x800004760301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_1_0x800104760301183F, ULL(0x800104760301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_1_0x800004770301143F, ULL(0x800004770301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_1_0x800104770301143F, ULL(0x800104770301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_1_0x800004770301183F, ULL(0x800004770301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_1_0x800104770301183F, ULL(0x800104770301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, ULL(0x800008070301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, ULL(0x800108070301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301183F, ULL(0x800008070301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301183F, ULL(0x800108070301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_2_0x800008760301143F, ULL(0x800008760301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_2_0x800108760301143F, ULL(0x800108760301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_2_0x800008760301183F, ULL(0x800008760301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_2_0x800108760301183F, ULL(0x800108760301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_2_0x800008770301143F, ULL(0x800008770301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_2_0x800108770301143F, ULL(0x800108770301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_2_0x800008770301183F, ULL(0x800008770301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_2_0x800108770301183F, ULL(0x800108770301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, ULL(0x80000C070301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, ULL(0x80010C070301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301183F, ULL(0x80000C070301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301183F, ULL(0x80010C070301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_3_0x80000C760301143F, ULL(0x80000C760301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_3_0x80010C760301143F, ULL(0x80010C760301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_3_0x80000C760301183F, ULL(0x80000C760301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_3_0x80010C760301183F, ULL(0x80010C760301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_3_0x80000C770301143F, ULL(0x80000C770301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_3_0x80010C770301143F, ULL(0x80010C770301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_3_0x80000C770301183F, ULL(0x80000C770301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_3_0x80010C770301183F, ULL(0x80010C770301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, ULL(0x800010070301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, ULL(0x800110070301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301183F, ULL(0x800010070301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301183F, ULL(0x800110070301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_4_0x800010760301143F, ULL(0x800010760301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_4_0x800110760301143F, ULL(0x800110760301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_4_0x800010760301183F, ULL(0x800010760301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_4_0x800110760301183F, ULL(0x800110760301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_4_0x800010770301143F, ULL(0x800010770301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_4_0x800110770301143F, ULL(0x800110770301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_4_0x800010770301183F, ULL(0x800010770301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_4_0x800110770301183F, ULL(0x800110770301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_0x800080300301143F, ULL(0x800080300301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_0x800180300301143F, ULL(0x800180300301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_0x800080300301183F, ULL(0x800080300301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_0x800180300301183F, ULL(0x800180300301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_0x800080310301143F, ULL(0x800080310301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_0x800180310301143F, ULL(0x800180310301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_0x800080310301183F, ULL(0x800080310301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_0x800180310301183F, ULL(0x800180310301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, ULL(0x800080320301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, ULL(0x800180320301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301183F, ULL(0x800080320301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301183F, ULL(0x800180320301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_0x800084300301143F, ULL(0x800084300301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_0x800184300301143F, ULL(0x800184300301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_0x800084300301183F, ULL(0x800084300301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_0x800184300301183F, ULL(0x800184300301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_0x800084310301143F, ULL(0x800084310301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_0x800184310301143F, ULL(0x800184310301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_0x800084310301183F, ULL(0x800084310301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_0x800184310301183F, ULL(0x800184310301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, ULL(0x800084320301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, ULL(0x800184320301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301183F, ULL(0x800084320301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301183F, ULL(0x800184320301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301143F, ULL(0x8000C0000301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301143F, ULL(0x8001C0000301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301183F, ULL(0x8000C0000301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301183F, ULL(0x8001C0000301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301143F, ULL(0x8000C0010301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301143F, ULL(0x8001C0010301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301183F, ULL(0x8000C0010301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301183F, ULL(0x8001C0010301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_CONFIG0_P0_0x8000C00C0301143F, ULL(0x8000C00C0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_CONFIG0_P1_0x8001C00C0301143F, ULL(0x8001C00C0301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_CONFIG0_P0_0x8000C00C0301183F, ULL(0x8000C00C0301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_CONFIG0_P1_0x8001C00C0301183F, ULL(0x8001C00C0301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, ULL(0x8000C00E0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, ULL(0x8001C00E0301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_RESETS_P0_0x8000C00E0301183F, ULL(0x8000C00E0301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_RESETS_P1_0x8001C00E0301183F, ULL(0x8001C00E0301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, ULL(0x8000C0140301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, ULL(0x8001C0140301143F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301183F, ULL(0x8000C0140301183F) ); +CONST_UINT64_T( DPHY23_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301183F, ULL(0x8001C0140301183F) ); + + +/******************************************************************************/ +/********* MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/ +/******************************************************************************/ +CONST_UINT64_T( READ_OR_ALL_FUNC_GP0_0x41000000 , ULL(0x41000000) ); // group1: all except PRV: GP0 +CONST_UINT64_T( READ_OR_ALL_FUNC_GP1_0x41000001 , ULL(0x41000001) ); // group1: all except PRV: GP1 +CONST_UINT64_T( READ_OR_ALL_FUNC_GP2_0x41000002 , ULL(0x41000002) ); // group1: all except PRV: GP2 +CONST_UINT64_T( READ_OR_ALL_FUNC_GP4_0x41000003 , ULL(0x41000003) ); // group1: all except PRV: GP4 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL0_0x41030002 , ULL(0x41030002) ); // group1: all except PRV: OPCG_CNTL0 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL1_0x41030003 , ULL(0x41030003) ); // group1: all except PRV: OPCG_CNTL1 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL2_0x41030004 , ULL(0x41030004) ); // group1: all except PRV: OPCG_CNTL2 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL3_0x41030005 , ULL(0x41030005) ); // group1: all except PRV: OPCG_CNTL3 +CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_REGION_0x41030006 , ULL(0x41030006) ); // group1: all except PRV: CLK_REGION +CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_SCANSEL_0x41030007 , ULL(0x41030007) ); // group1: all except PRV: CLK_SCANSEL +CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_STATUS_0x41030008 , ULL(0x41030008) ); // group1: all except PRV: CLK_STATUS +CONST_UINT64_T( READ_OR_ALL_FUNC_GP3_0x410F0012 , ULL(0x410F0012) ); // group1: all except PRV: GP3 +CONST_UINT64_T( READ_OR_ALL_PCB_SLAVE_ERRREG_0x410F001F , ULL(0x410F001F) ); // group1: all except PRV: + +CONST_UINT64_T( READ_AND_ALL_FUNC_GP0_0x49000000 , ULL(0x49000000) ); // group1: all except PRV: GP0 +CONST_UINT64_T( READ_AND_ALL_FUNC_GP1_0x49000001 , ULL(0x49000001) ); // group1: all except PRV: GP1 +CONST_UINT64_T( READ_AND_ALL_FUNC_GP2_0x49000002 , ULL(0x49000002) ); // group1: all except PRV: GP2 +CONST_UINT64_T( READ_AND_ALL_FUNC_GP4_0x49000003 , ULL(0x49000003) ); // group1: all except PRV: GP4 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL0_0x49030002 , ULL(0x49030002) ); // group1: all except PRV: OPCG_CNTL0 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL1_0x49030003 , ULL(0x49030003) ); // group1: all except PRV: OPCG_CNTL1 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL2_0x49030004 , ULL(0x49030004) ); // group1: all except PRV: OPCG_CNTL2 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL3_0x49030005 , ULL(0x49030005) ); // group1: all except PRV: OPCG_CNTL3 +CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_REGION_0x49030006 , ULL(0x49030006) ); // group1: all except PRV: CLK_REGION +CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_SCANSEL_0x49030007 , ULL(0x49030007) ); // group1: all except PRV: CLK_SCANSEL +CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_STATUS_0x49030008 , ULL(0x49030008) ); // group1: all except PRV: CLK_STATUS +CONST_UINT64_T( READ_AND_ALL_FUNC_GP3_0x490F0012 , ULL(0x490F0012) ); // group1: all except PRV: GP3 +CONST_UINT64_T( READ_AND_ALL_PCB_SLAVE_ERRREG_0x490F001F , ULL(0x490F001F) ); // group1: all except PRV: + +CONST_UINT64_T( WRITE_ALL_FUNC_GP0_0x69000000 , ULL(0x69000000) ); // group1: all except PRV: GP0 +CONST_UINT64_T( WRITE_ALL_FUNC_GP1_0x69000001 , ULL(0x69000001) ); // group1: all except PRV: GP1 +CONST_UINT64_T( WRITE_ALL_FUNC_GP2_0x69000002 , ULL(0x69000002) ); // group1: all except PRV: GP2 +CONST_UINT64_T( WRITE_ALL_FUNC_GP4_0x69000003 , ULL(0x69000003) ); // group1: all except PRV: GP4 +CONST_UINT64_T( WRITE_ALL_FUNC_GP0_AND_0x69000004 , ULL(0x69000004) ); // group1: all except PRV: GP0 AND (for clearing bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP0_OR_0x69000005 , ULL(0x69000005) ); // group1: all except PRV: GP0 OR (for setting bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP4_AND_0x69000006 , ULL(0x69000006) ); // group1: all except PRV: GP4 AND (for clearing bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP4_OR_0x69000007 , ULL(0x69000007) ); // group1: all except PRV: GP4 OR (for setting bits) +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL0_0x69030002 , ULL(0x69030002) ); // group1: all except PRV: OPCG_CNTL0 +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL1_0x69030003 , ULL(0x69030003) ); // group1: all except PRV: OPCG_CNTL1 +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL2_0x69030004 , ULL(0x69030004) ); // group1: all except PRV: OPCG_CNTL2 +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL3_0x69030005 , ULL(0x69030005) ); // group1: all except PRV: OPCG_CNTL3 +CONST_UINT64_T( WRITE_ALL_FUNC_CLK_REGION_0x69030006 , ULL(0x69030006) ); // group1: all except PRV: CLK_REGION +CONST_UINT64_T( WRITE_ALL_FUNC_CLK_SCANSEL_0x69030007 , ULL(0x69030007) ); // group1: all except PRV: CLK_SCANSEL +CONST_UINT64_T( WRITE_ALL_FUNC_CLK_STATUS_0x69030008 , ULL(0x69030008) ); // group1: all except PRV: CLK_STATUS +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_0x690F0012 , ULL(0x690F0012) ); // group1: all except PRV: GP3 +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_AND_0x690F0013 , ULL(0x690F0013) ); // group1: all except PRV: GP3 AND (for clearing bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_OR_0x690F0014 , ULL(0x690F0014) ); // group1: all except PRV: GP3 OR (for setting bits) +CONST_UINT64_T( WRITE_ALL_PCB_SLAVE_ERRREG_0x690F001F , ULL(0x690F001F) ); // group1: all except PRV: + +//******************************************************************************/ +//********* ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/ +//******************************************************************************/ + +CONST_UINT8_T( READ_OR_ALL_CHIPLETS, ULL(0x40) ); // group 0: TP, MEM, NEST +CONST_UINT8_T( READ_OR_ALL_FUNC_CHIPLETS, ULL(0x41) ); // group 1: MEM, NEST// CONST_UINT8_T( READ_AND_ALL_CHIPLETS, ULL(0x48) ); // group 0: TP, MEM, NEST +CONST_UINT8_T( READ_AND_ALL_FUNC_CHIPLETS, ULL(0x49) ); // group 1: MEM, NEST +CONST_UINT8_T( WRITE_ALL_CHIPLETS, ULL(0x68) ); // group 0: TP, MEM, NEST +CONST_UINT8_T( WRITE_ALL_FUNC_CHIPLETS, ULL(0x69) ); // group 1: MEM, NEST + + +#endif + + +/* +*************** Do not edit this area *************** +This section is automatically updated by CVS when you check in this file. +Be sure to create CVS comments when you commit so that they can be included here. + +$Log: cen_scom_addresses.H,v $ +Revision 1.11 2012/01/06 22:34:45 jmcgill +move shared/common addresses to common_scom_addresses.H, general cleanup + +Revision 1.10 2011/10/26 21:37:03 mfred +Fix error. Extra space in an address was causing compile failure. + +Revision 1.9 2011/10/25 22:53:46 mfred +Added MEM chiplet indirect scom addresses (DPHY registers). + +Revision 1.8 2011/09/20 15:51:30 venton +Add missing SCOMs from P8 + +Revision 1.7 2011/08/02 20:28:40 mfred +added some 8-bit constants for use with P0 and P1 + +Revision 1.6 2011/07/28 14:44:51 mfred +Added more multicast addresses. + +Revision 1.5 2011/07/27 20:08:01 mfred +Added multicast addresses for OPCG, etc. + +Revision 1.3 2011/07/25 13:03:53 gweber +moved centaur constants from p8_scom_addresses.H + +Revision 1.2 2011/07/13 18:35:13 mfred +Get rid of some temp lines and comments. + +Revision 1.1 2011/07/07 13:07:52 mfred +Adding first version of scom address file. Was created from P8 version. + + + + +*/ diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/fapi_sbe_common.h b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/fapi_sbe_common.h new file mode 100644 index 000000000..2ad5b7bda --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/fapi_sbe_common.h @@ -0,0 +1,62 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/fapi_sbe_common.h $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +#ifndef __FAPI_SBE_COMMON_H +#define __FAPI_SBE_COMMON_H + +// $Id: fapi_sbe_common.h,v 1.1 2011/07/06 04:06:49 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/fapi_sbe_common.h,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME : Email: + +/// \file fapi_sbe_common.h +/// \brief Definitions common to FAPI and SBE procedures +/// +/// Several preprocessor macros are required to have different definitions in +/// traditional C, C++ and SBE assembly procedures. These common forms are +/// collected here. + +#ifdef __ASSEMBLER__ + +#define CONST_UINT8_T(name, expr) .set name, (expr) +#define CONST_UINT32_T(name, expr) .set name, (expr) +#define CONST_UINT64_T(name, expr) .set name, (expr) + +#define ULL(x) x + +#else + +#include <stdint.h> + +#define CONST_UINT8_T(name, expr) const uint8_t name = (expr); +#define CONST_UINT32_T(name, expr) const uint32_t name = (expr); +#define CONST_UINT64_T(name, expr) const uint64_t name = (expr); + +#define ULL(x) x##ull + +#endif // __ASSEMBLER__ + +#endif // __FAPI_SBE_COMMON_H diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/p8_scom_addresses.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/p8_scom_addresses.H new file mode 100755 index 000000000..17b672b30 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/p8_scom_addresses.H @@ -0,0 +1,1201 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/p8_scom_addresses.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: p8_scom_addresses.H,v 1.50 2012/01/06 22:20:53 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : p8_scom_addresses.H +// *! DESCRIPTION : Defines for P8 scom addresses +// *! OWNER NAME : Jeshua Smith Email: jeshua@us.ibm.com +// *! BACKUP NAME : Email: @us.ibm.com +// #! ADDITIONAL COMMENTS : +// +// The purpose of this header is to define scom addresses for use by procedures. +// This will help catch address typos at compile time, and will make it easy +// to track down which procedures use each address +// + +#ifndef P8_SCOM_ADDRESSES +#define P8_SCOM_ADDRESSES + +//---------------------------------------------------------------------- +// Scom address overview +//---------------------------------------------------------------------- +// P8 uses 64-bit scom addresses, which are classified into two formats: +// +// "Normal" (legacy) format +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 00000000 00000000 00000000 00000000 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// || | | +// || | `-> Local Address* +// || | +// || `-> Port +// || +// |`-> Chiplet ID** +// | +// `-> Multicast bit +// +// * Local address is composed of "00" + 4-bit ring + 10-bit ID +// The 10-bit ID is usually 4-bit sat_id and 6-bit reg_id +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// +// "Indirect" format +// +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 10000000 0000IIII IIIIIGGG GGGLLLLL 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// | | | || | | +// | | | || | `-> Local Address* +// | | | || | +// | | | || `-> Port +// | | | || +// | | | |`-> Chiplet ID** +// | | | | +// | | | `-> Multicast bit +// | | | +// | | `-> Lane ID +// | | +// | `-> RX or TX Group ID +// | +// `-> Indirect Register Address +// +// * Local address is composed of "00" + 4-bit ring + 4-bit sat_id + "111111" +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// + +#include "common_scom_addresses.H" +#include "fapi_sbe_common.h" + +/******************************************************************************/ +/********************************** CHIPLET *********************************/ +/******************************************************************************/ +// use for lpcs P0, <chipletID> +CONST_UINT64_T( X_BUS_CHIPLET_0x04000000 , ULL(0x04000000) ); +CONST_UINT64_T( PCIE_CHIPLET_0x08000000 , ULL(0x08000000) ); +CONST_UINT64_T( A_BUS_CHIPLET_0x09000000 , ULL(0x09000000) ); +// EX00_CHIPLET - EX15_CHIPLET defined in the EX CHIPLET section +// "Multicast" chiplets +CONST_UINT64_T( ALL_CHIPLETS_OR_0x40000000 , ULL(0x40000000) ); +CONST_UINT64_T( ALL_CHIPLETS_AND_0x48000000 , ULL(0x48000000) ); +CONST_UINT64_T( ALL_CHIPLETS_BITX_0x50000000 , ULL(0x50000000) ); +CONST_UINT64_T( ALL_CHIPLETS_COMP_0x60000000 , ULL(0x60000000) ); +CONST_UINT64_T( ALL_CHIPLETS_WRITE_0x68000000 , ULL(0x68000000) ); + +CONST_UINT64_T( ALL_EXS_OR_0x41000000 , ULL(0x41000000) ); +CONST_UINT64_T( ALL_EXS_AND_0x49000000 , ULL(0x49000000) ); +CONST_UINT64_T( ALL_EXS_BITX_0x51000000 , ULL(0x51000000) ); +CONST_UINT64_T( ALL_EXS_COMP_0x61000000 , ULL(0x61000000) ); +CONST_UINT64_T( ALL_EXS_WRITE_0x69000000 , ULL(0x69000000) ); + +CONST_UINT64_T( ALL_CORES_OR_0x42000000 , ULL(0x42000000) ); +CONST_UINT64_T( ALL_CORES_AND_0x4A000000 , ULL(0x4A000000) ); +CONST_UINT64_T( ALL_CORES_BITX_0x52000000 , ULL(0x52000000) ); +CONST_UINT64_T( ALL_CORES_COMP_0x62000000 , ULL(0x62000000) ); +CONST_UINT64_T( ALL_CORES_WRITE_0x6A000000 , ULL(0x6A000000) ); + + +/******************************************************************************/ +/******************************** TP CHIPLET ********************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// PORE-GPE0 +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_GPE0_0x00060000 , ULL(0x00060000) ); +CONST_UINT64_T( PORE_GPE0_STATUS_0x00060000 , ULL(0x00060000) ); +CONST_UINT64_T( PORE_GPE0_CONTROL_0x00060001 , ULL(0x00060001) ); +CONST_UINT64_T( PORE_GPE0_RESET_0x00060002 , ULL(0x00060002) ); +CONST_UINT64_T( PORE_GPE0_ERROR_MASK_0x00060003 , ULL(0x00060003) ); +CONST_UINT64_T( PORE_GPE0_PRV_BASE_ADDRESS0_0x00060004 , ULL(0x00060004) ); +CONST_UINT64_T( PORE_GPE0_PRV_BASE_ADDRESS1_0x00060005 , ULL(0x00060005) ); +CONST_UINT64_T( PORE_GPE0_OCI_BASE_ADDRESS0_0x00060006 , ULL(0x00060006) ); +CONST_UINT64_T( PORE_GPE0_OCI_BASE_ADDRESS1_0x00060007 , ULL(0x00060007) ); +CONST_UINT64_T( PORE_GPE0_TABLE_BASE_ADDR_0x00060008 , ULL(0x00060008) ); +CONST_UINT64_T( PORE_GPE0_EXE_TRIGGER_0x00060009 , ULL(0x00060009) ); +CONST_UINT64_T( PORE_GPE0_SCRATCH0_0x0006000A , ULL(0x0006000A) ); +CONST_UINT64_T( PORE_GPE0_SCRATCH1_0x0006000B , ULL(0x0006000B) ); +CONST_UINT64_T( PORE_GPE0_SCRATCH2_0x0006000C , ULL(0x0006000C) ); +CONST_UINT64_T( PORE_GPE0_IBUF_01_0x0006000D , ULL(0x0006000D) ); +CONST_UINT64_T( PORE_GPE0_IBUF_2_0x0006000E , ULL(0x0006000E) ); +CONST_UINT64_T( PORE_GPE0_DBG0_0x0006000F , ULL(0x0006000F) ); +CONST_UINT64_T( PORE_GPE0_DBG1_0x00060010 , ULL(0x00060010) ); +CONST_UINT64_T( PORE_GPE0_PC_STACK0_0x00060011 , ULL(0x00060011) ); +CONST_UINT64_T( PORE_GPE0_PC_STACK1_0x00060012 , ULL(0x00060012) ); +CONST_UINT64_T( PORE_GPE0_PC_STACK2_0x00060013 , ULL(0x00060013) ); +CONST_UINT64_T( PORE_GPE0_ID_FLAGS_0x00060014 , ULL(0x00060014) ); +CONST_UINT64_T( PORE_GPE0_DATA0_0x00060015 , ULL(0x00060015) ); +CONST_UINT64_T( PORE_GPE0_MEMORY_RELOC_0x00060016 , ULL(0x00060016) ); +CONST_UINT64_T( PORE_GPE0_I2C_E0_PARAM_0x00060017 , ULL(0x00060017) ); +CONST_UINT64_T( PORE_GPE0_I2C_E1_PARAM_0x00060018 , ULL(0x00060018) ); +CONST_UINT64_T( PORE_GPE0_I2C_E2_PARAM_0x00060019 , ULL(0x00060019) ); + +//------------------------------------------------------------------------------ +// PORE-GPE1 +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_GPE1_0x00060020 , ULL(0x00060020) ); +CONST_UINT64_T( PORE_GPE1_STATUS_0x00060020 , ULL(0x00060020) ); +CONST_UINT64_T( PORE_GPE1_CONTROL_0x00060021 , ULL(0x00060021) ); +CONST_UINT64_T( PORE_GPE1_RESET_0x00060022 , ULL(0x00060022) ); +CONST_UINT64_T( PORE_GPE1_ERROR_MASK_0x00060023 , ULL(0x00060023) ); +CONST_UINT64_T( PORE_GPE1_PRV_BASE_ADDRESS0_0x00060024 , ULL(0x00060024) ); +CONST_UINT64_T( PORE_GPE1_PRV_BASE_ADDRESS1_0x00060025 , ULL(0x00060025) ); +CONST_UINT64_T( PORE_GPE1_OCI_BASE_ADDRESS0_0x00060026 , ULL(0x00060026) ); +CONST_UINT64_T( PORE_GPE1_OCI_BASE_ADDRESS1_0x00060027 , ULL(0x00060027) ); +CONST_UINT64_T( PORE_GPE1_TABLE_BASE_ADDR_0x00060028 , ULL(0x00060028) ); +CONST_UINT64_T( PORE_GPE1_EXE_TRIGGER_0x00060029 , ULL(0x00060029) ); +CONST_UINT64_T( PORE_GPE1_SCRATCH0_0x0006002A , ULL(0x0006002A) ); +CONST_UINT64_T( PORE_GPE1_SCRATCH1_0x0006002B , ULL(0x0006002B) ); +CONST_UINT64_T( PORE_GPE1_SCRATCH2_0x0006002C , ULL(0x0006002C) ); +CONST_UINT64_T( PORE_GPE1_IBUF_01_0x0006002D , ULL(0x0006002D) ); +CONST_UINT64_T( PORE_GPE1_IBUF_2_0x0006002E , ULL(0x0006002E) ); +CONST_UINT64_T( PORE_GPE1_DBG0_0x0006002F , ULL(0x0006002F) ); +CONST_UINT64_T( PORE_GPE1_DBG1_0x00060030 , ULL(0x00060030) ); +CONST_UINT64_T( PORE_GPE1_PC_STACK0_0x00060031 , ULL(0x00060031) ); +CONST_UINT64_T( PORE_GPE1_PC_STACK1_0x00060032 , ULL(0x00060032) ); +CONST_UINT64_T( PORE_GPE1_PC_STACK2_0x00060033 , ULL(0x00060033) ); +CONST_UINT64_T( PORE_GPE1_ID_FLAGS_0x00060034 , ULL(0x00060034) ); +CONST_UINT64_T( PORE_GPE1_DATA0_0x00060035 , ULL(0x00060035) ); +CONST_UINT64_T( PORE_GPE1_MEMORY_RELOC_0x00060036 , ULL(0x00060036) ); +CONST_UINT64_T( PORE_GPE1_I2C_E0_PARAM_0x00060037 , ULL(0x00060037) ); +CONST_UINT64_T( PORE_GPE1_I2C_E1_PARAM_0x00060038 , ULL(0x00060038) ); +CONST_UINT64_T( PORE_GPE1_I2C_E2_PARAM_0x00060039 , ULL(0x00060039) ); + +//------------------------------------------------------------------------------ +// PORE-SLW +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_SLW_0x00068000 , ULL(0x00068000) ); +CONST_UINT64_T( PORE_SLW_STATUS_0x00068000 , ULL(0x00068000) ); +CONST_UINT64_T( PORE_SLW_CONTROL_0x00068001 , ULL(0x00068001) ); +CONST_UINT64_T( PORE_SLW_RESET_0x00068002 , ULL(0x00068002) ); +CONST_UINT64_T( PORE_SLW_ERROR_MASK_0x00068003 , ULL(0x00068003) ); +CONST_UINT64_T( PORE_SLW_PRV_BASE_ADDRESS0_0x00068004 , ULL(0x00068004) ); +CONST_UINT64_T( PORE_SLW_PRV_BASE_ADDRESS1_0x00068005 , ULL(0x00068005) ); +CONST_UINT64_T( PORE_SLW_OCI_BASE_ADDRESS0_0x00068006 , ULL(0x00068006) ); +CONST_UINT64_T( PORE_SLW_OCI_BASE_ADDRESS1_0x00068007 , ULL(0x00068007) ); +CONST_UINT64_T( PORE_SLW_TABLE_BASE_ADDR_0x00068008 , ULL(0x00068008) ); +CONST_UINT64_T( PORE_SLW_EXE_TRIGGER_0x00068009 , ULL(0x00068009) ); +CONST_UINT64_T( PORE_SLW_SCRATCH0_0x0006800A , ULL(0x0006800A) ); +CONST_UINT64_T( PORE_SLW_SCRATCH1_0x0006800B , ULL(0x0006800B) ); +CONST_UINT64_T( PORE_SLW_SCRATCH2_0x0006800C , ULL(0x0006800C) ); +CONST_UINT64_T( PORE_SLW_IBUF_01_0x0006800D , ULL(0x0006800D) ); +CONST_UINT64_T( PORE_SLW_IBUF_2_0x0006800E , ULL(0x0006800E) ); +CONST_UINT64_T( PORE_SLW_DBG0_0x0006800F , ULL(0x0006800F) ); +CONST_UINT64_T( PORE_SLW_DBG1_0x00068010 , ULL(0x00068010) ); +CONST_UINT64_T( PORE_SLW_PC_STACK0_0x00068011 , ULL(0x00068011) ); +CONST_UINT64_T( PORE_SLW_PC_STACK1_0x00068012 , ULL(0x00068012) ); +CONST_UINT64_T( PORE_SLW_PC_STACK2_0x00068013 , ULL(0x00068013) ); +CONST_UINT64_T( PORE_SLW_ID_FLAGS_0x00068014 , ULL(0x00068014) ); +CONST_UINT64_T( PORE_SLW_DATA0_0x00068015 , ULL(0x00068015) ); +CONST_UINT64_T( PORE_SLW_MEMORY_RELOC_0x00068016 , ULL(0x00068016) ); +CONST_UINT64_T( PORE_SLW_I2C_E0_PARAM_0x00068017 , ULL(0x00068017) ); +CONST_UINT64_T( PORE_SLW_I2C_E1_PARAM_0x00068018 , ULL(0x00068018) ); +CONST_UINT64_T( PORE_SLW_I2C_E2_PARAM_0x00068019 , ULL(0x00068019) ); + +//------------------------------------------------------------------------------ +// OCC/OCB +//------------------------------------------------------------------------------ +CONST_UINT64_T( OCC_CONTROL_0x0006B000 , ULL(0x0006B000) ); +CONST_UINT64_T( OCC_CONTROL_AND_0x0006B001 , ULL(0x0006B001) ); +CONST_UINT64_T( OCC_CONTROL_OR_0x0006B002 , ULL(0x0006B002) ); +CONST_UINT64_T( OCC_DEBUG_MODE_0x0006B003 , ULL(0x0006B003) ); + +CONST_UINT64_T( OCB0_ADDRESS_0x0006B010 , ULL(0x0006B010) ); +CONST_UINT64_T( OCB0_STATUS_CONTROL_0x0006B011 , ULL(0x0006B011) ); +CONST_UINT64_T( OCB0_STATUS_CONTROL_AND_0x0006B012 , ULL(0x0006B012) ); +CONST_UINT64_T( OCB0_STATUS_CONTROL_OR_0x0006B013 , ULL(0x0006B013) ); +CONST_UINT64_T( OCB0_ERROR_STATUS_0x0006B014 , ULL(0x0006B014) ); +CONST_UINT64_T( OCB0_DATA_0x0006B015 , ULL(0x0006B015) ); + +CONST_UINT64_T( OCB1_ADDRESS_0x0006B030 , ULL(0x0006B030) ); +CONST_UINT64_T( OCB1_STATUS_CONTROL_0x0006B031 , ULL(0x0006B031) ); +CONST_UINT64_T( OCB1_STATUS_CONTROL_AND_0x0006B032 , ULL(0x0006B032) ); +CONST_UINT64_T( OCB1_STATUS_CONTROL_OR_0x0006B032 , ULL(0x0006B033) ); +CONST_UINT64_T( OCB1_ERROR_STATUS_0x0006B034 , ULL(0x0006B034) ); +CONST_UINT64_T( OCB1_DATA_0x0006B035 , ULL(0x0006B035) ); + +CONST_UINT64_T( OCB2_ADDRESS_0x0006B050 , ULL(0x0006B050) ); +CONST_UINT64_T( OCB2_STATUS_CONTROL_0x0006B051 , ULL(0x0006B051) ); +CONST_UINT64_T( OCB2_STATUS_CONTROL_AND_0x0006B052 , ULL(0x0006B052) ); +CONST_UINT64_T( OCB2_STATUS_CONTROL_OR_0x0006B052 , ULL(0x0006B053) ); +CONST_UINT64_T( OCB2_ERROR_STATUS_0x0006B054 , ULL(0x0006B054) ); +CONST_UINT64_T( OCB2_DATA_0x0006B055 , ULL(0x0006B055) ); + +CONST_UINT64_T( OCB3_ADDRESS_0x0006B070 , ULL(0x0006B070) ); +CONST_UINT64_T( OCB3_STATUS_CONTROL_0x0006B071 , ULL(0x0006B071) ); +CONST_UINT64_T( OCB3_STATUS_CONTROL_AND_0x0006B072 , ULL(0x0006B072) ); +CONST_UINT64_T( OCB3_STATUS_CONTROL_OR_0x0006B072 , ULL(0x0006B073) ); +CONST_UINT64_T( OCB3_ERROR_STATUS_0x0006B074 , ULL(0x0006B074) ); +CONST_UINT64_T( OCB3_DATA_0x0006B075 , ULL(0x0006B075) ); + +//------------------------------------------------------------------------------ +// SPIADC +//------------------------------------------------------------------------------ +CONST_UINT64_T( SPIADC_0x00070000 , ULL(0x00070000) ); + +//------------------------------------------------------------------------------ +// PIB-ATTACHED MEMORY +//------------------------------------------------------------------------------ +CONST_UINT64_T( PIBMEM0_0x00080000 , ULL(0x00080000) ); + +//------------------------------------------------------------------------------ +// I2C MASTER (MEMS1) +//------------------------------------------------------------------------------ +CONST_UINT64_T( I2CMS_MEMS1_CONTROL_0x000A0020 , ULL(0x000A0020) ); +CONST_UINT64_T( I2CMS_MEMS1_RESET_0x000A0021 , ULL(0x000A0021) ); +CONST_UINT64_T( I2CMS_MEMS1_STATUS_0x000A0022 , ULL(0x000A0022) ); +CONST_UINT64_T( I2CMS_MEMS1_DATA_0x000A0023 , ULL(0x000A0023) ); +CONST_UINT64_T( I2CMS_MEMS1_COMMAND_0x000A0025 , ULL(0x000A0025) ); + +//------------------------------------------------------------------------------ +// I2C MASTER (PCI) +//------------------------------------------------------------------------------ +CONST_UINT64_T( I2CMS_PCI_0x000A0040 , ULL(0x000A0040) ); +CONST_UINT64_T( I2CMS_PCI_CONTROL_0x000A0040 , ULL(0x000A0040) ); +CONST_UINT64_T( I2CMS_PCI_RESET_0x000A0041 , ULL(0x000A0041) ); +CONST_UINT64_T( I2CMS_PCI_STATUS_0x000A0042 , ULL(0x000A0042) ); +CONST_UINT64_T( I2CMS_PCI_DATA_0x000A0043 , ULL(0x000A0043) ); +CONST_UINT64_T( I2CMS_PCI_COMMAND_0x000A0045 , ULL(0x000A0045) ); + +//------------------------------------------------------------------------------ +// PORE-SBE +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_SBE_0x000E0000 , ULL(0x000E0000) ); +CONST_UINT64_T( PORE_SBE_STATUS_0x000E0000 , ULL(0x000E0000) ); +CONST_UINT64_T( PORE_SBE_CONTROL_0x000E0001 , ULL(0x000E0001) ); +CONST_UINT64_T( PORE_SBE_RESET_0x000E0002 , ULL(0x000E0002) ); +CONST_UINT64_T( PORE_SBE_ERROR_MASK_0x000E0003 , ULL(0x000E0003) ); +CONST_UINT64_T( PORE_SBE_PRV_BASE_ADDRESS0_0x000E0004 , ULL(0x000E0004) ); +CONST_UINT64_T( PORE_SBE_PRV_BASE_ADDRESS1_0x000E0005 , ULL(0x000E0005) ); +CONST_UINT64_T( PORE_SBE_OCI_BASE_ADDRESS0_0x000E0006 , ULL(0x000E0006) ); +CONST_UINT64_T( PORE_SBE_OCI_BASE_ADDRESS1_0x000E0007 , ULL(0x000E0007) ); +CONST_UINT64_T( PORE_SBE_TABLE_BASE_ADDR_0x000E0008 , ULL(0x000E0008) ); +CONST_UINT64_T( PORE_SBE_EXE_TRIGGER_0x000E0009 , ULL(0x000E0009) ); +CONST_UINT64_T( PORE_SBE_SCRATCH0_0x000E000A , ULL(0x000E000A) ); +CONST_UINT64_T( PORE_SBE_SCRATCH1_0x000E000B , ULL(0x000E000B) ); +CONST_UINT64_T( PORE_SBE_SCRATCH2_0x000E000C , ULL(0x000E000C) ); +CONST_UINT64_T( PORE_SBE_IBUF_01_0x000E000D , ULL(0x000E000D) ); +CONST_UINT64_T( PORE_SBE_IBUF_2_0x000E000E , ULL(0x000E000E) ); +CONST_UINT64_T( PORE_SBE_DBG0_0x000E000F , ULL(0x000E000F) ); +CONST_UINT64_T( PORE_SBE_DBG1_0x000E0010 , ULL(0x000E0010) ); +CONST_UINT64_T( PORE_SBE_PC_STACK0_0x000E0011 , ULL(0x000E0011) ); +CONST_UINT64_T( PORE_SBE_PC_STACK1_0x000E0012 , ULL(0x000E0012) ); +CONST_UINT64_T( PORE_SBE_PC_STACK2_0x000E0013 , ULL(0x000E0013) ); +CONST_UINT64_T( PORE_SBE_ID_FLAGS_0x000E0014 , ULL(0x000E0014) ); +CONST_UINT64_T( PORE_SBE_DATA0_0x000E0015 , ULL(0x000E0015) ); +CONST_UINT64_T( PORE_SBE_MEMORY_RELOC_0x000E0016 , ULL(0x000E0016) ); +CONST_UINT64_T( PORE_SBE_I2C_E0_PARAM_0x000E0017 , ULL(0x000E0017) ); +CONST_UINT64_T( PORE_SBE_I2C_E1_PARAM_0x000E0018 , ULL(0x000E0018) ); +CONST_UINT64_T( PORE_SBE_I2C_E2_PARAM_0x000E0019 , ULL(0x000E0019) ); + +//------------------------------------------------------------------------------ +// TP SCOM +// ring 1 = Trace +// ring 2 = OCC +// ring 3 = PIB +// ring 15 = OCCSEC +//------------------------------------------------------------------------------ + + +/******************************************************************************/ +/******************************* NEST CHIPLET *******************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// NEST SCOM +// ring 1 = Trace +// ring 2 = TCBR +// ring 3 = PB +// ring 6 = MCL +// MC0 MCS0 = 0x02011800 +// MC0 MCS1 = 0x02011880 +// MC1 MCS0 = 0x02011900 +// MC1 MCS0 = 0x02011980 +// IOMC0 = 0x02011A00 +// ring 7 = MCR +// MC2 MCS0 = 0x02011C00 +// MC2 MCS1 = 0x02011C80 +// MC3 MCS0 = 0x02011D00 +// MC3 MCS1 = 0x02011D80 +// IOMC1 = 0x02011E00 +// ring 8 = PCIS0 +// ring 9 = PCIS1 +// ring 10 = PCIS2 +// ring 11 = PCIS3 +// ring 12 = NX +// ring 13 = MCD +// ring 15 = TCBRSEC +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// POWERBUS ACCESS BRIDGE (PBA) +//------------------------------------------------------------------------------ +CONST_UINT64_T( PBA_FIR_0x02010840 , ULL(0x02010840) ); +CONST_UINT64_T( PBA_FIR_AND_0x02010841 , ULL(0x02010841) ); +CONST_UINT64_T( PBA_FIR_OR_0x02010842 , ULL(0x02010842) ); +CONST_UINT64_T( PBA_FIR_ACTION0_0x02010843 , ULL(0x02010843) ); +CONST_UINT64_T( PBA_FIR_ACTION1_0x02010844 , ULL(0x02010844) ); +CONST_UINT64_T( PBA_FIR_MASK_0x02010846 , ULL(0x02010846) ); +CONST_UINT64_T( PBA_FIR_MASK_AND_0x02010847 , ULL(0x02010847) ); +CONST_UINT64_T( PBA_FIR_MASK_OR_0x02010848 , ULL(0x02010848) ); +CONST_UINT64_T( PBA_OCC_ACTION_0x0201084A , ULL(0x0201084A) ); +CONST_UINT64_T( PBA_CONFIG_0x0201084B , ULL(0x0201084B) ); +CONST_UINT64_T( PBA_ERR_RPT0_0x0201084C , ULL(0x0201084C) ); +CONST_UINT64_T( PBA_ERR_RPT1_0x0201084D , ULL(0x0201084D) ); +CONST_UINT64_T( PBA_ERR_RPT2_0x0201084E , ULL(0x0201084E) ); +CONST_UINT64_T( PBA_RBUFVAL0_0x02010850 , ULL(0x02010850) ); +CONST_UINT64_T( PBA_RBUFVAL1_0x02010851 , ULL(0x02010851) ); +CONST_UINT64_T( PBA_RBUFVAL2_0x02010852 , ULL(0x02010852) ); +CONST_UINT64_T( PBA_RBUFVAL3_0x02010853 , ULL(0x02010853) ); +CONST_UINT64_T( PBA_RBUFVAL4_0x02010854 , ULL(0x02010854) ); +CONST_UINT64_T( PBA_RBUFVAL5_0x02010855 , ULL(0x02010855) ); +CONST_UINT64_T( PBA_WBUFVAL0_0x02010858 , ULL(0x02010858) ); +CONST_UINT64_T( PBA_WBUFVAL1_0x02010859 , ULL(0x02010859) ); + +CONST_UINT64_T( PBA_MODE_0x00064000 , ULL(0x00064000) ); +CONST_UINT64_T( PBA_SLVRST_0x00064001 , ULL(0x00064001) ); +CONST_UINT64_T( PBA_SLVCTL0_0x00064004 , ULL(0x00064004) ); +CONST_UINT64_T( PBA_SLVCTL1_0x00064005 , ULL(0x00064005) ); +CONST_UINT64_T( PBA_SLVCTL2_0x00064006 , ULL(0x00064006) ); +CONST_UINT64_T( PBA_SLVCTL3_0x00064007 , ULL(0x00064007) ); +CONST_UINT64_T( PBA_BCDE_CTL_0x00064010 , ULL(0x00064010) ); +CONST_UINT64_T( PBA_BCDE_SET_0x00064011 , ULL(0x00064011) ); +CONST_UINT64_T( PBA_BCDE_STAT_0x00064012 , ULL(0x00064012) ); +CONST_UINT64_T( PBA_BCDE_PBADR_0x00064013 , ULL(0x00064013) ); +CONST_UINT64_T( PBA_BCDE_OCIBAR_0x00064014 , ULL(0x00064014) ); +CONST_UINT64_T( PBA_BCUE_CTL_0x00064015 , ULL(0x00064015) ); +CONST_UINT64_T( PBA_BCUE_SET_0x00064016 , ULL(0x00064016) ); +CONST_UINT64_T( PBA_BCUE_STAT_0x00064017 , ULL(0x00064017) ); +CONST_UINT64_T( PBA_BCUE_PBADR_0x00064018 , ULL(0x00064018) ); +CONST_UINT64_T( PBA_BCUE_OCIBAR_0x00064019 , ULL(0x00064019) ); +CONST_UINT64_T( PBA_PBOCR0_0x00064020 , ULL(0x00064020) ); +CONST_UINT64_T( PBA_PBOCR1_0x00064021 , ULL(0x00064021) ); +CONST_UINT64_T( PBA_PBOCR2_0x00064022 , ULL(0x00064022) ); +CONST_UINT64_T( PBA_PBOCR3_0x00064023 , ULL(0x00064023) ); +CONST_UINT64_T( PBA_PBOCR4_0x00064024 , ULL(0x00064024) ); +CONST_UINT64_T( PBA_PBOCR5_0x00064025 , ULL(0x00064025) ); + +CONST_UINT64_T( PBA_BAR0_0x02013F00 , ULL(0x02013F00) ); +CONST_UINT64_T( PBA_BARMSK0_0x02013F04 , ULL(0x02013F04) ); +CONST_UINT64_T( PBA_BAR1_0x02013F01 , ULL(0x02013F01) ); +CONST_UINT64_T( PBA_BARMSK1_0x02013F05 , ULL(0x02013F05) ); +CONST_UINT64_T( PBA_BAR2_0x02013F02 , ULL(0x02013F02) ); +CONST_UINT64_T( PBA_BARMSK2_0x02013F06 , ULL(0x02013F06) ); +CONST_UINT64_T( PBA_BAR3_0x02013F03 , ULL(0x02013F03) ); +CONST_UINT64_T( PBA_BARMSK3_0x02013F07 , ULL(0x02013F07) ); +CONST_UINT64_T( PBA_TRUSTMODE_0x02013F08 , ULL(0x02013F08) ); + +//------------------------------------------------------------------------------ +// NEST PB EH +//------------------------------------------------------------------------------ +// registers with multiple physical/shadow copies (all must be configured consistently) +// west +CONST_UINT64_T( PB_MODE_WEST_0x02010C0A , ULL(0x02010C0A) ); +CONST_UINT64_T( PB_HP_MODE_NEXT_WEST_0x02010C0B , ULL(0x02010C0B) ); +CONST_UINT64_T( PB_HP_MODE_CURR_WEST_0x02010C0C , ULL(0x02010C0C) ); +CONST_UINT64_T( PB_HPX_MODE_NEXT_WEST_0x02010C0D , ULL(0x02010C0D) ); +CONST_UINT64_T( PB_HPX_MODE_CURR_WEST_0x02010C0E , ULL(0x02010C0E) ); +CONST_UINT64_T( PB_FLMCFG0_WEST_0x02010C12 , ULL(0x02010C12) ); +CONST_UINT64_T( PB_FLMCFG1_WEST_0x02010C13 , ULL(0x02010C13) ); +CONST_UINT64_T( PB_FRMCFG0_WEST_0x02010C14 , ULL(0x02010C14) ); +CONST_UINT64_T( PB_FRMCFG1_WEST_0x02010C15 , ULL(0x02010C15) ); +// center +CONST_UINT64_T( PB_MODE_CENT_0x02010C4A , ULL(0x02010C4A) ); +CONST_UINT64_T( PB_HP_MODE_NEXT_CENT_0x02010C4B , ULL(0x02010C4B) ); +CONST_UINT64_T( PB_HP_MODE_CURR_CENT_0x02010C4C , ULL(0x02010C4C) ); +CONST_UINT64_T( PB_HPX_MODE_NEXT_CENT_0x02010C4D , ULL(0x02010C4D) ); +CONST_UINT64_T( PB_HPX_MODE_CURR_CENT_0x02010C4E , ULL(0x02010C4E) ); +CONST_UINT64_T( PB_FLMCFG0_CENT_0x02010C5E , ULL(0x02010C5E) ); +CONST_UINT64_T( PB_FLMCFG1_CENT_0x02010C5F , ULL(0x02010C5F) ); +CONST_UINT64_T( PB_FRMCFG0_CENT_0x02010C60 , ULL(0x02010C60) ); +CONST_UINT64_T( PB_FRMCFG1_CENT_0x02010C61 , ULL(0x02010C61) ); +// east +CONST_UINT64_T( PB_MODE_EAST_0x02010C8A , ULL(0x02010C8A) ); +CONST_UINT64_T( PB_HP_MODE_NEXT_EAST_0x02010C8B , ULL(0x02010C8B) ); +CONST_UINT64_T( PB_HP_MODE_CURR_EAST_0x02010C8C , ULL(0x02010C8C) ); +CONST_UINT64_T( PB_HPX_MODE_NEXT_EAST_0x02010C8D , ULL(0x02010C8D) ); +CONST_UINT64_T( PB_HPX_MODE_CURR_EAST_0x02010C8E , ULL(0x02010C8E) ); +CONST_UINT64_T( PB_FLMCFG0_EAST_0x02010C92 , ULL(0x02010C92) ); +CONST_UINT64_T( PB_FLMCFG1_EAST_0x02010C93 , ULL(0x02010C93) ); +CONST_UINT64_T( PB_FRMCFG0_EAST_0x02010C94 , ULL(0x02010C94) ); +CONST_UINT64_T( PB_FRMCFG1_EAST_0x02010C95 , ULL(0x02010C95) ); + +// registers without shadow copies +// center +CONST_UINT64_T( PB_PMU_0x02010C4F , ULL(0x02010C4F) ); +CONST_UINT64_T( PB_NMPM_COUNT_0x02010C50 , ULL(0x02010C50) ); +CONST_UINT64_T( PB_LMPM_COUNT_0x02010C51 , ULL(0x02010C51) ); +CONST_UINT64_T( PB_RCMD_INTDAT_COUNT_0x02010C52 , ULL(0x02010C52) ); +CONST_UINT64_T( PB_EXTDAT_COUNT_0x02010C53 , ULL(0x02010C53) ); +CONST_UINT64_T( PB_PMU_COUNT0_0x02010C54 , ULL(0x02010C54) ); +CONST_UINT64_T( PB_PMU_COUNT1_0x02010C55 , ULL(0x02010C55) ); +CONST_UINT64_T( PB_PMU_COUNT2_0x02010C56 , ULL(0x02010C56) ); +CONST_UINT64_T( PB_PMU_COUNT3_0x02010C57 , ULL(0x02010C57) ); +CONST_UINT64_T( PB_RGMCFG00_0x02010C58 , ULL(0x02010C58) ); +CONST_UINT64_T( PB_RGMCFG01_0x02010C59 , ULL(0x02010C59) ); +CONST_UINT64_T( PB_RGMCFG10_0x02010C5A , ULL(0x02010C5A) ); +CONST_UINT64_T( PB_RGMCFGM00_0x02010C5B , ULL(0x02010C5B) ); +CONST_UINT64_T( PB_RGMCFGM01_0x02010C5C , ULL(0x02010C5C) ); +CONST_UINT64_T( PB_RGMCFGM10_0x02010C5D , ULL(0x02010C5D) ); +CONST_UINT64_T( PB_GP_CMD_RATE_DP0_0x02010C62 , ULL(0x02010C62) ); +CONST_UINT64_T( PB_GP_CMD_RATE_DP1_0x02010C63 , ULL(0x02010C63) ); +CONST_UINT64_T( PB_RGP_CMD_RATE_DP0_0x02010C64 , ULL(0x02010C64) ); +CONST_UINT64_T( PB_RGP_CMD_RATE_DP1_0x02010C65 , ULL(0x02010C65) ); +CONST_UINT64_T( PB_SP_CMD_RATE_DP0_0x02010C66 , ULL(0x02010C66) ); +CONST_UINT64_T( PB_SP_CMD_RATE_DP1_0x02010C67 , ULL(0x02010C67) ); +CONST_UINT64_T( PB_EVENT_TRACE_0x02010C68 , ULL(0x02010C68) ); +CONST_UINT64_T( PB_EVENT_COMPA_0x02010C69 , ULL(0x02010C69) ); +CONST_UINT64_T( PB_EVENT_COMPB_0x02010C6A , ULL(0x02010C6A) ); +CONST_UINT64_T( PB_CR_ERROR_0x02010C6B , ULL(0x02010C6B) ); + +//------------------------------------------------------------------------------ +// NEST PB EH FIR +//------------------------------------------------------------------------------ +// west FIR +CONST_UINT64_T( PB_FIR_WEST_0x02010C00 , ULL(0x02010C00) ); +CONST_UINT64_T( PB_FIR_AND_WEST_0x02010C01 , ULL(0x02010C01) ); +CONST_UINT64_T( PB_FIR_OR_WEST_0x02010C02 , ULL(0x02010C02) ); +CONST_UINT64_T( PB_FIR_MASK_WEST_0x02010C03 , ULL(0x02010C03) ); +CONST_UINT64_T( PB_FIR_MASK_AND_WEST_0x02010C04 , ULL(0x02010C04) ); +CONST_UINT64_T( PB_FIR_MASK_OR_WEST_0x02010C05 , ULL(0x02010C05) ); +CONST_UINT64_T( PB_FIR_ACTION0_WEST_0x02010C06 , ULL(0x02010C06) ); +CONST_UINT64_T( PB_FIR_ACTION1_WEST_0x02010C07 , ULL(0x02010C07) ); +// center FIR +CONST_UINT64_T( PB_FIR_CENT_0x02010C40 , ULL(0x02010C40) ); +CONST_UINT64_T( PB_FIR_AND_CENT_0x02010C41 , ULL(0x02010C41) ); +CONST_UINT64_T( PB_FIR_OR_CENT_0x02010C42 , ULL(0x02010C42) ); +CONST_UINT64_T( PB_FIR_MASK_CENT_0x02010C43 , ULL(0x02010C43) ); +CONST_UINT64_T( PB_FIR_MASK_AND_CENT_0x02010C44 , ULL(0x02010C44) ); +CONST_UINT64_T( PB_FIR_MASK_OR_CENT_0x02010C45 , ULL(0x02010C45) ); +CONST_UINT64_T( PB_FIR_ACTION0_CENT_0x02010C46 , ULL(0x02010C46) ); +CONST_UINT64_T( PB_FIR_ACTION1_CENT_0x02010C47 , ULL(0x02010C47) ); +// east FIR +CONST_UINT64_T( PB_FIR_EAST_0x02010C80 , ULL(0x02010C80) ); +CONST_UINT64_T( PB_FIR_AND_EAST_0x02010C81 , ULL(0x02010C81) ); +CONST_UINT64_T( PB_FIR_OR_EAST_0x02010C82 , ULL(0x02010C82) ); +CONST_UINT64_T( PB_FIR_MASK_EAST_0x02010C83 , ULL(0x02010C83) ); +CONST_UINT64_T( PB_FIR_MASK_AND_EAST_0x02010C84 , ULL(0x02010C84) ); +CONST_UINT64_T( PB_FIR_MASK_OR_EAST_0x02010C85 , ULL(0x02010C85) ); +CONST_UINT64_T( PB_FIR_ACTION0_EAST_0x02010C86 , ULL(0x02010C86) ); +CONST_UINT64_T( PB_FIR_ACTION1_EAST_0x02010C87 , ULL(0x02010C87) ); +// RAS FIR +CONST_UINT64_T( PB_RAS_FIR_0x02010C6C , ULL(0x02010C6C) ); +CONST_UINT64_T( PB_RAS_FIR_AND_0x02010C6D , ULL(0x02010C6D) ); +CONST_UINT64_T( PB_RAS_FIR_OR_0x02010C6E , ULL(0x02010C6E) ); +CONST_UINT64_T( PB_RAS_FIR_MASK_0x02010C6F , ULL(0x02010C6F) ); +CONST_UINT64_T( PB_RAS_FIR_MASK_AND_0x02010C70 , ULL(0x02010C70) ); +CONST_UINT64_T( PB_RAS_FIR_MASK_OR_0x02010C71 , ULL(0x02010C71) ); +CONST_UINT64_T( PB_RAS_FIR_ACTION0_0x02010C72 , ULL(0x02010C72) ); +CONST_UINT64_T( PB_RAS_FIR_ACTION1_0x02010C73 , ULL(0x02010C73) ); + +//------------------------------------------------------------------------------ +// MCS +//------------------------------------------------------------------------------ +// MCI +CONST_UINT64_T( MCI_FIR_0x02011840 , ULL(0x02011840) ); +CONST_UINT64_T( MCI_CFG_0x0201184A , ULL(0x0201184A) ); +CONST_UINT64_T( MCI_STAT_0x0201184B , ULL(0x0201184B) ); + +//------------------------------------------------------------------------------ +// NEST Alter-Diplay Unit (ADU) +//------------------------------------------------------------------------------ +CONST_UINT64_T( ADU_CONTROL_0x02020000 , ULL(0x02020000) ); +CONST_UINT64_T( ADU_COMMAND_0x02020001 , ULL(0x02020001) ); +CONST_UINT64_T( ADU_STATUS_0x02020002 , ULL(0x02020002) ); +CONST_UINT64_T( ADU_DATA_0x02020003 , ULL(0x02020003) ); +CONST_UINT64_T( ADU_FORCE_ECC_0x02020010 , ULL(0x02020010) ); +CONST_UINT64_T( ADU_PMISC_MODE_0x0202000B , ULL(0x0202000B) ); + + +/******************************************************************************/ +/****************************** X-BUS CHIPLET *******************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// X-BUS GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_GP0_0x04000000 , ULL(0x04000000) ); +CONST_UINT64_T( X_GP1_0x04000001 , ULL(0x04000001) ); +CONST_UINT64_T( X_GP2_0x04000002 , ULL(0x04000002) ); + +//------------------------------------------------------------------------------ +// X-BUS SCOM +// ring 1 = Trace 0 +// ring 2 = Trace 1 +// ring 3 = PBEN +// ring 4 = IOX0 +// ring 5 = IOX1 +// ring 6 = IOX3 +// ring 7 = IOX2 +// ring 9 = IOPSI +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_SCOM_0x04010000 , ULL(0x04010000) ); + +//------------------------------------------------------------------------------ +// X-BUS CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_OPCG_CNTL0_0x04030002 , ULL(0x04030002) ); +CONST_UINT64_T( X_OPCG_CNTL1_0x04030003 , ULL(0x04030003) ); +CONST_UINT64_T( X_OPCG_CNTL2_0x04030004 , ULL(0x04030004) ); +CONST_UINT64_T( X_OPCG_CNTL3_0x04030005 , ULL(0x04030005) ); +CONST_UINT64_T( X_CLK_REGION_0x04030006 , ULL(0x04030006) ); +CONST_UINT64_T( X_CLK_SCANSEL_0x04030007 , ULL(0x04030007) ); +CONST_UINT64_T( X_CLK_STATUS_0x04030008 , ULL(0x04030008) ); + +//------------------------------------------------------------------------------ +// X-BUS FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_XSTOP_0x04040000 , ULL(0x04040000) ); +CONST_UINT64_T( X_RECOV_0x04040001 , ULL(0x04040001) ); +CONST_UINT64_T( X_FIR_MASK_0x04040002 , ULL(0x04040002) ); +CONST_UINT64_T( X_SPATTN_0x04040004 , ULL(0x04040004) ); +CONST_UINT64_T( X_SPATTN_AND_0x04040005 , ULL(0x04040005) ); +CONST_UINT64_T( X_SPATTN_OR_0x04040006 , ULL(0x04040006) ); +CONST_UINT64_T( X_SPATTN_MASK_0x04040007 , ULL(0x04040007) ); +CONST_UINT64_T( X_FIR_MODE_0x04040008 , ULL(0x04040008) ); +CONST_UINT64_T( X_PERV_LFIR_0x0404000A , ULL(0x0404000A) ); +CONST_UINT64_T( X_PERV_LFIR_AND_0x0404000B , ULL(0x0404000B) ); +CONST_UINT64_T( X_PERV_LFIR_OR_0x0404000C , ULL(0x0404000C) ); +CONST_UINT64_T( X_PERV_LFIR_MASK_0x0404000D , ULL(0x0404000D) ); +CONST_UINT64_T( X_PERV_LFIR_MASK_AND_0x0404000E , ULL(0x0404000E) ); +CONST_UINT64_T( X_PERV_LFIR_MASK_OR_0x0404000F , ULL(0x0404000F) ); +CONST_UINT64_T( X_PERV_LFIR_ACT0_0x04040010 , ULL(0x04040010) ); +CONST_UINT64_T( X_PERV_LFIR_ACT1_0x04040011 , ULL(0x04040011) ); + +//------------------------------------------------------------------------------ +// X-BUS THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_THERM_0x04050000 , ULL(0x04050000) ); + +//------------------------------------------------------------------------------ +// X-BUS PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( X_MCGR1_0x040F0001 , ULL(0x040F0001) ); +CONST_UINT64_T( X_MCGR2_0x040F0002 , ULL(0x040F0002) ); +CONST_UINT64_T( X_MCGR3_0x040F0003 , ULL(0x040F0003) ); +CONST_UINT64_T( X_MCGR4_0x040F0004 , ULL(0x040F0004) ); +//GP0 Register +CONST_UINT64_T( X_GP0_AND_0x04000004 , ULL(0x04000004) ); +CONST_UINT64_T( X_GP0_OR_0x04000005 , ULL(0x04000005) ); +//GP3 Register +CONST_UINT64_T( X_GP3_0x040F0012 , ULL(0x040F0012) ); +CONST_UINT64_T( X_GP3_AND_0x040F0013 , ULL(0x040F0013) ); +CONST_UINT64_T( X_GP3_OR_0x040F0014 , ULL(0x040F0014) ); + +//------------------------------------------------------------------------------ +// X-BUS HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_HANG_P0_XBUS_0x040F0020 , ULL(0x040F0020) ); // XBUS : setup hang pulse register0 +CONST_UINT64_T( X_HANG_PRE_XBUS_0x040F0028 , ULL(0x040F0028) ); // XBUS : setup hang precounter (HEX:01) + +//------------------------------------------------------------------------------ +// X-BUS PBEN +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_PB_MODE_0x04010C0A , ULL(0x04010C0A) ); + + +/******************************************************************************/ +/****************************** A-BUS CHIPLET *******************************/ +/******************************************************************************/ +//------------------------------------------------------------------------------ +// A-BUS GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_GP0_0x08000000 , ULL(0x08000000) ); +CONST_UINT64_T( A_GP1_0x08000001 , ULL(0x08000001) ); +CONST_UINT64_T( A_GP2_0x08000002 , ULL(0x08000002) ); + +//------------------------------------------------------------------------------ +// A-BUS SCOM +// ring 1 = trace +// ring 2 = PBES +// ring 3 = IOA +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_SCOM_0x08010000 , ULL(0x08010000) ); + +//------------------------------------------------------------------------------ +// A-BUS CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_OPCG_CNTL0_0x08030002 , ULL(0x08030002) ); +CONST_UINT64_T( A_OPCG_CNTL1_0x08030003 , ULL(0x08030003) ); +CONST_UINT64_T( A_OPCG_CNTL2_0x08030004 , ULL(0x08030004) ); +CONST_UINT64_T( A_OPCG_CNTL3_0x08030005 , ULL(0x08030005) ); +CONST_UINT64_T( A_CLK_REGION_0x08030006 , ULL(0x08030006) ); +CONST_UINT64_T( A_CLK_SCANSEL_0x08030007 , ULL(0x08030007) ); +CONST_UINT64_T( A_CLK_STATUS_0x08030008 , ULL(0x08030008) ); + +//------------------------------------------------------------------------------ +// A-BUS FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_XSTOP_0x08040000 , ULL(0x08040000) ); +CONST_UINT64_T( A_RECOV_0x08040001 , ULL(0x08040001) ); +CONST_UINT64_T( A_FIR_MASK_0x08040002 , ULL(0x08040002) ); +CONST_UINT64_T( A_SPATTN_0x08040004 , ULL(0x08040004) ); +CONST_UINT64_T( A_SPATTN_AND_0x08040005 , ULL(0x08040005) ); +CONST_UINT64_T( A_SPATTN_OR_0x08040006 , ULL(0x08040006) ); +CONST_UINT64_T( A_SPATTN_MASK_0x08040007 , ULL(0x08040007) ); +CONST_UINT64_T( A_FIR_MODE_0x08040008 , ULL(0x08040008) ); +CONST_UINT64_T( A_PERV_LFIR_0x0804000A , ULL(0x0804000A) ); +CONST_UINT64_T( A_PERV_LFIR_AND_0x0804000B , ULL(0x0804000B) ); +CONST_UINT64_T( A_PERV_LFIR_OR_0x0804000C , ULL(0x0804000C) ); +CONST_UINT64_T( A_PERV_LFIR_MASK_0x0804000D , ULL(0x0804000D) ); +CONST_UINT64_T( A_PERV_LFIR_MASK_AND_0x0804000E , ULL(0x0804000E) ); +CONST_UINT64_T( A_PERV_LFIR_MASK_OR_0x0804000F , ULL(0x0804000F) ); +CONST_UINT64_T( A_PERV_LFIR_ACT0_0x08040010 , ULL(0x08040010) ); +CONST_UINT64_T( A_PERV_LFIR_ACT1_0x08040011 , ULL(0x08040011) ); + +//------------------------------------------------------------------------------ +// A-BUS THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_THERM_0x08050000 , ULL(0x08050000) ); + +//------------------------------------------------------------------------------ +// A-BUS PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( A_MCGR1_0x080F0001 , ULL(0x080F0001) ); +CONST_UINT64_T( A_MCGR2_0x080F0002 , ULL(0x080F0002) ); +CONST_UINT64_T( A_MCGR3_0x080F0003 , ULL(0x080F0003) ); +CONST_UINT64_T( A_MCGR4_0x080F0004 , ULL(0x080F0004) ); +//GP0 Register +CONST_UINT64_T( A_GP0_AND_0x08000004 , ULL(0x08000004) ); +CONST_UINT64_T( A_GP0_OR_0x08000005 , ULL(0x08000005) ); +//GP3 Register +CONST_UINT64_T( A_GP3_0x080F0012 , ULL(0x080F0012) ); +CONST_UINT64_T( A_GP3_AND_0x080F0013 , ULL(0x080F0013) ); +CONST_UINT64_T( A_GP3_OR_0x080F0014 , ULL(0x080F0014) ); + +//------------------------------------------------------------------------------ +// A-BUS HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_HANG_P0_0x080F0020 , ULL(0x080F0020) ); // ABUS : setup hang pulse register0 +CONST_UINT64_T( A_HANG_PRE_0x080F0028 , ULL(0x080F0028) ); // ABUS : setup hang precounter (HEX:01) + +//------------------------------------------------------------------------------ +// A-BUS PBES +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_PB_MODE_0x0801080A , ULL(0x0801080A) ); + + +/******************************************************************************/ +/***************************** PCIE-BUS CHIPLET *****************************/ +/******************************************************************************/ +//------------------------------------------------------------------------------ +// PCIE-BUS GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_GP0_0x09000000 , ULL(0x09000000) ); +CONST_UINT64_T( PCIE_GP1_0x09000001 , ULL(0x09000001) ); +CONST_UINT64_T( PCIE_GP2_0x09000002 , ULL(0x09000002) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS SCOM +// ring 1 = trace +// ring 2 = PBF +// ring 5 = IOPCI0 +// ring 6 = IOPCI1 +// ring 7 = IOPCI2 +// ring 8 = PCI0 +// ring 9 = PCI1 +// ring 10 = PCI2 +// ring 11 = PCI3 +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_SCOM_0x09010000 , ULL(0x09010000) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_OPCG_CNTL0_0x09030002 , ULL(0x09030002) ); +CONST_UINT64_T( PCIE_OPCG_CNTL1_0x09030003 , ULL(0x09030003) ); +CONST_UINT64_T( PCIE_OPCG_CNTL2_0x09030004 , ULL(0x09030004) ); +CONST_UINT64_T( PCIE_OPCG_CNTL3_0x09030005 , ULL(0x09030005) ); +CONST_UINT64_T( PCIE_CLK_REGION_0x09030006 , ULL(0x09030006) ); +CONST_UINT64_T( PCIE_CLK_SCANSEL_0x09030007 , ULL(0x09030007) ); +CONST_UINT64_T( PCIE_CLK_STATUS_0x09030008 , ULL(0x09030008) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_XSTOP_0x09040000 , ULL(0x09040000) ); +CONST_UINT64_T( PCIE_RECOV_0x09040001 , ULL(0x09040001) ); +CONST_UINT64_T( PCIE_FIR_MASK_0x09040002 , ULL(0x09040002) ); +CONST_UINT64_T( PCIE_SPATTN_0x09040004 , ULL(0x09040004) ); +CONST_UINT64_T( PCIE_SPATTN_AND_0x09040005 , ULL(0x09040005) ); +CONST_UINT64_T( PCIE_SPATTN_OR_0x09040006 , ULL(0x09040006) ); +CONST_UINT64_T( PCIE_SPATTN_MASK_0x09040007 , ULL(0x09040007) ); +CONST_UINT64_T( PCIE_FIR_MODE_0x09040008 , ULL(0x09040008) ); +CONST_UINT64_T( PCIE_PERV_LFIR_0x0904000A , ULL(0x0904000A) ); +CONST_UINT64_T( PCIE_PERV_LFIR_AND_0x0904000B , ULL(0x0904000B) ); +CONST_UINT64_T( PCIE_PERV_LFIR_OR_0x0904000C , ULL(0x0904000C) ); +CONST_UINT64_T( PCIE_PERV_LFIR_MASK_0x0904000D , ULL(0x0904000D) ); +CONST_UINT64_T( PCIE_PERV_LFIR_MASK_AND_0x0904000E , ULL(0x0904000E) ); +CONST_UINT64_T( PCIE_PERV_LFIR_MASK_OR_0x0904000F , ULL(0x0904000F) ); +CONST_UINT64_T( PCIE_PERV_LFIR_ACT0_0x09040010 , ULL(0x09040010) ); +CONST_UINT64_T( PCIE_PERV_LFIR_ACT1_0x09040011 , ULL(0x09040011) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_THERM_0x09050000 , ULL(0x09050000) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( PCIE_MCGR1_0x090F0001 , ULL(0x090F0001) ); +CONST_UINT64_T( PCIE_MCGR2_0x090F0002 , ULL(0x090F0002) ); +CONST_UINT64_T( PCIE_MCGR3_0x090F0003 , ULL(0x090F0003) ); +CONST_UINT64_T( PCIE_MCGR4_0x090F0004 , ULL(0x090F0004) ); +//GP3 Register +CONST_UINT64_T( PCIE_GP3_0x090F0012 , ULL(0x090F0012) ); +CONST_UINT64_T( PCIE_GP3_AND_0x090F0013 , ULL(0x090F0013) ); +CONST_UINT64_T( PCIE_GP3_OR_0x090F0014 , ULL(0x090F0014) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_HANG_PRE_0x090F0028 , ULL(0x090F0028) ); // PCIE : setup hang precounter (HEX:01) + + +/******************************************************************************/ +/******************************** EX CHIPLET ********************************/ +/******************************************************************************/ +// Note: ECMD will require the use of these addresses, and it will update them +// under the covers to point to the actual EX chiplet in question. +// +// Example: getscom pu.ex 10000001 -c3 ---> scom address 0x13000001 + +//------------------------------------------------------------------------------ +// EX CHIPLET ID +// use for lpcs P0, <chipletID> +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX00_CHIPLET_0x10000000 , ULL(0x10000000) ); +CONST_UINT64_T( EX01_CHIPLET_0x11000000 , ULL(0x11000000) ); +CONST_UINT64_T( EX02_CHIPLET_0x12000000 , ULL(0x12000000) ); +CONST_UINT64_T( EX03_CHIPLET_0x13000000 , ULL(0x13000000) ); +CONST_UINT64_T( EX04_CHIPLET_0x14000000 , ULL(0x14000000) ); +CONST_UINT64_T( EX05_CHIPLET_0x15000000 , ULL(0x15000000) ); +CONST_UINT64_T( EX06_CHIPLET_0x16000000 , ULL(0x16000000) ); +CONST_UINT64_T( EX07_CHIPLET_0x17000000 , ULL(0x17000000) ); +CONST_UINT64_T( EX08_CHIPLET_0x18000000 , ULL(0x18000000) ); +CONST_UINT64_T( EX09_CHIPLET_0x19000000 , ULL(0x19000000) ); +CONST_UINT64_T( EX10_CHIPLET_0x1A000000 , ULL(0x1A000000) ); +CONST_UINT64_T( EX11_CHIPLET_0x1B000000 , ULL(0x1B000000) ); +CONST_UINT64_T( EX12_CHIPLET_0x1C000000 , ULL(0x1C000000) ); +CONST_UINT64_T( EX13_CHIPLET_0x1D000000 , ULL(0x1D000000) ); +CONST_UINT64_T( EX14_CHIPLET_0x1E000000 , ULL(0x1E000000) ); +CONST_UINT64_T( EX15_CHIPLET_0x1F000000 , ULL(0x1F000000) ); + +//------------------------------------------------------------------------------ +// EX GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_GP0_0x10000000 , ULL(0x10000000) ); +CONST_UINT64_T( EX_GP1_0x10000001 , ULL(0x10000001) ); +CONST_UINT64_T( EX_GP2_0x10000002 , ULL(0x10000002) ); + +//------------------------------------------------------------------------------ +// EX SCOM +// ring 1 = ECO trace +// ring 2 = L3 +// ring 3 = NC +// ring 4 = HTM +// ring 8 = L2 trace 0 +// ring 9 = L2 trace 1 +// ring 10 = L2 +// ring 11 = PC trace +// ring 12 = PC +// ring 15 = PC sec +//------------------------------------------------------------------------------ +//ECO Trace +CONST_UINT64_T( EX_ECO_TRACE0_0x10010400 , ULL(0x10010400) ); +CONST_UINT64_T( EX_ECO_TRACE1_0x10010401 , ULL(0x10010401) ); +//L3 +CONST_UINT64_T( EX_L3_MODE_REG1_0x1001080A , ULL(0x1001080A) ); +CONST_UINT64_T( EX_L3_MODE_REG0_0x1001082B , ULL(0x1001082B) ); +//L2 +CONST_UINT64_T( EX_L2_MODE_REG0_0x1001280A , ULL(0x1001280A) ); +CONST_UINT64_T( EX_L2_PURGE_CMD_PRD_0x1001280E , ULL(0x1001280E) ); +CONST_UINT64_T( EX_L2_PURGE_CMD_PHYP_0x1001280F , ULL(0x1001280F) ); + +//------------------------------------------------------------------------------ +// EX/CORE PERVASIVE THREAD CONTROLS +// (chiplet/core set by P0 register) +//------------------------------------------------------------------------------ +// TCTL Direct Controls (for each thread) +CONST_UINT64_T( EX_PERV_TCTL0_DIRECT_0x10013000 , ULL(0x10013000) ); +CONST_UINT64_T( EX_PERV_TCTL1_DIRECT_0x10013010 , ULL(0x10013010) ); +CONST_UINT64_T( EX_PERV_TCTL2_DIRECT_0x10013020 , ULL(0x10013020) ); +CONST_UINT64_T( EX_PERV_TCTL3_DIRECT_0x10013030 , ULL(0x10013030) ); +CONST_UINT64_T( EX_PERV_TCTL4_DIRECT_0x10013040 , ULL(0x10013040) ); +CONST_UINT64_T( EX_PERV_TCTL5_DIRECT_0x10013050 , ULL(0x10013050) ); +CONST_UINT64_T( EX_PERV_TCTL6_DIRECT_0x10013060 , ULL(0x10013060) ); +CONST_UINT64_T( EX_PERV_TCTL7_DIRECT_0x10013070 , ULL(0x10013070) ); + +// TCTL RAS Status (for each thread) +CONST_UINT64_T( EX_PERV_TCTL0_R_STAT_0x10013002 , ULL(0x10013002) ); +CONST_UINT64_T( EX_PERV_TCTL1_R_STAT_0x10013012 , ULL(0x10013012) ); +CONST_UINT64_T( EX_PERV_TCTL2_R_STAT_0x10013022 , ULL(0x10013022) ); +CONST_UINT64_T( EX_PERV_TCTL3_R_STAT_0x10013032 , ULL(0x10013032) ); +CONST_UINT64_T( EX_PERV_TCTL4_R_STAT_0x10013042 , ULL(0x10013042) ); +CONST_UINT64_T( EX_PERV_TCTL5_R_STAT_0x10013052 , ULL(0x10013052) ); +CONST_UINT64_T( EX_PERV_TCTL6_R_STAT_0x10013062 , ULL(0x10013062) ); +CONST_UINT64_T( EX_PERV_TCTL7_R_STAT_0x10013072 , ULL(0x10013072) ); + +//------------------------------------------------------------------------------ +// EX OHA +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_SCOM_0x10020000 , ULL(0x10020000) ); + +//------------------------------------------------------------------------------ +// EX CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_OPCG_CNTL0_0x10030002 , ULL(0x10030002) ); +CONST_UINT64_T( EX_OPCG_CNTL1_0x10030003 , ULL(0x10030003) ); +CONST_UINT64_T( EX_OPCG_CNTL2_0x10030004 , ULL(0x10030004) ); +CONST_UINT64_T( EX_OPCG_CNTL3_0x10030005 , ULL(0x10030005) ); +CONST_UINT64_T( EX_CLK_REGION_0x10030006 , ULL(0x10030006) ); +CONST_UINT64_T( EX_CLK_SCANSEL_0x10030007 , ULL(0x10030007) ); +CONST_UINT64_T( EX_CLK_STATUS_0x10030008 , ULL(0x10030008) ); + +//------------------------------------------------------------------------------ +// EX FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_XSTOP_0x10040000 , ULL(0x10040000) ); +CONST_UINT64_T( EX_RECOV_0x10040001 , ULL(0x10040001) ); +CONST_UINT64_T( EX_FIR_MASK_0x10040002 , ULL(0x10040002) ); +CONST_UINT64_T( EX_SPATTN_0x10040004 , ULL(0x10040004) ); +CONST_UINT64_T( EX_SPATTN_AND_0x10040005 , ULL(0x10040005) ); +CONST_UINT64_T( EX_SPATTN_OR_0x10040006 , ULL(0x10040006) ); +CONST_UINT64_T( EX_SPATTN_MASK_0x10040007 , ULL(0x10040007) ); +CONST_UINT64_T( EX_FIR_MODE_0x10040008 , ULL(0x10040008) ); +CONST_UINT64_T( EX_PERV_LFIR_0x1004000A , ULL(0x1004000A) ); +CONST_UINT64_T( EX_PERV_LFIR_AND_0x1004000B , ULL(0x1004000B) ); +CONST_UINT64_T( EX_PERV_LFIR_OR_0x1004000C , ULL(0x1004000C) ); +CONST_UINT64_T( EX_PERV_LFIR_MASK_0x1004000D , ULL(0x1004000D) ); +CONST_UINT64_T( EX_PERV_LFIR_MASK_AND_0x1004000E , ULL(0x1004000E) ); +CONST_UINT64_T( EX_PERV_LFIR_MASK_OR_0x1004000F , ULL(0x1004000F) ); +CONST_UINT64_T( EX_PERV_LFIR_ACT0_0x10040010 , ULL(0x10040010) ); +CONST_UINT64_T( EX_PERV_LFIR_ACT1_0x10040011 , ULL(0x10040011) ); + +//------------------------------------------------------------------------------ +// EX THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_THERM_0x10050000 , ULL(0x10050000) ); + +//------------------------------------------------------------------------------ +// EX PCB SLAVE +//------------------------------------------------------------------------------ +//Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used +//Multicast Group Registers +CONST_UINT64_T( EX_MCGR1_0x100F0001 , ULL(0x100F0001) ); +CONST_UINT64_T( EX_MCGR2_0x100F0002 , ULL(0x100F0002) ); +CONST_UINT64_T( EX_MCGR3_0x100F0003 , ULL(0x100F0003) ); +CONST_UINT64_T( EX_MCGR4_0x100F0004 , ULL(0x100F0004) ); +//GP3 Register +CONST_UINT64_T( EX_GP3_0x100F0012 , ULL(0x100F0012) ); +CONST_UINT64_T( EX_GP3_AND_0x100F0013 , ULL(0x100F0013) ); +CONST_UINT64_T( EX_GP3_OR_0x100F0014 , ULL(0x100F0014) ); +//PMGP0 Register +CONST_UINT64_T( EX_PMGP0_0x100F0100 , ULL(0x100F0100) ); +CONST_UINT64_T( EX_PMGP0_AND_0x100F0101 , ULL(0x100F0101) ); +CONST_UINT64_T( EX_PMGP0_OR_0x100F0102 , ULL(0x100F0102) ); + +//Chiplet specific names (probably won't ever be used) +CONST_UINT64_T( EX00_GP3_0x100F0012 , ULL(0x100F0012) ); +CONST_UINT64_T( EX00_GP3_AND_0x100F0013 , ULL(0x100F0013) ); +CONST_UINT64_T( EX00_GP3_OR_0x100F0014 , ULL(0x100F0014) ); + +CONST_UINT64_T( EX01_GP3_0x110F0012 , ULL(0x110F0012) ); +CONST_UINT64_T( EX01_GP3_AND_0x110F0013 , ULL(0x110F0013) ); +CONST_UINT64_T( EX01_GP3_OR_0x110F0014 , ULL(0x110F0014) ); + +CONST_UINT64_T( EX02_GP3_0x120F0012 , ULL(0x120F0012) ); +CONST_UINT64_T( EX02_GP3_AND_0x120F0013 , ULL(0x120F0013) ); +CONST_UINT64_T( EX02_GP3_OR_0x120F0014 , ULL(0x120F0014) ); + +CONST_UINT64_T( EX03_GP3_0x130F0012 , ULL(0x130F0012) ); +CONST_UINT64_T( EX03_GP3_AND_0x130F0013 , ULL(0x130F0013) ); +CONST_UINT64_T( EX03_GP3_OR_0x130F0014 , ULL(0x130F0014) ); + +CONST_UINT64_T( EX04_GP3_0x140F0012 , ULL(0x140F0012) ); +CONST_UINT64_T( EX04_GP3_AND_0x140F0013 , ULL(0x140F0013) ); +CONST_UINT64_T( EX04_GP3_OR_0x140F0014 , ULL(0x140F0014) ); + +CONST_UINT64_T( EX05_GP3_0x150F0012 , ULL(0x150F0012) ); +CONST_UINT64_T( EX05_GP3_AND_0x150F0013 , ULL(0x150F0013) ); +CONST_UINT64_T( EX05_GP3_OR_0x150F0014 , ULL(0x150F0014) ); + +CONST_UINT64_T( EX06_GP3_0x160F0012 , ULL(0x160F0012) ); +CONST_UINT64_T( EX06_GP3_AND_0x160F0013 , ULL(0x160F0013) ); +CONST_UINT64_T( EX06_GP3_OR_0x160F0014 , ULL(0x160F0014) ); + +CONST_UINT64_T( EX07_GP3_0x170F0012 , ULL(0x170F0012) ); +CONST_UINT64_T( EX07_GP3_AND_0x170F0013 , ULL(0x170F0013) ); +CONST_UINT64_T( EX07_GP3_OR_0x170F0014 , ULL(0x170F0014) ); + +CONST_UINT64_T( EX08_GP3_0x180F0012 , ULL(0x180F0012) ); +CONST_UINT64_T( EX08_GP3_AND_0x180F0013 , ULL(0x180F0013) ); +CONST_UINT64_T( EX08_GP3_OR_0x180F0014 , ULL(0x180F0014) ); + +CONST_UINT64_T( EX09_GP3_0x190F0012 , ULL(0x190F0012) ); +CONST_UINT64_T( EX09_GP3_AND_0x190F0013 , ULL(0x190F0013) ); +CONST_UINT64_T( EX09_GP3_OR_0x190F0014 , ULL(0x190F0014) ); + +CONST_UINT64_T( EX10_GP3_0x1A0F0012 , ULL(0x1A0F0012) ); +CONST_UINT64_T( EX10_GP3_AND_0x1A0F0013 , ULL(0x1A0F0013) ); +CONST_UINT64_T( EX10_GP3_OR_0x1A0F0014 , ULL(0x1A0F0014) ); + +CONST_UINT64_T( EX11_GP3_0x1B0F0012 , ULL(0x1B0F0012) ); +CONST_UINT64_T( EX11_GP3_AND_0x1B0F0013 , ULL(0x1B0F0013) ); +CONST_UINT64_T( EX11_GP3_OR_0x1B0F0014 , ULL(0x1B0F0014) ); + +CONST_UINT64_T( EX12_GP3_0x1C0F0012 , ULL(0x1C0F0012) ); +CONST_UINT64_T( EX12_GP3_AND_0x1C0F0013 , ULL(0x1C0F0013) ); +CONST_UINT64_T( EX12_GP3_OR_0x1C0F0014 , ULL(0x1C0F0014) ); + +CONST_UINT64_T( EX13_GP3_0x1D0F0012 , ULL(0x1D0F0012) ); +CONST_UINT64_T( EX13_GP3_AND_0x1D0F0013 , ULL(0x1D0F0013) ); +CONST_UINT64_T( EX13_GP3_OR_0x1D0F0014 , ULL(0x1D0F0014) ); + +CONST_UINT64_T( EX14_GP3_0x1E0F0012 , ULL(0x1E0F0012) ); +CONST_UINT64_T( EX14_GP3_AND_0x1E0F0013 , ULL(0x1E0F0013) ); +CONST_UINT64_T( EX14_GP3_OR_0x1E0F0014 , ULL(0x1E0F0014) ); + +CONST_UINT64_T( EX15_GP3_0x1F0F0012 , ULL(0x1F0F0012) ); +CONST_UINT64_T( EX15_GP3_AND_0x1F0F0013 , ULL(0x1F0F0013) ); +CONST_UINT64_T( EX15_GP3_OR_0x1F0F0014 , ULL(0x1F0F0014) ); + +//------------------------------------------------------------------------------ +// EX PCB SLAVE PM +//------------------------------------------------------------------------------ +//Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used + +CONST_UINT64_T( EX_IDLEGOTO_0x100F0114 , ULL(0x100F0114) ); +CONST_UINT64_T( EX_FREQCNTL_0x100F0151 , ULL(0x100F0151) ); + + +//******************************************************************************/ +//********* MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/ +//******************************************************************************/ + +CONST_UINT64_T( READ_ALL_GP0_0x43000000 , ULL(0x43000000) ); // all GP0 but not PRV +CONST_UINT64_T( WRITE_ALL_GP0_0x6B000000 , ULL(0x6B000000) ); // all GP0 but not PRV +CONST_UINT64_T( WRITE_ALL_GP0_AND_0x6B000004 , ULL(0x6B000004) ); // all GP0 AND but not PRV +CONST_UINT64_T( WRITE_ALL_GP0_OR_0x6B000005 , ULL(0x6B000005) ); // all GP0 OR but not PRV + +CONST_UINT64_T( READ_ALL_GP1_AND_0x4B000001 , ULL(0x4B000001) ); // and all GP1 but not PRV + +CONST_UINT64_T( WRITE_ALL_CLK_REGION_0x6B030006 , ULL(0x6B030006) ); // all GP3 but not PRV + +CONST_UINT64_T( READ_ALL_OPCG_CNTL0_0x43030002 , ULL(0x43030002) ); // all EX OPCG0 +CONST_UINT64_T( WRITE_ALL_OPCG_CNTL0_0x6B030002 , ULL(0x6B030002) ); // all EX OPCG0 + +CONST_UINT64_T( READ_ALL_OPCG_CNTL2_0x43030004 , ULL(0x43030004) ); // all OPCG2 but not PRV +CONST_UINT64_T( WRITE_ALL_OPCG_CNTL2_0x6B030004 , ULL(0x6B030004) ); // all OPCG2 but not PRV + +CONST_UINT64_T( READ_ALL_FUNC_GP3_0x430F0012 , ULL(0x430F0012) ); // all GP3 but not PRV +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_0x6B0F0012 , ULL(0x6B0F0012) ); // all GP3 but not PRV +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_AND_0x6B0F0013 , ULL(0x6B0F0013) ); // all GP3 but not PRV +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_OR_0x6B0F0014 , ULL(0x6B0F0014) ); // all GP3 but not PRV + +CONST_UINT64_T( WRITE_ALL_HPRE0_0x690F0020 , ULL(0x690F0020) ); // hang pulse register 0 +CONST_UINT64_T( WRITE_ALL_HPRE1_0x690F0021 , ULL(0x690F0021) ); // hang pulse register 1 +CONST_UINT64_T( WRITE_ALL_HPRE2_0x690F0022 , ULL(0x690F0022) ); // hang pulse register 2 +CONST_UINT64_T( WRITE_ALL_HPCRE_0x690F0028 , ULL(0x690F0028) ); // hang pulse count register + +CONST_UINT64_T( WRITE_EX_PMGP0_AND_0x690F0101 , ULL(0x690F0101) ); // PM GP0 initialization + +CONST_UINT64_T( SLAVE_PCB_ERR_0x6B0F001F , ULL(0x6B0F001F) ); + + +#endif + + +/* +*************** Do not edit this area *************** +This section is automatically updated by CVS when you check in this file. +Be sure to create CVS comments when you commit so that they can be included here. + +$Log: p8_scom_addresses.H,v $ +Revision 1.50 2012/01/06 22:20:53 jmcgill +move shared/common addresses to common_scom_addresses.H, general cleanup + +Revision 1.49 2012/01/05 22:07:47 jeshua +Updated ring numbers for most chiplets + +Revision 1.48 2012/01/05 21:38:17 jmcgill +adjust EX SCOM ring comments, pervasive thread control/status register addresses + +Revision 1.47 2012/01/05 20:18:16 jmcgill +adjust L2 SCOM addresses + +Revision 1.46 2011/12/15 17:49:30 bcbrock +Added the PIBMEM base address to p8_scom_addresses.H + +Revision 1.45 2011/11/07 23:52:21 bcbrock +Added GENERIC_CLK_SCANDATA0_0x00038000 + +Revision 1.44 2011/11/07 05:49:06 jmcgill +update PBA trusted SCOM ring and PB X mode register addresses, add GP0 and/or addresses for A bus chiplet + +Revision 1.43 2011/09/28 12:49:47 stillgs +Added some PCBS-PM addresses for early PM FAPI work + +Revision 1.42 2011/09/16 16:01:34 jeshua +Added MBOX_SBEVITAL + +Revision 1.41 2011/09/16 16:00:26 jeshua +Undo Ralph's X-bus change. The X-bus is now chiplet 4, not chiplet 3. + +Revision 1.40 2011/09/16 10:28:56 rkoester +wrong X-BUS addresses corrected, changed from 0b04 to 0b03 + +Revision 1.39 2011/09/09 21:00:33 jeshua +X_BUS is now chiplet 4 (as of 051 chip) + +Revision 1.37 2011/09/02 18:45:46 dan +Added scan_time_rep + +Revision 1.36 2011/09/01 20:37:17 jmcgill +add PBA config register, shift L2 scom addresses for HW170113, fix L3 Mode Reg0 address + +Revision 1.35 2011/08/30 22:07:37 jeshua +Added NEST_GP0_AND + +Revision 1.34 2011/08/29 21:11:31 jmcgill +add generic PM GP0 OR constant + +Revision 1.33 2011/08/26 15:51:38 jeshua +Added chiplet defines for multicast operations + +Revision 1.32 2011/08/26 12:53:27 gweber +added constant SCAN_ALLSCANEXPRV_IMM + +Revision 1.31 2011/08/11 20:56:24 dan +removed redundant GENERIC_PMGP0_AND_0x000F0101. +added WRITE_ALL_GP0_AND_0x6B000004, WRITE_ALL_GP0_OR_0x6B000005 + +Revision 1.30 2011/07/28 16:36:30 jmcgill +add comment regarding L2 SCOM addresses which need to be adjusted when model fixes arrive (HW170113) + +Revision 1.29 2011/07/27 12:28:55 dan +Added scan0 defines. + +Revision 1.28 2011/07/25 22:31:03 venton +Added back in global addresses still used in SBe procs from version 1.24 + +Revision 1.27 2011/07/25 20:52:58 jmcgill +temporary workaround for L2 Purge Register SCOM access + +Revision 1.26 2011/07/25 17:30:35 dan +Added some generic registers. + +Revision 1.25 2011/07/25 13:05:09 gweber +moved centaur constants to cen_scom_addresses.H + +Revision 1.23 2011/07/20 15:32:10 gweber +added some centaur constants + +Revision 1.22 2011/07/15 20:50:13 jeshua +Added chiplet and some generic addresses + +Revision 1.21 2011/07/15 20:24:14 jeshua +TP_GP3_0x01000003 should be TP_GP4_0x01000003 + +Revision 1.20 2011/07/08 19:49:01 jeshua +Moved some addresses to their appropriate sections +Fixes some addresses that didn't match their name +Added EX08-15 generics +Removed some non-generic EX01 addresses + +Revision 1.19 2011/07/07 21:36:11 rkoester +more addresses added + +Revision 1.18 2011/07/07 16:27:49 karm +added chiplet_core_pervasive registers for start and status, added chiplet id + +Revision 1.17 2011/07/07 12:24:49 rkoester +addresses added + +Revision 1.16 2011/07/06 20:03:46 jmcgill +updates to handle TP design modifications which changed SCOM access method for subset of PBA facilities + +Revision 1.15 2011/07/06 15:01:36 bcbrock +Fix header file name + +Revision 1.14 2011/07/06 04:06:49 bcbrock +Added a common header for FAPI/SBE #defines, fapi_sbe_common.h + +Revision 1.13 2011/07/01 15:13:16 rkoester +addresses added for mailbox register + +Revision 1.12 2011/06/30 09:50:28 rkoester +private version of .H file released back to LIB, MBOX addresses added + +Revision 1.11 2011/06/15 22:46:26 jeshua +Added Mailbox registers + +Revision 1.10 2011/06/14 15:55:46 rkoester +move SCOM addresses from porinit.C to p8_scom_addresses.H + +Revision 1.9 2011/06/14 04:57:04 bcbrock +Latest version of PGAS and PORE inline tools; Added PORE SCOM addresses + +Revision 1.8 2011/06/07 21:26:49 jeshua +Updated OCB names to have the correct addresses + +Revision 1.7 2011/06/02 14:28:26 jmcgill +add PB EH scom addresses, L3 mode register1 address + +Revision 1.6 2011/05/31 22:09:47 jeshua +Updated the ULL macro, because the previous one didn't work with the assembler + +Revision 1.5 2011/05/27 21:49:13 jeshua +Switch to constants instead of #defines +Added in a macro to allow PORE assembler to use this header as well + +Revision 1.4 2011/05/24 19:01:58 jmcgill +add addresses from OCC/OCB/PBA + +Revision 1.3 2011/04/21 19:48:23 jeshua +Added L2 and L3 Mode Reg 0 + +Revision 1.2 2011/04/06 18:27:01 jmcgill +fixup ADU Control Register name, add ADU PMISC Mode Register address + +Revision 1.1 2011/02/23 17:09:44 jeshua +Initial version + + + +*/ diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C new file mode 100644 index 000000000..dd4cd80bf --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C @@ -0,0 +1,1266 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/proc_cen_framelock.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: proc_cen_framelock.C,v 1.2 2012/01/06 23:44:48 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_cen_framelock.H +// *! DESCRIPTION : Run framelock and FRTL (FAPI) +// *! +// *! OWNER NAME : Irving Baysah Email: baysah@us.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "proc_cen_framelock.H" + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: utility subroutine to create proper SCOM address for P8 MCI +// resource given base SCOM address (associated with MCS0) and target +// MCS chiplet offset +// parameters: i_base_addr => base SCOM address (associated with MCS0) for +// desired MCI resource +// i_mcs => MCS target chiplet offset to operate on +// o_xlate_addr => translated SCOM address for desired MCI resource +// returns: FAPI_RC_SUCCESS if address translation was successful, +// else RC_PROC_CEN_FRAMELOCK_INTERNAL_ERR if MCS target chiplet offset +// is out of range or base +// address is unsupported +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_translate_mci_scom_addr( + const uint32_t& i_base_addr, + const uint8_t& i_mcs, + uint32_t& o_xlate_addr) +{ + fapi::ReturnCode rc; + + // validate that MCS offset is in range + if (i_mcs > PROC_CEN_FRAMELOCK_MAX_MCS_OFFSET) + { + FAPI_ERR( + "proc_cen_framelock_translate_mci_scom_addr: Out of range value %d presented for MCS offset argument value!", + i_mcs); + const uint8_t & ERR_DATA = i_mcs; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INTERNAL_ERR); + } + // check that base address matches one of the supported addresses + else if ((i_base_addr != MCI_FIR_0x02011840) && + (i_base_addr != MCI_CFG_0x0201184A) && + (i_base_addr != MCI_STAT_0x0201184B)) + { + FAPI_ERR( + "proc_cen_framelock_translate_mci_scom_addr: Unsupported base SCOM address value 0x%x presented for translation!", + i_base_addr); + const uint32_t & ERR_DATA = i_base_addr; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INTERNAL_ERR); + } + else + { + // perform SCOM address translation + o_xlate_addr = i_base_addr; + + // add base offset for MC + o_xlate_addr += ((i_mcs / 2) * 0x100); + if ((i_mcs / 2) > 1) + { + o_xlate_addr += 0x200; + } + + // add offset for odd MCS numbers + if (i_mcs % 2) + { + o_xlate_addr += 0x80; + } + } + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to clear the Centaur MBI Status Register +// parameters: i_mem_target => Centaur target +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_stat_reg( + const fapi::Target& i_mem_target) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase zero_data(64); + + FAPI_DBG("proc_cen_framelock_clear_cen_mbi_stat_reg: Start"); + + rc = fapiPutScom(i_mem_target, MBI_STAT_0x0201080B, zero_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_cen_mbi_stat_reg: fapiPutScom error"); + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to get the Centaur MBI Status Register +// parameters: i_mem_target => Centaur target +// o_data => Output data +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_get_cen_mbi_stat_reg( + const fapi::Target& i_mem_target, + ecmdDataBufferBase& o_data) +{ + fapi::ReturnCode rc; + + FAPI_DBG("proc_cen_framelock_get_cen_mbi_stat_reg: Start"); + + rc = fapiGetScom(i_mem_target, MBI_STAT_0x0201080B, o_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_get_cen_mbi_stat_reg: fapiGetScom error"); + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to clear the Centaur MBI FIR Register +// parameters: i_mem_target => Centaur target +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_fir_reg( + const fapi::Target& i_mem_target) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase zero_data(64); + + FAPI_DBG("proc_cen_framelock_clear_cen_mbi_fir_reg: Start"); + + rc = fapiPutScom(i_mem_target, MBI_FIR_0x02010800, zero_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_cen_mbi_fir_reg: fapiPutScom error"); + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to get the Centaur MBI FIR Register +// parameters: i_mem_target => Centaur target +// o_data => Output data +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_get_cen_mbi_fir_reg( + const fapi::Target& i_mem_target, + ecmdDataBufferBase& o_data) +{ + fapi::ReturnCode rc; + + FAPI_DBG("proc_cen_framelock_get_cen_mbi_fir_reg: Start"); + + rc = fapiGetScom(i_mem_target, MBI_FIR_0x02010800, o_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_get_cen_mbi_fir_reg: fapiGetScom error"); + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to clear the P8 MCI Status Register +// parameters: i_pu_target => P8 target +// i_args => proc_cen_framelock HWP argumemt structure +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_clear_pu_mci_stat_reg( + const fapi::Target& i_pu_target, + const proc_cen_framelock_args& i_args) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase zero_data(64); + uint32_t mci_xlate_scom_addr = 0; + + FAPI_DBG("proc_cen_framelock_clear_pu_mci_stat_reg: Start"); + rc = proc_cen_framelock_translate_mci_scom_addr(MCI_STAT_0x0201184B, + i_args.mcs_pu, + mci_xlate_scom_addr); + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_pu_mci_stat_reg: xlate error"); + } + else + { + rc = fapiPutScom(i_pu_target, mci_xlate_scom_addr, zero_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_pu_mci_stat_reg: fapiPutScom error"); + } + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to get the P8 MCI Status Register +// parameters: i_pu_target => P8 target +// i_args => proc_cen_framelock HWP argumemt structure +// o_data => Output data +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_get_pu_mci_stat_reg( + const fapi::Target& i_pu_target, + const proc_cen_framelock_args& i_args, + ecmdDataBufferBase& o_data) +{ + fapi::ReturnCode rc; + uint32_t mci_xlate_scom_addr = 0; + + FAPI_DBG("proc_cen_framelock_get_pu_mci_stat_reg: Start"); + rc = proc_cen_framelock_translate_mci_scom_addr(MCI_STAT_0x0201184B, + i_args.mcs_pu, + mci_xlate_scom_addr); + if (rc) + { + FAPI_ERR("proc_cen_framelock_get_pu_mci_stat_reg: xlate error"); + } + else + { + rc = fapiGetScom(i_pu_target, mci_xlate_scom_addr, o_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_get_pu_mci_stat_reg: fapiGetScom error"); + } + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to clear the P8 MCI FIR Register +// parameters: i_pu_target => P8 target +// i_args => proc_cen_framelock HWP argumemt structure +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_clear_pu_mci_fir_reg( + const fapi::Target& i_pu_target, + const proc_cen_framelock_args& i_args) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase zero_data(64); + uint32_t mci_xlate_scom_addr = 0; + + FAPI_DBG("proc_cen_framelock_clear_pu_mci_fir_reg: Start"); + rc = proc_cen_framelock_translate_mci_scom_addr(MCI_FIR_0x02011840, + i_args.mcs_pu, + mci_xlate_scom_addr); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_pu_mci_fir_reg: xlate error"); + } + else + { + rc = fapiPutScom(i_pu_target, mci_xlate_scom_addr, zero_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_pu_mci_fir_reg: fapiPutScom error"); + } + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to get the P8 MCI FIR Register +// parameters: i_pu_target => P8 target +// i_args => proc_cen_framelock HWP argumemt structure +// o_data => output data +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_get_pu_mci_fir_reg( + const fapi::Target& i_pu_target, + const proc_cen_framelock_args& i_args, + ecmdDataBufferBase& o_data) +{ + fapi::ReturnCode rc; + uint32_t mci_xlate_scom_addr = 0; + + FAPI_DBG("proc_cen_framelock_get_pu_mci_fir_reg: Start"); + rc = proc_cen_framelock_translate_mci_scom_addr(MCI_FIR_0x02011840, + i_args.mcs_pu, + mci_xlate_scom_addr); + if (rc) + { + FAPI_ERR("proc_cen_framelock_get_pu_mci_fir_reg: xlate error"); + } + else + { + rc = fapiGetScom(i_pu_target, mci_xlate_scom_addr, o_data); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_get_pu_mci_fir_reg: fapiGetScom error"); + } + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to set the Centaur MBI Config Register +// parameters: i_mem_target => Centaur target +// i_data => Input data +// i_mask => Input mask +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_set_cen_mbi_cfg_reg( + const fapi::Target& i_mem_target, + ecmdDataBufferBase& i_data, + ecmdDataBufferBase& i_mask) +{ + fapi::ReturnCode rc; + + FAPI_DBG("proc_cen_framelock_set_cen_mbi_cfg_reg: Start"); + rc = fapiPutScomUnderMask(i_mem_target, MBI_CFG_0x0201080A, i_data, i_mask); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_set_cen_mbi_cfg_reg: fapiPutScomUnderMask error"); + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to set the P8 MCI Config Register +// parameters: i_pu_target => P8 target +// i_data => Input data +// i_mask => Input mask +// i_args => proc_cen_framelock HWP argumemt structure +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_set_pu_mci_cfg_reg( + const fapi::Target& i_pu_target, + ecmdDataBufferBase& i_data, + ecmdDataBufferBase& i_mask, + const proc_cen_framelock_args& i_args) +{ + fapi::ReturnCode rc; + uint32_t mci_xlate_scom_addr = 0; + + FAPI_DBG("proc_cen_framelock_set_pu_mci_cfg_reg: Start"); + rc = proc_cen_framelock_translate_mci_scom_addr(MCI_CFG_0x0201184A, + i_args.mcs_pu, + mci_xlate_scom_addr); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_set_pu_mci_cfg_reg: xlate error"); + } + else + { + rc = fapiPutScomUnderMask(i_pu_target, mci_xlate_scom_addr, i_data, + i_mask); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_set_pu_mci_cfg_reg: fapiPutScomUnderMask error"); + } + } + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to claer the P8 and Centaur Status/FIR Registers +// parameters: i_pu_target => P8 target +// i_mem_target => Centaur target +// i_args => proc_cen_framelock HWP argumemt structure +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_clear_stat_fir_regs( + const fapi::Target& i_pu_target, + const fapi::Target& i_mem_target, + const proc_cen_framelock_args& i_args) +{ + fapi::ReturnCode rc; + + FAPI_DBG("proc_cen_framelock_clear_stat_fir_regs: Start"); + + do + { + // Clear Centaur MBI Status Register + rc = proc_cen_framelock_clear_cen_mbi_stat_reg(i_mem_target); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_cen_mbi_stat_reg"); + break; + } + + // Clear Centaur MBI FIR Register + rc = proc_cen_framelock_clear_cen_mbi_fir_reg(i_mem_target); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_cen_mbi_fir_reg"); + break; + } + + // Clear P8 MCI Status Register + rc = proc_cen_framelock_clear_pu_mci_stat_reg(i_pu_target, i_args); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_pu_mci_stat_reg"); + break; + } + + // Clear P8 MCI FIR Register + rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target, i_args); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_pu_mci_fir_reg"); + break; + } + + } while(0); + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to initiate P8/Centaur framelock operation and +// poll for completion +// parameters: i_pu_target => P8 chip target +// i_mem_target => Centaur chip target +// i_args => proc_cen_framelock HWP argumemt structure +// returns: FAPI_RC_SUCCESS if framelock sequence completes successfully, +// RC_PROC_CEN_FRAMELOCK_INTERNAL_ERR +// if internal program logic error is encountered, +// RC_PROC_CEN_FRAMELOCK_FL_CEN_FIR_ERR +// RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR +// if MCI/MBI FIR is set during framelock operation, +// RC_PROC_CEN_FRAMELOCK_FL_CEN_FAIL_ERR +// RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR +// if MCI/MBI indicates framelock operation failure +// RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR +// if MCI/MBI does not post pass/fail indication after framelock +// operation is started, +// else FAPI getscom/putscom return code for failing SCOM operation +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_run_framelock( + const fapi::Target& i_pu_target, + const fapi::Target& i_mem_target, + const proc_cen_framelock_args& i_args) +{ + // data buffers + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + ecmdDataBufferBase mbi_stat(64); + ecmdDataBufferBase mbi_fir(64); + ecmdDataBufferBase mci_stat(64); + ecmdDataBufferBase mci_fir(64); + + // return codes + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + + FAPI_DBG("proc_cen_framelock_run_framelock: Starting framelock sequence ..."); + + do + { + // Clear Centaur/P8 Status/FIR registers + rc = proc_cen_framelock_clear_stat_fir_regs(i_pu_target, i_mem_target, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing Centaur/P8 Status/FIR regs"); + break; + } + + // If error state is set, force framelock bit in Centaur MBI + // Configuration Register + if (i_args.in_error_state) + { + FAPI_DBG("proc_cen_framelock_run_framelock: Writing Centaur MBI Configuration Register to force framelock ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRAMELOCK_BIT); + rc_ecmd |= data.copy(mask); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to force framelock", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, + mask); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error writing Centaur MBI Configuration Register to force framelock"); + break; + } + } + + // set channel init timeout value in P8 MCI Configuration Register + FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to set channel init timeout value ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= mask.flushTo0(); + rc_ecmd |= data.insertFromRight( + (uint32_t) (i_args.channel_init_timeout & + MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK), + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + rc_ecmd |= mask.setBit( + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to set init timeout", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to set init timeout"); + break; + } + + // start framelock + FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to initiate framelock ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MCI_CFG_START_FRAMELOCK_BIT); + rc_ecmd |= data.copy(mask); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to initiate framelock", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to initiate framelock"); + break; + } + + // poll until framelock operation is finished, a timeout is deemed to + // have occurred, or an error is detected + uint8_t polls = 0; + + while (1) + { + // Read Centaur MBI Status Register + rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, + mbi_stat); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error reading Centaur MBI Status Register"); + break; + } + + // Read Centaur MBI FIR Register + rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error reading Centaur MBI FIR Register"); + break; + } + + // Read P8 MCI Status Register + rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, i_args, + mci_stat); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI Status Register"); + break; + } + + // Read P8 MCI FIR Register + rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, i_args, + mci_fir); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI FIR Register"); + break; + } + + // Fail if any Centaur FIR bits are set + if (mbi_fir.getDoubleWord(0)) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. Centaur MBI FIR bit on (0x%llx)", + mbi_fir.getDoubleWord(0)); + ecmdDataBufferBase & FIR_REG = mbi_fir; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FIR_ERR); + break; + } + + // Fail if any P8 FIR bits are set + if (mci_fir.getDoubleWord(0)) + { + // TODO: seeing FIR[25] set on e8052+cen050 model due to flush + // state parity error fixed in future P8 models, skip check for + // now + FAPI_ERR("TODO. IGNORING. proc_cen_framelock_run_framelock: Framelock fail. P8 MCI FIR bit on (0x%llx)", + mci_fir.getDoubleWord(0)); + //ecmdDataBufferBase & FIR_REG = mci_fir; + //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR); + //break; + } + + // Fail if Centaur FAIL bit set + if (mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_FAIL_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. Centaur MBI_STAT_FRAMELOCK_FAIL_BIT set"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FAIL_ERR); + break; + } + + // Fail if P8 FAIL bit set + if (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_FAIL_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI_STAT_FRAMELOCK_FAIL_BIT set"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR); + break; + } + + // Success if Centaur and P8 PASS bits set + if ((mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_PASS_BIT)) && + (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_PASS_BIT))) + { + FAPI_DBG("proc_cen_framelock_run_framelock: Framelock completed successfully!"); + break; + } + + if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS) + { + // Loop count has expired, timeout + if (mbi_stat.isBitClear(MBI_STAT_FRAMELOCK_PASS_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Framelock timeout waiting on pass/fail indication in Centaur MBI Status Register!"); + } + if (mci_stat.isBitClear(MCI_STAT_FRAMELOCK_PASS_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_framelock: Framelock timeout waiting on pass/fail indication in P8 MCI Status Register!"); + } + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR); + break; + } + else + { + // polls left, keep waiting for pass/fail bits to come on + polls++; + FAPI_DBG("proc_cen_framelock_run_framelock: Loop %d of %d ...\n", + polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS); + } + } + } while (0); + + return rc; +} + +//------------------------------------------------------------------------------ +// function: utility subroutine to initiate P8/Centaur FRTL (frame round trip +// latency) determination and check for completion +// parameters: i_pu_target => P8 chip target +// i_mem_target => Centaur chip target +// i_args => proc_cen_framelock HWP argumemt structure +// returns: FAPI_RC_SUCCESS if FRTL sequence completes successfully, +// RC_PROC_CEN_FRAMELOCK_INTERNAL_ERR +// if internal program logic error is encountered, +// RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FIR_ERR +// RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR +// if MCI/MBI FIR is set during FRTL operation, +// RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR +// RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR +// if MCI/MBI indicates FRTL operation failure, +// RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR +// if MCI/MBI does not post pass/fail indication after FRTL +// operation is started, +// else FAPI getscom/putscom return code for failing SCOM operation +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock_run_frtl( + const fapi::Target& i_pu_target, + const fapi::Target& i_mem_target, + const proc_cen_framelock_args& i_args) +{ + // data buffers for putscom/getscom calls + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + ecmdDataBufferBase mbi_stat(64); + ecmdDataBufferBase mbi_fir(64); + ecmdDataBufferBase mci_stat(64); + ecmdDataBufferBase mci_fir(64); + + // return codes + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + + // mark function entry + FAPI_DBG("proc_cen_framelock_run_frtl: Starting FRTL sequence ..."); + + do + { + // Clear Centaur/P8 Status/FIR registers + rc = proc_cen_framelock_clear_stat_fir_regs(i_pu_target, i_mem_target, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error clearing Centaur/P8 Status/FIR regs"); + break; + } + + if (i_args.frtl_auto_not_manual) + { + // Auto mode + + // if error state is set, force FRTL bit in Centaur MBI + // Configuration Register + if (i_args.in_error_state) + { + FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to force FRTL ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRTL_BIT); + rc_ecmd |= data.copy(mask); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to force FRTL", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, + mask); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration Register to force FRTL"); + break; + } + } + + // set channel init timeout value in P8 MCI Configuration Register + FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration Register to set channel init timeout value ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= mask.flushTo0(); + rc_ecmd |= data.insertFromRight( + (uint32_t) (i_args.channel_init_timeout & + MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK), + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + rc_ecmd |= mask.setBit( + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set init timeout", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to set init timeout"); + break; + } + + // start FRTL + FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration Register to initiate FRTL ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MCI_CFG_START_FRTL_BIT); + rc_ecmd |= data.copy(mask); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to initiate FRTL", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to initiate FRTL"); + break; + } + + // Poll until FRTL operation is finished, a timeout is deemed to + // have occurred, or an error is detected + uint8_t polls = 0; + + while (1) + { + // Read Centaur MBI Status Register + rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, + mbi_stat); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error reading Centaur MBI Status Register"); + break; + } + + // Read Centaur MBI FIR Register + rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, + mbi_fir); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error reading Centaur MBI FIR Register"); + break; + } + + // Read P8 MCI Status Register + rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, i_args, + mci_stat); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI Status Register"); + break; + } + + // Read P8 MCI FIR Register + rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, i_args, + mci_fir); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI FIR Register"); + break; + } + + // Fail if any Centaur FIR bits are set + if (mbi_fir.getDoubleWord(0)) + { + FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (auto). Centaur MBI FIR bit on (0x%llx)", + mbi_fir.getDoubleWord(0)); + ecmdDataBufferBase & FIR_REG = mbi_fir; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FIR_ERR); + break; + } + + // Fail if any P8 FIR bits are set + if (mci_fir.getDoubleWord(0)) + { + // TODO: seeing FIR[25] set on e8052+cen050 model due to + // flush state parity error fixed in future P8 models, skip + // check for now + FAPI_ERR("TODO. IGNORING. proc_cen_framelock_run_frtl: FRTL fail (auto). P8 MCI FIR bit on (0x%llx)", + mci_fir.getDoubleWord(0)); + //ecmdDataBufferBase & FIR_REG = mci_fir; + //FAPI_SET_HWP_ERROR(rc, + // RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR); + //break; + } + + // Fail if Centaur FAIL bit set + if (mbi_stat.isBitSet(MBI_STAT_FRTL_FAIL_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (auto). Centaur MBI_STAT_FRTL_FAIL_BIT set"); + FAPI_SET_HWP_ERROR(rc, + RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR); + break; + } + + // Fail if P8 FAIL bit set + if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (auto). P8 MCI_STAT_FRTL_FAIL_BIT set"); + FAPI_SET_HWP_ERROR(rc, + RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR); + break; + } + + // Success if Centaur and P8 PASS bits set + if ((mbi_stat.isBitSet(MBI_STAT_FRTL_PASS_BIT)) && + (mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT))) + { + FAPI_DBG("proc_cen_framelock_run_frtl: FRTL (auto) completed successfully!"); + break; + } + + if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS) + { + // Loop count has expired, timeout + if (mbi_stat.isBitClear(MBI_STAT_FRTL_PASS_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_frtl: FRTL timeout (auto) waiting on pass/fail indication in Centaur MBI Status Register!"); + } + if (mci_stat.isBitClear(MCI_STAT_FRTL_PASS_BIT)) + { + FAPI_ERR("proc_cen_framelock_run_frtl: FRTL timeout (auto) waiting on pass/fail indication in P8 MCI Status Register!"); + } + FAPI_SET_HWP_ERROR(rc, + RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR); + break; + } + else + { + // polls left, keep waiting for pass/fail bits to come on + polls++; + FAPI_DBG("proc_cen_framelock_run_frtl: Loop %d of %d ...\n", + polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS); + } + } + } + else + { + // Manual mode + + // Disable auto FRTL mode & channel init timeout in Centaur MBI + // Configuration Register + FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to disable auto FRTL mode & channel init timeout ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MBI_CFG_AUTO_FRTL_DISABLE_BIT); + rc_ecmd |= data.copy(mask); + rc_ecmd |= data.insertFromRight( + (uint32_t) (CHANNEL_INIT_TIMEOUT_NO_TIMEOUT & + MBI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK), + MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + rc_ecmd |= mask.setBit( + MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to disable Centaur auto FRTL mode", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, + mask); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration register to disable auto FRTL mode"); + break; + } + + // write specified FRTL value into Centaur MBI Configuration + // Register + FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to set manual FRTL value ..."); + if (i_args.frtl_manual_mem > MBI_CFG_MANUAL_FRTL_FIELD_MASK) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Out of range value %d presented for Centaur manual FRTL argument value!", + i_args.frtl_manual_mem); + const proc_cen_framelock_args & ARGS = i_args; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS); + break; + } + + rc_ecmd |= data.flushTo0(); + rc_ecmd |= mask.flushTo0(); + rc_ecmd |= data.insertFromRight( + (uint32_t) (i_args.frtl_manual_mem & + MBI_CFG_MANUAL_FRTL_FIELD_MASK), + MBI_CFG_MANUAL_FRTL_START_BIT, + (MBI_CFG_MANUAL_FRTL_END_BIT - + MBI_CFG_MANUAL_FRTL_START_BIT + 1)); + rc_ecmd |= mask.setBit( + MBI_CFG_MANUAL_FRTL_START_BIT, + (MBI_CFG_MANUAL_FRTL_END_BIT - + MBI_CFG_MANUAL_FRTL_START_BIT + 1)); + + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL value", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, + mask); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration register to set manual FRTL value"); + break; + } + + // write FRTL manual done bit into Centaur MBI Configuration + // Register + FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to set manual FRTL done bit ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MBI_CFG_MANUAL_FRTL_DONE_BIT); + rc_ecmd |= data.copy(mask); + if (rc_ecmd) + { + FAPI_ERR( "proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL done", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, + mask); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration register to set manual FRTL done"); + break; + } + + // disable auto FRTL mode & channel init timeout in P8 MCI + // Configuration Register + FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration register to disable auto FRTL mode & channel init timeout ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MCI_CFG_AUTO_FRTL_DISABLE_BIT); + rc_ecmd |= data.copy(mask); + rc_ecmd |= data.insertFromRight( + (uint32_t)(CHANNEL_INIT_TIMEOUT_NO_TIMEOUT & + MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK), + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + rc_ecmd |= mask.setBit( + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT, + (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT - + MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1)); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to disable P8 auto FRTL mode", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to disable auto FRTL mode"); + break; + } + + // write specified FRTL value into P8 MCI Configuration Register + FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration register to set manual FRTL value ..."); + if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Out of range value 0x%x presented for P8 manual FRTL argument value!", + i_args.frtl_manual_pu); + const proc_cen_framelock_args & ARGS = i_args; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS); + break; + } + rc_ecmd |= data.flushTo0(); + rc_ecmd |= mask.flushTo0(); + rc_ecmd |= data.insertFromRight( + (uint32_t)(i_args.frtl_manual_pu & + MCI_CFG_MANUAL_FRTL_FIELD_MASK), + MCI_CFG_MANUAL_FRTL_START_BIT, + (MCI_CFG_MANUAL_FRTL_END_BIT - + MCI_CFG_MANUAL_FRTL_START_BIT + 1)); + rc_ecmd |= mask.setBit( + MCI_CFG_MANUAL_FRTL_START_BIT, + (MCI_CFG_MANUAL_FRTL_END_BIT - + MCI_CFG_MANUAL_FRTL_START_BIT + 1)); + + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set P8 manual FRTL value", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to set manual FRTL value"); + break; + } + + // write FRTL manual done bit into P8 MCI Configuration Register + FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration register to set manual FRTL done bit ..."); + rc_ecmd |= data.flushTo0(); + rc_ecmd |= data.setBit(MCI_CFG_MANUAL_FRTL_DONE_BIT); + rc_ecmd |= data.copy(mask); + if (rc_ecmd) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to write P8 manual FRTL done", + rc_ecmd); + rc = rc_ecmd; + break; + } + + rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask, + i_args); + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to set manual FRTL done"); + break; + } + + // Read Centaur MBI FIR Register + rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error reading Centaur MBI FIR Register"); + break; + } + + // Read P8 MCI FIR Register + rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, i_args, + mci_fir); + + if (rc) + { + FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI FIR Register"); + break; + } + + // Fail if any Centaur FIR bits are set + if (mbi_fir.getDoubleWord(0)) + { + FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (manual). Centaur MBI FIR bit on (0x%llx)", + mbi_fir.getDoubleWord(0)); + ecmdDataBufferBase & FIR_REG = mbi_fir; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FIR_ERR); + break; + } + + // Fail if any P8 FIR bits are set + if (mci_fir.getDoubleWord(0)) + { + // TODO: seeing FIR[25] set on e8052+cen050 model due to flush + // state parity error fixed in future P8 models, skip check for + // now + FAPI_ERR("TODO. IGNORING. proc_cen_framelock_run_frtl: FRTL fail (manual). P8 MCI FIR bit on (0x%llx)", + mci_fir.getDoubleWord(0)); + //ecmdDataBufferBase & FIR_REG = mci_fir; + //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR); + //break; + } + } + + } while (0); + + return rc; +} + +//------------------------------------------------------------------------------ +// Hardware Procedure +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target, + const fapi::Target& i_mem_target, + const proc_cen_framelock_args& i_args) +{ + fapi::ReturnCode rc; + + // mark HWP entry + FAPI_IMP("proc_cen_framelock: Entering ..."); + + do + { + // validate arguments + if (i_args.mcs_pu > PROC_CEN_FRAMELOCK_MAX_MCS_OFFSET) + { + FAPI_ERR("proc_cen_framelock: Out of range value %d presented for P8 MCS offset argument value!", + i_args.mcs_pu); + const proc_cen_framelock_args & ARGS = i_args; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS); + break; + } + + if (i_args.frtl_manual_mem > MBI_CFG_MANUAL_FRTL_FIELD_MASK) + { + FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL mem argument value!", + i_args.frtl_manual_mem); + const proc_cen_framelock_args & ARGS = i_args; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS); + break; + } + + if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK) + { + FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL pu argument value!", + i_args.frtl_manual_pu); + const proc_cen_framelock_args & ARGS = i_args; + FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS); + break; + } + + // execute framelock + rc = proc_cen_framelock_run_framelock(i_pu_target, i_mem_target, + i_args); + if (rc) + { + break; + } + + // execute FRTL + rc = proc_cen_framelock_run_frtl(i_pu_target, i_mem_target, i_args); + if (rc) + { + break; + } + + } while (0); + + // mark HWP exit + FAPI_IMP("proc_cen_framelock: Exiting ..."); + return rc; +} + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H new file mode 100644 index 000000000..47b176c7f --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H @@ -0,0 +1,182 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/dmi_training/proc_cen_framelock.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: proc_cen_framelock.H,v 1.3 2012/01/06 23:44:51 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_cen_framelock.H +// *! DESCRIPTION : Run framelock and FRTL (FAPI) +// *! +// *! OWNER NAME : Irving Baysah Email: baysah@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS : +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_CEN_FRAMELOCK_H_ +#define _PROC_CEN_FRAMELOCK_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "cen_scom_addresses.H" + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// enum to represent supported channel init timeout values +enum proc_cen_framelock_channel_init_timeout +{ + CHANNEL_INIT_TIMEOUT_NO_TIMEOUT = 0, + CHANNEL_INIT_TIMEOUT_3US = 1, + CHANNEL_INIT_TIMEOUT_7US = 2, + CHANNEL_INIT_TIMEOUT_14US = 3 +}; + +// structure to represent HWP arguments +struct proc_cen_framelock_args +{ + uint8_t mcs_pu; // MCS offset on P8 chip target to operate on + bool in_error_state; // apply error state overrides to framelock/auto FRTL? + proc_cen_framelock_channel_init_timeout channel_init_timeout; + // channel init timeout value to program for framelock/ + // auto/FRTL + bool frtl_auto_not_manual; // set FRTL mode (true = auto-calculation via HW, + // false = manually-programmed via SW) + uint8_t frtl_manual_pu; // in manual FRTL mode, P8 MCI FRTL value to be + // programmed + uint8_t frtl_manual_mem; // in manual FRTL mode, Centaur MBI FRTL value to + // be programmed +}; + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode +(*proc_cen_framelock_FP_t)(const fapi::Target&, + const fapi::Target&, + const proc_cen_framelock_args&); + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// maximum MCS offset supported by P8 chip design +const uint8_t PROC_CEN_FRAMELOCK_MAX_MCS_OFFSET = 7; + +// framelock/FRTL polling constants +const uint8_t PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS = 5; +const uint8_t PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS = 5; + +// P8 MCI Configuration Register field/bit definitions +const uint32_t MCI_CFG_START_FRAMELOCK_BIT = 7; +const uint32_t MCI_CFG_START_FRTL_BIT = 8; +const uint32_t MCI_CFG_AUTO_FRTL_DISABLE_BIT = 9; +const uint32_t MCI_CFG_MANUAL_FRTL_START_BIT = 10; +const uint32_t MCI_CFG_MANUAL_FRTL_END_BIT = 16; +const uint32_t MCI_CFG_MANUAL_FRTL_DONE_BIT = 17; +const uint32_t MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT = 35; +const uint32_t MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT = 36; + +const uint8_t MCI_CFG_MANUAL_FRTL_FIELD_MASK = 0x7F; +const uint32_t MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK = 0x3; + +// P8 MCI Status Register field/bit definitions +const uint32_t MCI_STAT_FRAMELOCK_PASS_BIT = 0; +const uint32_t MCI_STAT_FRAMELOCK_FAIL_BIT = 1; +const uint32_t MCI_STAT_FRTL_PASS_BIT = 2; +const uint32_t MCI_STAT_FRTL_FAIL_BIT = 3; + +// Centaur MBI Configuration Register field/bit defintions +const uint32_t MBI_CFG_FORCE_FRAMELOCK_BIT = 7; +const uint32_t MBI_CFG_FORCE_FRTL_BIT = 8; +const uint32_t MBI_CFG_AUTO_FRTL_DISABLE_BIT = 9; +const uint32_t MBI_CFG_MANUAL_FRTL_START_BIT = 10; +const uint32_t MBI_CFG_MANUAL_FRTL_END_BIT = 16; +const uint32_t MBI_CFG_MANUAL_FRTL_DONE_BIT = 17; +const uint32_t MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT = 35; +const uint32_t MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT = 36; + +const uint8_t MBI_CFG_MANUAL_FRTL_FIELD_MASK = 0x7F; +const uint32_t MBI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK = 0x3; + +// Centaur MBI Status Register field/bit definitions +const uint32_t MBI_STAT_FRAMELOCK_PASS_BIT = 0; +const uint32_t MBI_STAT_FRAMELOCK_FAIL_BIT = 1; +const uint32_t MBI_STAT_FRTL_PASS_BIT = 2; +const uint32_t MBI_STAT_FRTL_FAIL_BIT = 3; + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +// function: FAPI proc_cen_framelock HWP entry point, execute P8/Centaur +// framelock and FRTL operations +// parameters: i_pu_target => P8 chip target +// i_mem_target => Centaur chip target +// i_args => proc_cen_framelock HWP argumemt structure +// returns: FAPI_RC_SUCCESS if framelock/FRTL sequence completes successfully, +// RC_PROC_CEN_FRAMELOCK_INVALID_ARGS +// if invalid/out of range arguments are presented in i_args, +// RC_PROC_CEN_FRAMELOCK_INTERNAL_ERR +// if internal program logic error is encountered, +// RC_PROC_CEN_FRAMELOCK_FL_CEN_FIR_ERR +// if Centaur MBI FIR is set during framelock operation, +// RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR +// if P8 MCI FIR is set during framelock operation, +// RC_PROC_CEN_FRAMELOCK_FL_CEN_FAIL_ERR +// if Centaur MBI indicates framelock operation failure, +// RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR +// if P8 MCI indicates framelock operation failure, +// RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR +// if MCI/MBI does not post pass/fail indication after framelock +// operation is started, +// RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FIR_ERR +// if Centaur MBI FIR is set during FRTL operation, +// RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR +// if P8 MCI FIR is set during FRTL operation, +// RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR +// if Centaur MBI indicates FRTL operation failure, +// RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR +// if P8 MCI indicates FRTL operation failure, +// RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR +// if MCI/MBI does not post pass/fail indication after FRTL +// operation is started, +// +// else FAPI getscom/putscom return code for failing operation +fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target, + const fapi::Target& i_mem_target, + const proc_cen_framelock_args& i_args); + +} // extern "C" + +#endif // _PROC_CEN_FRAMELOCK_H_ diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml new file mode 100644 index 000000000..bfa5fa5c7 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml @@ -0,0 +1,91 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/HWPs/dmi_training/proc_cen_framelock_errors.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END --> +<!-- Error definitions for proc_cen_framelock procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_INVALID_ARGS</rc> + <description>Invalid or out-of-range argument value(s) presented to proc_cen_framelock HWP.</description> + <ffdc>ARGS</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_INTERNAL_ERR</rc> + <description>Unexpected internal program logic error.</description> + <ffdc>ERR_DATA</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FL_CEN_FIR_ERR</rc> + <description>Framelock sequence set FIR bit in Centaur MBI FIR Register.</description> + <ffdc>FIR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR</rc> + <description>Framelock sequence set FIR bit in P8 MCI FIR Register.</description> + <ffdc>FIR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FL_CEN_FAIL_ERR</rc> + <description>Framelock sequence fail reported in Centaur MBI Status Register.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR</rc> + <description>Framelock sequence fail reported in P8 MCI Status Register.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR</rc> + <description>Framelock sequence timed out waiting for pass/fail indication in Centaur MBI Status Register or P8 MCI Status Register.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FIR_ERR</rc> + <description>FRTL sequence set FIR bit in Centaur MBI FIR Register.</description> + <ffdc>FIR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR</rc> + <description>FRTL sequence set FIR bit in P8 MCI FIR Register.</description> + <ffdc>FIR_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR</rc> + <description>FRTL sequence fail reported in Centaur MBI Status Register.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR</rc> + <description>FRTL sequence fail reported in P8 MCI Status Register.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR</rc> + <description>FRTL sequence timed out waiting for pass/fail indication in Centaur MBI Status Register or P8 MCI Status Register.</description> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H new file mode 100755 index 000000000..f7ca02897 --- /dev/null +++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H @@ -0,0 +1,436 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/common_scom_addresses.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: common_scom_addresses.H,v 1.1 2012/01/06 22:21:10 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : common_scom_addresses.H +// *! DESCRIPTION : Defines for common/generic scom addresses shared between P8/Centaur +// *! OWNER NAME : Jeshua Smith Email: jeshua@us.ibm.com +// *! BACKUP NAME : Email: @us.ibm.com +// #! ADDITIONAL COMMENTS : +// +// The purpose of this header is to define scom addresses for use by procedures. +// This will help catch address typos at compile time, and will make it easy +// to track down which procedures use each address +// + +#ifndef COMMON_SCOM_ADDRESSES +#define COMMON_SCOM_ADDRESSES + +//---------------------------------------------------------------------- +// Scom address overview +//---------------------------------------------------------------------- +// P8 uses 64-bit scom addresses, which are classified into two formats: +// +// "Normal" (legacy) format +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 00000000 00000000 00000000 00000000 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// || | | +// || | `-> Local Address* +// || | +// || `-> Port +// || +// |`-> Chiplet ID** +// | +// `-> Multicast bit +// +// * Local address is composed of "00" + 4-bit ring + 10-bit ID +// The 10-bit ID is usually 4-bit sat_id and 6-bit reg_id +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// +// "Indirect" format +// +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 10000000 0000IIII IIIIIGGG GGGLLLLL 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// | | | || | | +// | | | || | `-> Local Address* +// | | | || | +// | | | || `-> Port +// | | | || +// | | | |`-> Chiplet ID** +// | | | | +// | | | `-> Multicast bit +// | | | +// | | `-> Lane ID +// | | +// | `-> RX or TX Group ID +// | +// `-> Indirect Register Address +// +// * Local address is composed of "00" + 4-bit ring + 4-bit sat_id + "111111" +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// + +#include "fapi_sbe_common.h" + + +/******************************************************************************/ +/********************************** CHIPLET *********************************/ +/******************************************************************************/ +// use for lpcs P0, <chipletID> +CONST_UINT64_T( STBY_CHIPLET_0x00000000 , ULL(0x00000000) ); +CONST_UINT64_T( TP_CHIPLET_0x01000000 , ULL(0x01000000) ); +CONST_UINT64_T( NEST_CHIPLET_0x02000000 , ULL(0x02000000) ); + + +/******************************************************************************/ +/****************************** GENERIC CHIPLET *****************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// GENERIC GP +//------------------------------------------------------------------------------ +CONST_UINT64_T( GENERIC_GP0_0x00000000 , ULL(0x00000000) ); +CONST_UINT64_T( GENERIC_GP1_0x00000001 , ULL(0x00000001) ); +CONST_UINT64_T( GENERIC_GP2_0x00000002 , ULL(0x00000002) ); +CONST_UINT64_T( GENERIC_GP4_0x00000003 , ULL(0x00000003) ); +CONST_UINT64_T( GENERIC_GP0_AND_0x00000004 , ULL(0x00000004) ); +CONST_UINT64_T( GENERIC_GP0_OR_0x00000005 , ULL(0x00000005) ); + +//------------------------------------------------------------------------------ +// GENERIC CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( GENERIC_OPCG_CNTL0_0x00030002 , ULL(0x00030002) ); +CONST_UINT64_T( GENERIC_OPCG_CNTL1_0x00030003 , ULL(0x00030003) ); +CONST_UINT64_T( GENERIC_OPCG_CNTL2_0x00030004 , ULL(0x00030004) ); +CONST_UINT64_T( GENERIC_OPCG_CNTL3_0x00030005 , ULL(0x00030005) ); +CONST_UINT64_T( GENERIC_CLK_REGION_0x00030006 , ULL(0x00030006) ); +CONST_UINT64_T( GENERIC_CLK_SCANSEL_0x00030007 , ULL(0x00030007) ); +CONST_UINT64_T( GENERIC_CLK_STATUS_0x00030008 , ULL(0x00030008) ); +CONST_UINT64_T( GENERIC_CLK_SCANDATA0_0x00038000 , ULL(0x00038000) ); + +//------------------------------------------------------------------------------ +// GENERIC FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( GENERIC_XSTOP_0x00040000 , ULL(0x00040000) ); +CONST_UINT64_T( GENERIC_RECOV_0x00040001 , ULL(0x00040001) ); +CONST_UINT64_T( GENERIC_FIR_MASK_0x00040002 , ULL(0x00040002) ); +CONST_UINT64_T( GENERIC_SPATTN_0x00040004 , ULL(0x00040004) ); +CONST_UINT64_T( GENERIC_SPATTN_AND_0x00040005 , ULL(0x00040005) ); +CONST_UINT64_T( GENERIC_SPATTN_OR_0x00040006 , ULL(0x00040006) ); +CONST_UINT64_T( GENERIC_SPATTN_MASK_0x00040007 , ULL(0x00040007) ); +CONST_UINT64_T( GENERIC_FIR_MODE_0x00040008 , ULL(0x00040008) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_0x0004000A , ULL(0x0004000A) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_AND_0x0004000B , ULL(0x0004000B) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_OR_0x0004000C , ULL(0x0004000C) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_MASK_0x0004000D , ULL(0x0004000D) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_MASK_AND_0x0004000E , ULL(0x0004000E) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_MASK_OR_0x0004000F , ULL(0x0004000F) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_ACT0_0x00040010 , ULL(0x00040010) ); +CONST_UINT64_T( GENERIC_PERV_LFIR_ACT1_0x00040011 , ULL(0x00040011) ); + +//------------------------------------------------------------------------------ +// GENERIC PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( GENERIC_MCGR1_0x000F0001 , ULL(0x000F0001) ); +CONST_UINT64_T( GENERIC_MCGR2_0x000F0002 , ULL(0x000F0002) ); +CONST_UINT64_T( GENERIC_MCGR3_0x000F0003 , ULL(0x000F0003) ); +CONST_UINT64_T( GENERIC_MCGR4_0x000F0004 , ULL(0x000F0004) ); + +//GP3 Register +CONST_UINT64_T( GENERIC_GP3_0x000F0012 , ULL(0x000F0012) ); +CONST_UINT64_T( GENERIC_GP3_AND_0x000F0013 , ULL(0x000F0013) ); +CONST_UINT64_T( GENERIC_GP3_OR_0x000F0014 , ULL(0x000F0014) ); + +// PM GP0 Register +CONST_UINT64_T( GENERIC_PMGP0_OR_0x000F0102 , ULL(0x000F0102) ); + +//------------------------------------------------------------------------------ +// GENERIC HANG PULSE CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( GENERIC_HANG_P0_0x000F0020 , ULL(0x000F0020) ); +CONST_UINT64_T( GENERIC_HANG_P1_0x000F0021 , ULL(0x000F0021) ); +CONST_UINT64_T( GENERIC_HANG_P2_0x000F0022 , ULL(0x000F0022) ); +CONST_UINT64_T( GENERIC_HANG_PRE_0x000F0028 , ULL(0x000F0028) ); + + +/******************************************************************************/ +/******************************** TP CHIPLET ********************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// CFAM Registers +//------------------------------------------------------------------------------ +CONST_UINT32_T( CFAM_FSI_SHIFT_CTRL_0x00000C10 , ULL(0x00000C10) ); +CONST_UINT32_T( CFAM_FSI_STATUS_0x00001007 , ULL(0x00001007) ); +CONST_UINT32_T( CFAM_FSI_GP1_0x00001010 , ULL(0x00001010) ); +CONST_UINT32_T( CFAM_FSI_GP2_0x00001011 , ULL(0x00001011) ); +CONST_UINT32_T( CFAM_FSI_GP3_0x00001012 , ULL(0x00001012) ); +CONST_UINT32_T( CFAM_FSI_GP4_0x00001013 , ULL(0x00001013) ); +CONST_UINT32_T( CFAM_FSI_GP5_0x00001014 , ULL(0x00001014) ); +CONST_UINT32_T( CFAM_FSI_GP6_0x00001015 , ULL(0x00001015) ); +CONST_UINT32_T( CFAM_FSI_GP7_0x00001016 , ULL(0x00001016) ); +CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000101B , ULL(0x0000101B) ); + +//------------------------------------------------------------------------------ +// OTPROM +//------------------------------------------------------------------------------ +CONST_UINT64_T( OTPROM_0x00010000 , ULL(0x00010000) ); + +//------------------------------------------------------------------------------ +// MFSI0 +//------------------------------------------------------------------------------ +CONST_UINT64_T( MFSI0_0x00020000 , ULL(0x00020000) ); + +//------------------------------------------------------------------------------ +// MFSI1 +//------------------------------------------------------------------------------ +CONST_UINT64_T( MFSI1_0x00030000 , ULL(0x00030000) ); + +//------------------------------------------------------------------------------ +// TOD +//------------------------------------------------------------------------------ +CONST_UINT64_T( TOD_0x00040000 , ULL(0x00040000) ); + +//------------------------------------------------------------------------------ +// FSI MBOX +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBOX_FSIRESET_0x00050006 , ULL(0x00050006) ); +CONST_UINT64_T( MBOX_FSISTATUS_0x00050007 , ULL(0x00050007) ); +CONST_UINT64_T( MBOX_CFAMID_0x0005000A , ULL(0x0005000A) ); +CONST_UINT64_T( MBOX_TMASK_0x0005000D , ULL(0x0005000D) ); +CONST_UINT64_T( MBOX_CMASK_0x0005000C , ULL(0x0005000C) ); +CONST_UINT64_T( MBOX_FSIGP3_0x00050012 , ULL(0x00050012) ); +CONST_UINT64_T( MBOX_FSIGP4_0x00050013 , ULL(0x00050013) ); +CONST_UINT64_T( MBOX_FSIGP5_0x00050014 , ULL(0x00050014) ); +CONST_UINT64_T( MBOX_FSIGP6_0x00050015 , ULL(0x00050015) ); +CONST_UINT64_T( MBOX_FSIGP7_0x00050016 , ULL(0x00050016) ); +CONST_UINT64_T( MBOX_OSC_S1_0x00050019 , ULL(0x00050019) ); +CONST_UINT64_T( MBOX_OSC_S2_0x0005001A , ULL(0x0005001A) ); +CONST_UINT64_T( MBOX_GP3MIR_0x0005001B , ULL(0x0005001B) ); +CONST_UINT64_T( MBOX_SBEVITAL_0x0005001C , ULL(0x0005001C) ); + +//------------------------------------------------------------------------------ +// I2C MASTER (MEMS0) +//------------------------------------------------------------------------------ +CONST_UINT64_T( I2CMS_MEMS0_CONTROL_0x000A0000 , ULL(0x000A0000) ); +CONST_UINT64_T( I2CMS_MEMS0_RESET_0x000A0001 , ULL(0x000A0001) ); +CONST_UINT64_T( I2CMS_MEMS0_STATUS_0x000A0002 , ULL(0x000A0002) ); +CONST_UINT64_T( I2CMS_MEMS0_DATA_0x000A0003 , ULL(0x000A0003) ); +CONST_UINT64_T( I2CMS_MEMS0_COMMAND_0x000A0005 , ULL(0x000A0005) ); + +//------------------------------------------------------------------------------ +// PCB MASTER +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCBMS_0x000F0000 , ULL(0x000F0000) ); +CONST_UINT64_T( PCBMS_DEVICE_ID_0x000F000F , ULL(0x000F000F) ); +CONST_UINT64_T( MASTER_PCB_INT_0x000F001A , ULL(0x000F001A) ); +CONST_UINT64_T( PRV_PIB_PCBMS_RESET_REG_0x000F001D , ULL(0x000F001D) ); +CONST_UINT64_T( MASTER_PCB_ERR_0x000F001F , ULL(0x000F001F) ); + +//------------------------------------------------------------------------------ +// TP GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_GP0_0x01000000 , ULL(0x01000000) ); +CONST_UINT64_T( TP_GP1_0x01000001 , ULL(0x01000001) ); +CONST_UINT64_T( TP_GP2_0x01000002 , ULL(0x01000002) ); +CONST_UINT64_T( TP_GP4_0x01000003 , ULL(0x01000003) ); +CONST_UINT64_T( TP_GP0_AND_0x01000004 , ULL(0x01000004) ); +CONST_UINT64_T( TP_GP0_OR_0x01000005 , ULL(0x01000005) ); +CONST_UINT64_T( TP_GP4_AND_0x01000006 , ULL(0x01000006) ); +CONST_UINT64_T( TP_GP4_OR_0x01000007 , ULL(0x01000007) ); + +//------------------------------------------------------------------------------ +// TP SCOM +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_SCOM_0x01010000 , ULL(0x01010000) ); + +//------------------------------------------------------------------------------ +// TP ITR +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_OSC_MSK_0x0102001A , ULL(0x0102001A) ); + +//------------------------------------------------------------------------------ +// TP CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_OPCG_CNTL0_0x01030002 , ULL(0x01030002) ); +CONST_UINT64_T( TP_OPCG_CNTL1_0x01030003 , ULL(0x01030003) ); +CONST_UINT64_T( TP_OPCG_CNTL2_0x01030004 , ULL(0x01030004) ); +CONST_UINT64_T( TP_OPCG_CNTL3_0x01030005 , ULL(0x01030005) ); +CONST_UINT64_T( TP_CLK_REGION_0x01030006 , ULL(0x01030006) ); +CONST_UINT64_T( TP_CLK_SCANSEL_0x01030007 , ULL(0x01030007) ); +CONST_UINT64_T( TP_CLK_STATUS_0x01030008 , ULL(0x01030008) ); + +//------------------------------------------------------------------------------ +// TP FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_XSTOP_0x01040000 , ULL(0x01040000) ); +CONST_UINT64_T( TP_RECOV_0x01040001 , ULL(0x01040001) ); +CONST_UINT64_T( TP_FIR_MASK_0x01040002 , ULL(0x01040002) ); +CONST_UINT64_T( TP_SPATTN_0x01040004 , ULL(0x01040004) ); +CONST_UINT64_T( TP_SPATTN_AND_0x01040005 , ULL(0x01040005) ); +CONST_UINT64_T( TP_SPATTN_OR_0x01040006 , ULL(0x01040006) ); +CONST_UINT64_T( TP_SPATTN_MASK_0x01040007 , ULL(0x01040007) ); +CONST_UINT64_T( TP_FIR_MODE_0x01040008 , ULL(0x01040008) ); +CONST_UINT64_T( TP_PERV_LFIR_0x0104000A , ULL(0x0104000A) ); +CONST_UINT64_T( TP_PERV_LFIR_AND_0x0104000B , ULL(0x0104000B) ); +CONST_UINT64_T( TP_PERV_LFIR_OR_0x0104000C , ULL(0x0104000C) ); +CONST_UINT64_T( TP_PERV_LFIR_MASK_0x0104000D , ULL(0x0104000D) ); +CONST_UINT64_T( TP_PERV_LFIR_MASK_AND_0x0104000E , ULL(0x0104000E) ); +CONST_UINT64_T( TP_PERV_LFIR_MASK_OR_0x0104000F , ULL(0x0104000F) ); +CONST_UINT64_T( TP_PERV_LFIR_ACT0_0x01040010 , ULL(0x01040010) ); +CONST_UINT64_T( TP_PERV_LFIR_ACT1_0x01040011 , ULL(0x01040011) ); + +//------------------------------------------------------------------------------ +// TP PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( TP_MCGR1_0x010F0001 , ULL(0x010F0001) ); +CONST_UINT64_T( TP_MCGR2_0x010F0002 , ULL(0x010F0002) ); +CONST_UINT64_T( TP_MCGR3_0x010F0003 , ULL(0x010F0003) ); +CONST_UINT64_T( TP_MCGR4_0x010F0004 , ULL(0x010F0004) ); +//GP3 Register +//Figtree says GP3 register doesn't exist in TP chiplet +//CONST_UINT64_T( TP_GP3_0x010F0012 , ULL(0x010F0012) ); +//CONST_UINT64_T( TP_GP3_AND_0x010F0013 , ULL(0x010F0013) ); +//CONST_UINT64_T( TP_GP3_OR_0x010F0014 , ULL(0x010F0014) ); + +//------------------------------------------------------------------------------ +// TP HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_HANG_P1_0x010F0021 , ULL(0x010F0021) ); // PRV: setup hang pulse register0 +CONST_UINT64_T( TP_HANG_P2_0x010F0022 , ULL(0x010F0022) ); // PRV: setup hang pulse register1 +CONST_UINT64_T( TP_HANG_PRE_0x010F0028 , ULL(0x010F0028) ); // PRV: setup hang precounter (HEX:01) + + +/******************************************************************************/ +/******************************* NEST CHIPLET *******************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// NEST GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( NEST_GP0_0x02000000 , ULL(0x02000000) ); +CONST_UINT64_T( NEST_GP1_0x02000001 , ULL(0x02000001) ); +CONST_UINT64_T( NEST_GP2_0x02000002 , ULL(0x02000002) ); +CONST_UINT64_T( NEST_GP0_AND_0x02000004 , ULL(0x02000004) ); +CONST_UINT64_T( NEST_GP0_OR_0x02000005 , ULL(0x02000005) ); +CONST_UINT64_T( NEST_GP4_AND_0x02000006 , ULL(0x02000006) ); +CONST_UINT64_T( NEST_GP4_OR_0x02000007 , ULL(0x02000007) ); + +//------------------------------------------------------------------------------ +// NEST SCOM +//------------------------------------------------------------------------------ +CONST_UINT64_T( NEST_SCOM_0x02010000 , ULL(0x02010000) ); + +//------------------------------------------------------------------------------ +// NEST CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( NEST_OPCG_CNTL0_0x02030002 , ULL(0x02030002) ); +CONST_UINT64_T( NEST_OPCG_CNTL1_0x02030003 , ULL(0x02030003) ); +CONST_UINT64_T( NEST_OPCG_CNTL2_0x02030004 , ULL(0x02030004) ); +CONST_UINT64_T( NEST_OPCG_CNTL3_0x02030005 , ULL(0x02030005) ); +CONST_UINT64_T( NEST_CLK_REGION_0x02030006 , ULL(0x02030006) ); +CONST_UINT64_T( NEST_CLK_SCANSEL_0x02030007 , ULL(0x02030007) ); +CONST_UINT64_T( NEST_CLK_STATUS_0x02030008 , ULL(0x02030008) ); + +//------------------------------------------------------------------------------ +// NEST FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( NEST_XSTOP_0x02040000 , ULL(0x02040000) ); +CONST_UINT64_T( NEST_RECOV_0x02040001 , ULL(0x02040001) ); +CONST_UINT64_T( NEST_FIR_MASK_0x02040002 , ULL(0x02040002) ); +CONST_UINT64_T( NEST_SPATTN_0x02040004 , ULL(0x02040004) ); +CONST_UINT64_T( NEST_SPATTN_AND_0x02040005 , ULL(0x02040005) ); +CONST_UINT64_T( NEST_SPATTN_OR_0x02040006 , ULL(0x02040006) ); +CONST_UINT64_T( NEST_SPATTN_MASK_0x02040007 , ULL(0x02040007) ); +CONST_UINT64_T( NEST_FIR_MODE_0x02040008 , ULL(0x02040008) ); +CONST_UINT64_T( NEST_PERV_LFIR_0x0204000A , ULL(0x0204000A) ); +CONST_UINT64_T( NEST_PERV_LFIR_AND_0x0204000B , ULL(0x0204000B) ); +CONST_UINT64_T( NEST_PERV_LFIR_OR_0x0204000C , ULL(0x0204000C) ); +CONST_UINT64_T( NEST_PERV_LFIR_MASK_0x0204000D , ULL(0x0204000D) ); +CONST_UINT64_T( NEST_PERV_LFIR_MASK_AND_0x0204000E , ULL(0x0204000E) ); +CONST_UINT64_T( NEST_PERV_LFIR_MASK_OR_0x0204000F , ULL(0x0204000F) ); +CONST_UINT64_T( NEST_PERV_LFIR_ACT0_0x02040010 , ULL(0x02040010) ); +CONST_UINT64_T( NEST_PERV_LFIR_ACT1_0x02040011 , ULL(0x02040011) ); + +//------------------------------------------------------------------------------ +// NEST PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( NEST_MCGR1_0x020F0001 , ULL(0x020F0001) ); +CONST_UINT64_T( NEST_MCGR2_0x020F0002 , ULL(0x020F0002) ); +CONST_UINT64_T( NEST_MCGR3_0x020F0003 , ULL(0x020F0003) ); +CONST_UINT64_T( NEST_MCGR4_0x020F0004 , ULL(0x020F0004) ); +//GP3 Register +CONST_UINT64_T( NEST_GP3_0x020F0012 , ULL(0x020F0012) ); +CONST_UINT64_T( NEST_GP3_AND_0x020F0013 , ULL(0x020F0013) ); +CONST_UINT64_T( NEST_GP3_OR_0x020F0014 , ULL(0x020F0014) ); + +//------------------------------------------------------------------------------ +// NEST HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( NEST_HANG_P0_0x020F0020 , ULL(0x020F0020) ); // NEST (PB): setup hang pulse register0 +CONST_UINT64_T( NEST_HANG_P1_0x020F0021 , ULL(0x020F0021) ); // NEST : setup hang pulse register1 +CONST_UINT64_T( NEST_HANG_P2_0x020F0022 , ULL(0x020F0022) ); // NEST : setup hang pulse register2 +CONST_UINT64_T( NEST_HANG_P3_0x020F0023 , ULL(0x020F0023) ); // NEST : setup hang pulse register3 +CONST_UINT64_T( NEST_HANG_P4_0x020F0024 , ULL(0x020F0024) ); // NEST : setup hang pulse register4 +CONST_UINT64_T( NEST_HANG_PRE_0x020F0028 , ULL(0x020F0028) ); // NEST (PB): setup hang precounter (HEX:01) + + +//******************************************************************************/ +//********* ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/ +//******************************************************************************/ +CONST_UINT64_T( SCAN_ALLSCANEXVITAL, ULL(0x0FF00FFE00000000) ); +CONST_UINT64_T( SCAN_ALLSCANEXPRV, ULL(0x0FF00DCE00000000) ); +CONST_UINT64_T( SCAN_GPTR_TIME_REP, ULL(0x0FF0023000000000) ); +CONST_UINT64_T( SCAN_TIME_REP, ULL(0x0CF0003000000000) ); + +CONST_UINT8_T( SCAN_CHIPLET_TP, ULL(0x01) ); +CONST_UINT8_T( SCAN_CHIPLET_NEST, ULL(0x02) ); +CONST_UINT8_T( SCAN_CHIPLET_MEM, ULL(0x03) ); +CONST_UINT8_T( SCAN_CHIPLET_ALL, ULL(0x69) ); +CONST_UINT8_T( SCAN_CHIPLET_GROUP3, ULL(0x6B) ); + + +#endif + + +/* +*************** Do not edit this area *************** +This section is automatically updated by CVS when you check in this file. +Be sure to create CVS comments when you commit so that they can be included here. + +$Log: common_scom_addresses.H,v $ +Revision 1.1 2012/01/06 22:21:10 jmcgill +initial release + + + + +*/ diff --git a/src/usr/hwpf/hwp/makefile b/src/usr/hwpf/hwp/makefile index cc6d32303..f61ada852 100644 --- a/src/usr/hwpf/hwp/makefile +++ b/src/usr/hwpf/hwp/makefile @@ -35,5 +35,8 @@ OBJS = fapiTestHwp.o \ fapiTestHwpConfig.o \ fapiTestHwpAttr.o \ fapiHwpExecInitFile.o + +SUBDIRS = dmi_training.d + include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/template.C b/src/usr/hwpf/hwp/template.C new file mode 100644 index 000000000..eee84c019 --- /dev/null +++ b/src/usr/hwpf/hwp/template.C @@ -0,0 +1,101 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/HWPs/template.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END + +// notes: +// replace <@foo> with the tag string @foo +// replace <<@foo>> with an uppercased tag string @foo + +/** + * @file <@istepname>.C // @ + * + * Support file for IStep: + * <@istepname> // @ + * + * + * + */ + + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <kernel/console.H> +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> +#include <targeting/targetservice.H> +#include <fapi.H> + +// -- prototype includes -- +#include "<@istepname>.H" // @ +#include "<@substepname>/<@substepname>.H" // @ + +namespace <<@istepname>> // @ +{ +trace_desc_t *g_trac_<@istepname> = NULL; // @ +TRAC_INIT(&g_trac_dmi<@istepname>, "<<@istepname>>", 2048 ); // @ + +using namespace TARGETING; + +// +// Wrapper function to call <@istepnum>.<@substepnum> : <@substepname> +// +void call_<@substepname>( void *io_pArgs ) // @ +{ + INITSERVICE::TaskArgs *pTaskArgs = + static_cast<INITSERVICE::TaskArgs *>( io_pArgs ); + fapi::ReturnCode l_fapirc; + + TRACDCOMP( g_trac_dmi_training, "call_<@substepname> entry" ); //@ + + + // figure out what targets we need + +#if 0 + // call the HWP with each target ( if parallel, spin off a task ) + l_fapirc = <@substepname>( ? , ?, ? ); +#endif + + // process return code. + if ( l_fapirc != fapi::FAPI_RC_SUCCESS ) + { + /** + * @todo fapi error - just print out for now... + */ + TRACFCOMP( g_trac_dmi_training, + "ERROR : HWP returned %d ", + static_cast<uint32_t>(l_fapirc) ); + } + + TRACDCOMP( g_trac_dmi_training, "<@substepname> exit" ); //@ + + // wait here on the barrier, then end the task. + pTaskArgs->waitChildSync(); + task_end(); +} + + +}; // end namespace + diff --git a/src/usr/hwpf/hwp/template.H b/src/usr/hwpf/hwp/template.H new file mode 100644 index 000000000..c774c026a --- /dev/null +++ b/src/usr/hwpf/hwp/template.H @@ -0,0 +1,67 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/include/usr/hwas/hwas.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2011 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END + +// +// ######################################### +// THIS IS A GENERATED FILE +// ######################################### +// + +#ifndef __<@istepname>_<@istepname>_H +#define __<@istepname>_<@istepname>_H +/** + * @file <@istepname>.H + * + * <@istepname> + * + * All of the following routines are "named isteps" - they are invoked as + * tasks by the @ref IStepDispatcher. + * + */ + + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + + +namespace <@istepname> +{ + + /** + * @brief <@substepname> + * + * <@istepnum>.<@substepnum> : <@substepdesc> + * + * param[in,out] io_pArgs - (normally) a pointer to a TaskArgs struct, + * or NULL. + * return none + * + */ + void call_<@substepname>( void * io_pArgs ); + + +}; // end namespace + +#endif diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 58189d9f9..5236d9545 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -30,7 +30,11 @@ SUBDIRS = fapi.d hwp.d plat.d test.d #------------------------------------------------------------------------------ # Source XML files #------------------------------------------------------------------------------ -HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml +HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ + hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml \ + hwp/dmi_training/dmi_io_run_training/io_run_training_errors.xml + + HWP_ATTR_XML_FILES = hwp/fapiHwpAttributeInfo.xml \ hwp/memory_attributes.xml \ hwp/L2_L3_attributes.xml diff --git a/src/usr/initservice/baseinitsvc/initservice.C b/src/usr/initservice/baseinitsvc/initservice.C index e2066ed0d..fce383372 100644 --- a/src/usr/initservice/baseinitsvc/initservice.C +++ b/src/usr/initservice/baseinitsvc/initservice.C @@ -131,6 +131,12 @@ errlHndl_t InitService::executeFn( const TaskInfo *i_ptask, assert( i_ptask != NULL ); assert( i_ptask->taskfn != NULL ) ; + /** + * @todo: add Doug Gilbert's code here to look up the module based on + * the function pointer and then load the module. + * For now we just blindly load the module in istepdispatcher + */ + // valid function, launch it l_tidrc = task_create( i_ptask->taskfn, io_pargs); if (static_cast<int16_t> (l_tidrc) < 0) diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C index 84a18baae..dfa0fe6e7 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.C +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C @@ -38,6 +38,7 @@ #include <stdio.h> #include <string.h> +#include <vfs/vfs.H> // load_module #include <sys/task.h> // tid_t, task_create, etc #include <sys/time.h> // nanosleep #include <sys/misc.h> // shutdown @@ -126,6 +127,7 @@ using namespace SPLESS; // SingleStepMode extern trace_desc_t *g_trac_initsvc; /** + * @note SPLess PAUSE - These two constants are used in a nanosleep() call * below to sleep between polls of the StatusReg. Typically this will * be about 10 ms - the actual value will be determined empirically. @@ -140,37 +142,52 @@ const uint64_t SINGLESTEP_PAUSE_NS = 10000000; TASK_ENTRY_MACRO( IStepDispatcher::getTheInstance().init ); -const TaskInfo *IStepDispatcher::findTaskInfo( const uint16_t i_IStep, - const uint16_t i_SubStep ) const +const TaskInfo *IStepDispatcher::findTaskInfo( + const uint16_t i_IStep, + const uint16_t i_SubStep, + const char *&io_rmodulename ) const { const TaskInfo *l_pistep = NULL; + /** + * @todo + * everything calling this should feed into the "real" istep/substep + * numbers ( starting at 1 ) - this routine will translate to index into + * the isteplists ( starting at 0 ) + * + */ + //int16_t l_istepIndex = i_IStep-1; + //int16_t l_substepIndex = i_SubStep-1; + //assert( l_istepIndex >= 0 ); + //assert( l_substepIndex >= 0 ); // apply filters do { - // Sanity check / dummy IStep if ( g_isteps[i_IStep].pti == NULL) { TRACDCOMP( g_trac_initsvc, - "g_isteps[%d].pti == NULL", - i_IStep ); + "g_isteps[0x%x].pti == NULL (substep=0x%x)", + i_IStep, + i_SubStep ); break; } TRACDCOMP( g_trac_initsvc, - "g_isteps[%d].numitems = 0x%x", + "g_isteps[0x%x].numitems = 0x%x (substep=0x%x)", i_IStep, - g_isteps[i_IStep].numitems ); + g_isteps[i_IStep].numitems, + i_SubStep ); // check input range - IStep if ( i_IStep >= MAX_ISTEPS ) { TRACDCOMP( g_trac_initsvc, - "IStep 0x%x out of range.", - i_IStep ); + "IStep 0x%x out of range. (substep=0x%x) ", + i_IStep, + i_SubStep ); break; // break out with l_pistep set to NULL } @@ -195,12 +212,31 @@ const TaskInfo *IStepDispatcher::findTaskInfo( const uint16_t i_IStep, break; } + // check to see if the pointer to the function is NULL. + // This is possible if some of the substeps aren't working yet + // and are just placeholders. + if ( g_isteps[i_IStep].pti[i_SubStep].taskfn == NULL ) + { + TRACDCOMP( g_trac_initsvc, + "IStep 0x%x SubSStep 0x%x fn ptr is NULL.", + i_IStep, + i_SubStep ); + break; + } + + + l_pistep = &( g_isteps[i_IStep].pti[i_SubStep] ); + // find the name of the module that contains this function, + io_rmodulename = VFS::module_find_name( + reinterpret_cast<void*>(l_pistep->taskfn) ); // looks good, send it back to the caller TRACDCOMP( g_trac_initsvc, - "Found TaskInfo 0x%x 0x%x", + "Found TaskInfo 0x%p 0x%x 0x%x in module %s", + l_pistep, i_IStep, - i_SubStep ); - l_pistep = &( g_isteps[i_IStep].pti[i_SubStep] ); + i_SubStep, + ((io_rmodulename!=NULL)?io_rmodulename:"NULL???") ); + } while ( 0 ); @@ -277,11 +313,15 @@ void IStepDispatcher::processSingleIStepCmd( SPLessSingleIStepCmd l_cmd( i_rrawcmd ); // create a cleared status 0x00 reg SPLessSingleIStepSts l_sts; + const char *l_modulename = NULL; + + // look up istep+substep l_pistep = IStepDispatcher::getTheInstance().findTaskInfo( l_cmd.istep, - l_cmd.substep ); + l_cmd.substep, + l_modulename); do { @@ -327,6 +367,46 @@ void IStepDispatcher::processSingleIStepCmd( o_rrawsts.val64 = l_sts.val64; writeSts( o_rrawsts ); + + /** + * @todo temporary - executeFn will eventually figure out and + * load the correct module + */ + if ( ( l_modulename != NULL ) + && ( !VFS::module_is_loaded( l_modulename ) ) + ) + { + TRACDCOMP( g_trac_initsvc, + "loading module %s", + l_modulename ); + l_errl = VFS::module_load( l_modulename ); + if ( l_errl ) + { + // can't load module for istep, break out of inner loop + // with errl set + TRACFCOMP( g_trac_initsvc, + "Could not load module %s", + l_modulename ); + + l_sts.hdr.status = SPLESS_TASKRC_RETURNED_ERRLOG; + // go ahead and commit the errorlog + errlCommit( l_errl, INITSVC_COMP_ID ); + + // failed to load module, return error + l_sts.hdr.runningbit = false; + l_sts.hdr.readybit = true; + l_sts.hdr.status = SPLESS_TASKRC_FAIL_LOADMODULE; + l_sts.istep = l_cmd.istep; + l_sts.substep = l_cmd.substep; + l_sts.istepStatus = 0; + + // return to caller to write back to user console + o_rrawsts.val64 = l_sts.val64; + + break; + } + } + /** * @todo placeholder - set progress code before starting * This will not be finalized until the progress code driver @@ -524,6 +604,7 @@ void IStepDispatcher::runAllISteps( void * io_ptr ) const const TaskInfo *l_pistep = NULL; uint64_t l_progresscode = 0; uint64_t l_isteprc = 0; + const char *l_modulename = NULL; // taskargs struct for children TaskArgs::TaskArgs l_args; @@ -540,28 +621,51 @@ void IStepDispatcher::runAllISteps( void * io_ptr ) const l_SubStep < INITSERVICE::MAX_SUBSTEPS; l_SubStep++) { - TRACDCOMP( g_trac_initsvc, - "Find IStep=%d, SubStep=%d", - l_IStep, - l_SubStep ); - l_pistep = findTaskInfo( l_IStep, - l_SubStep ); + l_SubStep, + l_modulename ); if ( l_pistep == NULL ) { - TRACDCOMP( g_trac_initsvc, - "End of ISubStep 0x%x list.", l_SubStep ); break; // break out of inner for loop } + /** + * @todo temporary - executeFn will eventually figure out and + * load the correct module + */ + if ( ( l_modulename != NULL ) + && ( !VFS::module_is_loaded( l_modulename ) ) + ) + { + TRACDCOMP( g_trac_initsvc, + "loading module %s", + l_modulename ); + l_errl = VFS::module_load( l_modulename ); + if ( l_errl ) + { + // can't load module for istep, break out of inner loop + // with errl set + TRACFCOMP( g_trac_initsvc, + "Could not load module %s", + l_modulename ); + + break; + } + } + // @todo placeholder until progress codes are defined and // progress code driver is implemented. l_progresscode = ( (l_IStep<<16) | l_SubStep ); InitService::getTheInstance().setProgressCode( l_progresscode ); - l_args.clear(); + // print out what we are running + TRACFCOMP( g_trac_initsvc, + "Running IStep %s", + l_pistep->taskname ); + + l_args.clear(); l_errl = InitService::getTheInstance().executeFn( l_pistep, &l_args ); if ( l_errl ) diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.H b/src/usr/initservice/istepdispatcher/istepdispatcher.H index 586caa9ec..ae293c421 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.H +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.H @@ -148,16 +148,18 @@ private: * @brief Find a TaskInfo struct in the global istep list(s), * addressed by { IStep, SubStep } * - * - * @param[in] i_IStep - IStepNumber - * @param[in] i_SubStep - SubStepNumber + * @param[in] i_IStep - IStepNumber + * @param[in] i_SubStep - SubStepNumber + * @param[in,out] io_rmodulename - return name of module to load * * @return pointer to a TaskInfo struct * @retval pointer to a TaskInfo struct, or NULL * */ - const TaskInfo *findTaskInfo( uint16_t i_IStep, - uint16_t i_SubStep ) const; + const TaskInfo *findTaskInfo( + const uint16_t i_IStep, + const uint16_t i_SubStep, + const char *&io_rmodulename ) const; /** * @brief Command 0: Run the requested IStep/SubStep diff --git a/src/usr/initservice/istepdispatcher/splesscommon.H b/src/usr/initservice/istepdispatcher/splesscommon.H index 3699b4360..fceb1687d 100644 --- a/src/usr/initservice/istepdispatcher/splesscommon.H +++ b/src/usr/initservice/istepdispatcher/splesscommon.H @@ -93,6 +93,7 @@ enum { SPLESS_TASKRC_LAUNCH_FAIL = -4, // failed to launch the task SPLESS_TASKRC_RETURNED_ERRLOG = -5, // istep returned an errorlog SPLESS_TASKRC_TERMINATED = -6, // terminated the polling loop + SPLESS_TASKRC_FAIL_LOADMODULE = -7, // failed to load module SPLESS_INVALID_COMMAND = 10, // invalid command from user console SPLESS_AT_BREAK_POINT = 11, // invalid command at breakpoint diff --git a/src/usr/targeting/xmltohb/attribute_types.xml b/src/usr/targeting/xmltohb/attribute_types.xml index 94785e06a..7a05cd43d 100644 --- a/src/usr/targeting/xmltohb/attribute_types.xml +++ b/src/usr/targeting/xmltohb/attribute_types.xml @@ -2780,5 +2780,16 @@ <readable/> <writeable/> </attribute> +<attribute> + <id>CHIP_UNIT</id> + <description>A unit (chiplet) 's offset number within the chip. </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> </attributes> diff --git a/src/usr/targeting/xmltohb/simics_SALERNO.system.xml b/src/usr/targeting/xmltohb/simics_SALERNO.system.xml index afcdf1a98..b4584c0db 100644 --- a/src/usr/targeting/xmltohb/simics_SALERNO.system.xml +++ b/src/usr/targeting/xmltohb/simics_SALERNO.system.xml @@ -254,7 +254,11 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-0</default> - </attribute> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> diff --git a/src/usr/targeting/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/xmltohb/simics_VENICE.system.xml index 7d31d4d87..d0a5607a7 100644 --- a/src/usr/targeting/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/xmltohb/simics_VENICE.system.xml @@ -264,6 +264,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-0</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -277,6 +281,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-1</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> </targetInstance> <targetInstance> @@ -290,6 +298,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -302,6 +314,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> </attribute> </targetInstance> @@ -316,6 +332,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -329,6 +349,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-5</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -342,6 +366,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -355,6 +383,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p0 pervasive unit --> @@ -652,6 +684,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-0</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -664,6 +700,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -677,6 +717,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> </attribute> </targetInstance> @@ -691,6 +735,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -704,6 +752,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -716,6 +768,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-5</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> </attribute> </targetInstance> @@ -730,6 +786,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -743,6 +803,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-1/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p1 pervasive unit --> @@ -1041,6 +1105,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-0</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -1053,6 +1121,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -1067,6 +1139,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -1080,6 +1156,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -1093,6 +1173,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -1106,6 +1190,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-5</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -1119,6 +1207,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -1132,6 +1224,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-2/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p2 pervasive unit --> @@ -1428,6 +1524,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> </attribute> </targetInstance> @@ -1441,6 +1541,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -1455,6 +1559,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -1468,6 +1576,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -1481,6 +1593,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -1494,6 +1610,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-5</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -1507,6 +1627,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -1520,6 +1644,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-3/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p3 pervasive unit --> @@ -1817,6 +1945,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-0</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -1829,6 +1961,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -1843,6 +1979,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -1856,6 +1996,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -1869,6 +2013,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -1882,6 +2030,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-5</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -1895,6 +2047,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -1908,9 +2064,13 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> -<!-- Vencie n0p4 pervasive unit --> +<!-- Venice n0p4 pervasive unit --> <targetInstance> <id>sys0node0proc4pervasive0</id> @@ -2204,7 +2364,11 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-0</default> - </attribute> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -2217,6 +2381,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -2231,6 +2399,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -2244,6 +2416,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -2257,6 +2433,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -2270,6 +2450,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-5</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -2283,6 +2467,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -2296,6 +2484,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-5/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p5 pervasive unit --> @@ -2592,7 +2784,11 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-0</default> - </attribute> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -2605,6 +2801,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -2619,6 +2819,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -2632,6 +2836,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -2645,6 +2853,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -2658,6 +2870,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-5</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -2671,6 +2887,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -2684,6 +2904,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-6/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p6 pervasive unit --> @@ -2981,6 +3205,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-0</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -2993,6 +3221,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -3007,6 +3239,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -3020,6 +3256,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -3033,6 +3273,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -3045,7 +3289,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-5</default> - </attribute> + </attribute> <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -3059,6 +3306,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -3072,6 +3323,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-7/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p7 pervasive unit --> diff --git a/src/usr/targeting/xmltohb/target_types.xml b/src/usr/targeting/xmltohb/target_types.xml index 67e922b5d..cc35f03af 100644 --- a/src/usr/targeting/xmltohb/target_types.xml +++ b/src/usr/targeting/xmltohb/target_types.xml @@ -557,6 +557,7 @@ <default>MCS</default> </attribute> <attribute><id>MSS_MEMSIZE</id></attribute> + <attribute><id>CHIP_UNIT</id></attribute> </targetType> <targetType> @@ -566,6 +567,7 @@ <id>MODEL</id> <default>VENICE</default> </attribute> + <attribute><id>CHIP_UNIT</id></attribute> </targetType> <targetType> @@ -575,6 +577,7 @@ <id>MODEL</id> <default>SALERNO</default> </attribute> + <attribute><id>CHIP_UNIT</id></attribute> </targetType> <!-- Processor target types --> diff --git a/src/usr/targeting/xmltohb/vbu.system.xml b/src/usr/targeting/xmltohb/vbu.system.xml index 676565aca..294ca7633 100644 --- a/src/usr/targeting/xmltohb/vbu.system.xml +++ b/src/usr/targeting/xmltohb/vbu.system.xml @@ -260,7 +260,11 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-0</default> - </attribute> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> </targetInstance> <targetInstance> @@ -273,6 +277,10 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> </attribute> </targetInstance> @@ -287,6 +295,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-2</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> </targetInstance> <targetInstance> @@ -300,6 +312,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-3</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> </targetInstance> <targetInstance> @@ -313,6 +329,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-4</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>4</default> + </attribute> </targetInstance> <targetInstance> @@ -326,6 +346,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-5</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>5</default> + </attribute> </targetInstance> <targetInstance> @@ -339,6 +363,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-6</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>6</default> + </attribute> </targetInstance> <targetInstance> @@ -352,6 +380,10 @@ <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-0/mcs-7</default> </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>7</default> + </attribute> </targetInstance> <!-- Venice n0p0 pervasive unit --> |
