diff options
Diffstat (limited to 'src/usr')
| -rw-r--r-- | src/usr/scom/scom.C | 116 | ||||
| -rw-r--r-- | src/usr/scom/scomtrans.C | 356 | ||||
| -rw-r--r-- | src/usr/scom/scomtrans.H | 27 | ||||
| -rw-r--r-- | src/usr/scom/test/scomtest.H | 654 | ||||
| -rw-r--r-- | src/usr/targeting/xmltohb/simics_MURANO.system.xml | 496 | ||||
| -rw-r--r-- | src/usr/targeting/xmltohb/simics_VENICE.system.xml | 1009 | ||||
| -rw-r--r-- | src/usr/targeting/xmltohb/target_types.xml | 74 |
7 files changed, 2489 insertions, 243 deletions
diff --git a/src/usr/scom/scom.C b/src/usr/scom/scom.C index 0074c9a4e..b07dd8d87 100644 --- a/src/usr/scom/scom.C +++ b/src/usr/scom/scom.C @@ -133,15 +133,21 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, // OR in the 20bit indirect address l_io_buffer = l_io_buffer | temp_scomAddr; - // zero out the indirect address from the buffer.. - i_addr = i_addr & 0x00000000EFFFFFFFF; + // zero out the indirect address from the buffer.. + // bit 0-31 - indirect area.. + // bit 32 - always 0 + // bit 33-47 - bcast/chipletID/port + // bit 48-63 - local addr + i_addr = i_addr & 0x000000007FFFFFFF; + // If we are doing a read. We need to do a write first.. if(i_opType == DeviceFW::READ) { // use the chip-specific mutex attribute - l_mutex = i_target->getHbMutexAttr<TARGETING::ATTR_SCOM_IND_MUTEX>(); + l_mutex = + i_target->getHbMutexAttr<TARGETING::ATTR_SCOM_IND_MUTEX>(); mutex_lock(l_mutex); @@ -183,10 +189,13 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, } // if bit 32 is on indicating a complete bit - if ((*((uint64_t *)io_buffer) & SCOM_IND_COMPLETE_MASK) == SCOM_IND_COMPLETE_MASK) + if ((*((uint64_t *)io_buffer) & SCOM_IND_COMPLETE_MASK) + == SCOM_IND_COMPLETE_MASK) { - // check for bits 37-39 to be 011 indicating the read is valid - if ((*((uint64_t *)io_buffer) & SCOM_IND_ERROR_MASK) == SCOM_IND_READ_SUCCESS_MASK) + // check for bits 37-39 to be 011 + // indicating the read is valid + if ((*((uint64_t *)io_buffer) & SCOM_IND_ERROR_MASK) + == SCOM_IND_READ_SUCCESS_MASK) { // Clear out the other bits in the io_buffer // register to only return the read data to caller @@ -217,7 +226,7 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, // got an indirect read error // the data buffer is in tempIoData TRACFCOMP(g_trac_scom, - "INDIRECT SCOM READ= ERROR valid bits are not on.. type=0x%X", + "INDIRECT SCOM READ= ERROR valid bits are not on.. scomreg=0x%X", *((uint64_t *)io_buffer)); /*@ @@ -225,14 +234,15 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, * @moduleid SCOM::CHECK_INDIRECT_AND_DO_SCOM * @reasoncode SCOM::INDIRECT_SCOM_READ_FAIL * @userdata1 Address - * @userdata2 io_buffer data + * @userdata2 Scom data read from Address * @devdesc Indirect SCOM Read error */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - SCOM_CHECK_INDIRECT_AND_DO_SCOM, - SCOM_INDIRECT_READ_FAIL, - i_addr, - *((uint64_t *)io_buffer)); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + SCOM_CHECK_INDIRECT_AND_DO_SCOM, + SCOM_INDIRECT_READ_FAIL, + i_addr, + *((uint64_t *)io_buffer)); //@TODO - add usr details to the errorlog when we have one to // give better info regarding the fail.. @@ -243,7 +253,7 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, { // got an indirect read timeout TRACFCOMP(g_trac_scom, - "INDIRECT SCOM READ=indirect read timout .. type=0x%X", + "INDIRECT SCOM READ=indirect read timout .. scomreg=0x%X", *((uint64_t *)io_buffer)); @@ -252,17 +262,18 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, * @moduleid SCOM::CHECK_INDIRECT_AND_DO_SCOM * @reasoncode SCOM::INDIRECT_SCOM_READ_TIMEOUT * @userdata1 Address - * @userdata2 io_buffer data + * @userdata2 Scom data read from Address * @devdesc Indirect SCOM complete bit did not come on */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - SCOM_CHECK_INDIRECT_AND_DO_SCOM, - SCOM_INDIRECT_READ_TIMEOUT, - i_addr, - *((uint64_t *)io_buffer)); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + SCOM_CHECK_INDIRECT_AND_DO_SCOM, + SCOM_INDIRECT_READ_TIMEOUT, + i_addr, + *((uint64_t *)io_buffer)); - //@TODO - add usr details to the errorlog when we have one to - // give better info regarding the fail.. + //@TODO - add usr details to the errorlog when we have + // one to give better info regarding the fail.. } } @@ -305,11 +316,13 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, } // if bit 32 is on indicating a complete bit - if ((temp_io_buffer & SCOM_IND_COMPLETE_MASK) == SCOM_IND_COMPLETE_MASK) + if ((temp_io_buffer & SCOM_IND_COMPLETE_MASK) + == SCOM_IND_COMPLETE_MASK) { - // The write is valid when bits 37-39 are 010.. if not on return error - // check for bits 37-39 to not be 010 - if ((temp_io_buffer & SCOM_IND_ERROR_MASK) != SCOM_IND_WRITE_SUCCESS_MASK) + // The write is valid when bits 37-39 are 010.. + // if not on return error + if ((temp_io_buffer & SCOM_IND_ERROR_MASK) + != SCOM_IND_WRITE_SUCCESS_MASK) { // bits did not get turned on.. set error to true. l_indScomError = true; @@ -331,24 +344,25 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, if (l_indScomError == true) { // got an indirect write error - TRACFCOMP(g_trac_scom, "INDIRECT SCOM WRITE= ERROR valid bits are not on.. type=0x%X", temp_io_buffer); + TRACFCOMP(g_trac_scom, "INDIRECT SCOM WRITE= ERROR valid bits are not on.. scomreg=0x%X", temp_io_buffer); /*@ * @errortype - * @moduleid SCOM::CHECK_INDIRECT_AND_DO_SCOM - * @reasoncode SCOM::INDIRECT_SCOM_WRITE_FAIL - * @userdata1 Address - * @userdata2 io_buffer data - * @devdesc Indirect SCOM Write failed for this address + * @moduleid SCOM::CHECK_INDIRECT_AND_DO_SCOM + * @reasoncode SCOM::INDIRECT_SCOM_WRITE_FAIL + * @userdata1 Address + * @userdata2 Scom data read from Address + * @devdesc Indirect SCOM Write failed for this address */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - SCOM_CHECK_INDIRECT_AND_DO_SCOM, - SCOM_INDIRECT_WRITE_FAIL, - i_addr, - temp_io_buffer); + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + SCOM_CHECK_INDIRECT_AND_DO_SCOM, + SCOM_INDIRECT_WRITE_FAIL, + i_addr, + temp_io_buffer); - //@TODO - add usr details to the errorlog when we have one to - // give better info regarding the fail.. + //@TODO - add usr details to the errorlog when we have + // one to give better info regarding the fail.. } // if we got a timeout, create an errorlog. @@ -356,7 +370,7 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, { // got an indirect write timeout TRACFCOMP(g_trac_scom, - "INDIRECT SCOM READ=indirect write timout .. type=0x%X", + "INDIRECT SCOM READ=indirect write timout .. scomreg=0x%X", temp_io_buffer); @@ -365,17 +379,19 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType, * @moduleid SCOM::CHECK_INDIRECT_AND_DO_SCOM * @reasoncode SCOM::INDIRECT_SCOM_WRITE_TIMEOUT * @userdata1 Address - * @userdata2 io_buffer data - * @devdesc Indirect SCOM write timeout, complete bit did not come one + * @userdata2 Scom data read from Address + * @devdesc Indirect SCOM write timeout, complete + * bit did not come one */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - SCOM_CHECK_INDIRECT_AND_DO_SCOM, - SCOM_INDIRECT_WRITE_TIMEOUT, - i_addr, - temp_io_buffer); - - //@TODO - add usr details to the errorlog when we have one to - // give better info regarding the fail.. + l_err = new ERRORLOG::ErrlEntry( + ERRORLOG::ERRL_SEV_UNRECOVERABLE, + SCOM_CHECK_INDIRECT_AND_DO_SCOM, + SCOM_INDIRECT_WRITE_TIMEOUT, + i_addr, + temp_io_buffer); + + //@TODO - add usr details to the errorlog when we have + // one to give better info regarding the fail.. } } diff --git a/src/usr/scom/scomtrans.C b/src/usr/scom/scomtrans.C index d1141582d..73e9f4fb6 100644 --- a/src/usr/scom/scomtrans.C +++ b/src/usr/scom/scomtrans.C @@ -88,8 +88,8 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, { errlHndl_t l_err = NULL; - bool l_invalidAddr = false; + uint64_t l_instance = 0; uint64_t i_addr = va_arg(i_args,uint64_t); @@ -105,22 +105,21 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, { // Below are the assumptions used for the EX translate - /*EX - Mask : 0x1F00_0000 - Range 1 : 0x1000_0000 - 0x10FF_FFFF - ... - ... - bits 3:7 correspond to what EX chiplet is targeted. - where 0x10XXXXXX is for EX0 - ... - where 0x13XXXXXX is for EX3 - where 0x14XXXXXX is for EX4 - ... - where 0x1CXXXXXX is for EX12 - - - original mask = 0x000000001F000000 - change that to be 0x7F000000 to catch other chiplets.*/ + // EX + // Mask : 0x1F00_0000 + // Range 1 : 0x1000_0000 - 0x10FF_FFFF + // + // bits 3:7 correspond to what EX chiplet is targeted. + // where 0x10XXXXXX is for EX0 + // + // where 0x13XXXXXX is for EX3 + // where 0x14XXXXXX is for EX4 + // ... + // where 0x1CXXXXXX is for EX12 + + // EX Mask = 0x7F000000 to catch other chiplets. + + // no indirect addresses to worry about*/ // check to see that the Address is in the correct range if ((i_addr & SCOM_TRANS_EX_MASK) == SCOM_TRANS_EX_BASEADDR) @@ -142,28 +141,25 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, } else if (l_type == TARGETING::TYPE_MCS) { - /* ring 6 = MCL - MC0 MCS0 = 0x02011800 MCS-0 range 0 - MC0 MCS1 = 0x02011880 MCS-1 range 0 + remainder - MC1 MCS0 = 0x02011900 MCS-2 range 1 - MC1 MCS0 = 0x02011980 MCS-3 range 1 + remainder - IOMC0 = 0x02011A00 -NOT targeting this range.. - ring 7 = MCR - MC2 MCS0 = 0x02011C00 MCS-4 range 2 - MC2 MCS1 = 0x02011C80 MCS-5 range 2 + remainder - MC3 MCS0 = 0x02011D00 MCS-6 range 3 - MC3 MCS1 = 0x02011D80 MCS-7 range 3 + remainder - - original mask = 0x0000000002011D80 - Need the mask to be 0x7FFFFF80*/ - - - uint64_t l_instance; - - // Check that we are working with the correct address range + + // MC0 MCS0 = 0x02011800 MCS-0 range 0 + // MC0 MCS1 = 0x02011880 MCS-1 range 0 + remainder + // MC1 MCS0 = 0x02011900 MCS-2 range 1 + // MC1 MCS0 = 0x02011980 MCS-3 range 1 + remainder + // IOMC0 = 0x02011A00 -NOT targeting this range.. + + // MC2 MCS0 = 0x02011C00 MCS-4 range 2 + // MC2 MCS1 = 0x02011C80 MCS-5 range 2 + remainder + // MC3 MCS0 = 0x02011D00 MCS-6 range 3 + // MC3 MCS1 = 0x02011D80 MCS-7 range 3 + remainder + + + // SCOM_TRANS_MCS_MASK = 0xFFFFFFFF7FFFFF80 + + + // Check that we are working with the correct MCS direct address range if ((i_addr & SCOM_TRANS_MCS_MASK) == SCOM_TRANS_MCS_BASEADDR ) { - // Need to extract what instance of the entity we are at l_instance = epath.pathElementOfType(TARGETING::TYPE_MCS).instance; @@ -197,6 +193,67 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, TARGETING::TYPE_PROC, i_target); } + // 0x00000000_02011A00 MCS 0-3 # MCS/DMI0 Direct SCOM + // 0x00000000_02011E00 MCS 4-7 # MCS/DMI4 Direct SCOM + // Address translation from DMI0 (A->E) + // SCOM_TRANS_MCS_DMI_BASEADDR = 0x0000000002011A00, + // If the base address passed in is 0x2011A00 - we are dealing with + // MCS/DMI. Use the instance to determine which one wanted. If + // MCS 4-7 is targeted, translations is required. + // + // Also if we have a indirect address then we need to update the + // same address bits as above whether indirect or not.. for + // indirect specifically need to update bits 25-26 to get the + // correct address range. + + // MCS Indirect mask = 0x80000060_FFFFFFFF + // 0x80000000_02011A3F MCS 0 # DMI0 Indirect SCOM + // 0x80000020_02011A3F MCS 1 # DMI1 Indirect SCOM + // 0x80000040_02011A3F MCS 2 # DMI2 Indirect SCOM + // 0x80000060_02011A3F MCS 3 # DMI3 Indirect SCOM + // 0x80000000_02011E3F MCS 4 # DMI4 Indirect SCOM + // 0x80000020_02011E3F MCS 5 # DMI5 Indirect SCOM + // 0x80000040_02011E3F MCS 6 # DMI6 Indirect SCOM + // 0x80000060_02011E3F MCS 7 # DMI7 Indirect SCOM + // SCOM_TRANS_IND_MCS_BASEADDR = 0x8000000002011A00, + + // check that we are working with a MCS/DMI address range.. + // can be indirect or direct. + else if (((i_addr & SCOM_TRANS_MCS_MASK) == + SCOM_TRANS_MCS_DMI_BASEADDR) || ((i_addr & SCOM_TRANS_IND_MCS_DMI_MASK) == + SCOM_TRANS_IND_MCS_DMI_BASEADDR)) + { + + // Need to extract what instance of the entity we are at + l_instance = + epath.pathElementOfType(TARGETING::TYPE_MCS).instance; + + // If we are dealing with an indirect SCOM MCS address + // Need to update the address based on instance + if ((i_addr & SCOM_TRANS_IND_MCS_DMI_MASK) == + SCOM_TRANS_IND_MCS_DMI_BASEADDR) + { + + // Need to update the upper bits of the indirect scom address. + uint64_t temp_instance = l_instance % 4; + temp_instance = temp_instance << 37; + i_addr = i_addr | temp_instance; + } + + // Need to update the address whether we are indirect or not + // for the MCS/DMI address ranges. + // need to do this check after above because we modify the base + // address based on instance and the mask check would then fail + if (l_instance > 3) + { + // or 0x400 to change 0x2011Axx to 0x2011Exx + i_addr = i_addr | 0x400; + } + // Call to set the target to the parent target type + l_err = scomfindParentTarget(epath, + TARGETING::TYPE_PROC, + i_target); + } else { l_invalidAddr = true; @@ -204,58 +261,124 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, } else if (l_type == TARGETING::TYPE_XBUS) { - //*** temporarily put an error log indicating not supported until we - // have info from the hardware team + // XBUS Direct Address info + // XBUS mask = 0xFFFFFC00 + // default>physical:sys-0/node-0/proc-0/xbus-0</default> + // startAddr target + // 0x04011000 XBUS 0 # XBUS0 Direct SCOM + // 0x04011400 XBUS 1 # XBUS1 Direct SCOM + // 0x04011C00 XBUS 2 # XBUS2 Direct SCOM + // 0x04011800 XBUS 3 # XBUS3 Direct SCOM + // + // XBUS Indirect Address info + // mask = 0x80000000_FFFFFFFF + // 0x800000000401103F XBUS 0 # XBUS0 Indirect SCOM + // 0x800000000401143F XBUS 1 # XBUS1 Indirect SCOM + // 0x8000000004011C3F XBUS 2 # XBUS2 Indirect SCOM + // 0x800000000401183F XBUS 3 # XBUS3 Indirect SCOM + + + // no differentiation between direct and indirect.. translate the same way + // Check that we are working with the correct address range + if ((i_addr & SCOM_TRANS_XBUS_MASK) == SCOM_TRANS_XBUS_BASEADDR ) + { - TRACFCOMP(g_trac_scom, "SCOM_TRANSLATE-unsupported target type=0x%X", l_type); + // Need to extract what instance of the entity we are at + l_instance = + epath.pathElementOfType(TARGETING::TYPE_XBUS).instance; - /*@ - * @errortype - * @moduleid SCOM::SCOM_TRANSLATE - * @reasoncode SCOM::SCOM_TRANS_UNSUPPORTED_XBUS - * @userdata1 Address - * @userdata2 Target Type that failed - * @devdesc Scom Translate not supported for this type - */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - SCOM_TRANSLATE, - SCOM_TRANS_UNSUPPORTED_XBUS, - i_addr, - l_type); + // based on the instance, update the address + if (l_instance != 0) + { + // zero out the address bits that need to change + i_addr = i_addr & 0xFFFFFFFFFFFFF3FF; + + // range 1 - add 0x400 to the addr + if (l_instance == 1) + { + i_addr += 0x400; + } + // range 2 - add 0xC00 to the addr + else if (l_instance == 2) + { + i_addr += 0xC00; + } + // range 3 - add 0x800 to the addr + else if (l_instance == 3) + { + i_addr += 0x800; + } + + } + + // Call to set the target to the parent target type + l_err = scomfindParentTarget(epath, + TARGETING::TYPE_PROC, + i_target); + } + else + { + l_invalidAddr = true; + } } else if (l_type == TARGETING::TYPE_ABUS) { - //*** temporarily put an error log indicating not supported until we have info - // from the hardware team - TRACFCOMP(g_trac_scom, "SCOM_TRANSLATE-unsupported target type=0x%X", l_type); + // ABUS + // Mask : 0xFFFFFC00 + // Range 1 : 0x08010C00 - 0x08010C3F + + // default>physical:sys-0/node-0/proc-0/abus-0</default> + // ABUS Direct addresses + // ABUS mask 0x000000FF_FFFFFF80 + // 0x00000000_08010C00 # ABUS0-2 Direct SCOM + // + // Abus Indirect Addresses + // Abus Indirect MASK = 0x80000060FFFFFFFF + // 0x80000000_08010C3F ABUS 0 # ABUS0 Indirect SCOM + // 0x80000020_08010C3F ABUS 1 # ABUS1 Indirect SCOM + // 0x80000040_08010C3F ABUS 2 # ABUS2 Indirect SCOM - /*@ - * @errortype - * @moduleid SCOM::SCOM_TRANSLATE - * @reasoncode SCOM::SCOM_TRANS_UNSUPPORTED_ABUS - * @userdata1 Address - * @userdata2 Target Type that failed - * @devdesc Scom Translate not supported for this type - */ - l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE, - SCOM_TRANSLATE, - SCOM_TRANS_UNSUPPORTED_ABUS, - i_addr, - l_type); + + // Check that we are working with the correct address range + // the base address bits 32 to 64 are the same for both + if ((i_addr & SCOM_TRANS_ABUS_MASK) == SCOM_TRANS_ABUS_BASEADDR ) + { + // If we have an indirect address.. then need to translate + if ((i_addr & SCOM_TRANS_INDIRECT_MASK) == SCOM_TRANS_INDIRECT_ADDRESS) + { + + // Need to extract what instance of the entity we are at + l_instance = + epath.pathElementOfType(TARGETING::TYPE_ABUS).instance; + + + // Need to update the upper bits of the indirect scom address. + uint64_t temp_instance = l_instance << 37; + i_addr = i_addr | temp_instance; + + } + // get the parent.. + l_err = scomfindParentTarget(epath, + TARGETING::TYPE_PROC, + i_target); + } + + else + { + // got and error.. bad address.. write an errorlog.. + l_invalidAddr = true; + } } else if (l_type == TARGETING::TYPE_MBS) { - /* - MBS - Mask : NA - Range 1 : 0x02010000 - 0x0201FFFF + // MBS + // Mask : NA + // Range 1 : 0x02010000 - 0x0201FFFF + // default>physical:sys-0/node-0/membuf-10/mbs-0</default> - default>physical:sys-0/node-0/membuf-10/mbs-0</default> - - */ // NO address shifting required.. no mask.. // just get parent. l_err = scomfindParentTarget(epath, @@ -265,30 +388,35 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, } else if (l_type == TARGETING::TYPE_MBA) { - /* - MBA - Mask : 0x03010800 - Range 1 : 0x03010400 - 0301043F # MBA01 - Range 2 : 0x03010600 - 030106FF # MBA01 MCBIST - Range 4 : 0x03010C00 - 03010C3F # MBA23 - Range 5 : 0x03010E00 - 03010EFF # MBA23 MCBIST - - Original mask from hdw team is: 03010800 - The mask needs to be 0x7FFFF800 in order make sure we - don't have any other valid address bits on for another - chiplet. - - bits 20 correspond to what MBA chiplet is targeted. - where 0x03010000 is for MBA01 - where 0x03010800 is for MBA23 - - In the XML.. the - <default>physical:sys-0/node-0/membuf-10/mbs-0/mba-1</default> - - Assuming the MBA we are accessing is under the Centaur - not the processor.. for now. - */ - // check to see that the Address is in the correct range + // MBA + // SCOM_TRANS_MBA_MASK = 0xFFFFFFFF7FFFFC00, + // SCOM_TRANS_MBA_BASEADDR = 0x0000000003010400, + // + // In the XML.. the + // <default>physical:sys-0/node-0/membuf-10/mbs-0/mba-1</default> + // + // Assuming the MBA we are accessing is under the Centaur + // not the processor.. for now. + // + // 0x00000000_03010400 MBA 0 # MBA01 + // 0x00000000_03010C00 MBA 1 # MBA23 + // + // + // 0x00000000_03011400 MBA 0 # DPHY01 (indirect addressing) + // 0x00000000_03011800 MBA 1 # DPHY23 (indirect addressing) + + // 0x80000000_0301143f MBA 0 # DPHY01 (indirect addressing) + // 0x80000000_0301183f MBA 1 # DPHY23 (indirect addressing) + + // 0x80000000_0701143f MBA 0 # DPHY01 (indirect addressing) + // 0x80000000_0701183f MBA 1 # DPHY23 (indirect addressing) + // + // SCOM_TRANS_IND_MBA_MASK = 0x80000000FFFFFFFF, + // SCOM_TRANS_IND_MBA_BASEADDR = 0x800000000301143f, + + + // check to see that the Address is in the correct direct + // scom MBA address range. if ((i_addr & SCOM_TRANS_MBA_MASK) == SCOM_TRANS_MBA_BASEADDR) { @@ -300,7 +428,28 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, i_target, i_addr ); } - else + // check to see if valid MBA 0 indirect address range + else if ((i_addr & SCOM_TRANS_IND_MBA_MASK) == + SCOM_TRANS_IND_MBA_BASEADDR) + { + // Need to extract what instance of the entity we are + l_instance = + epath.pathElementOfType(TARGETING::TYPE_MBA).instance; + + // If instance is 1 then need to update address + if (l_instance == 1) + { + // Have address 0301143f need address 0301183f + i_addr = i_addr & 0xFFFFFFFFFFFFFBFF; + i_addr = i_addr | 0x00000800; + } + + // Call to set the target to the parent target type + l_err = scomfindParentTarget(epath, + TARGETING::TYPE_MEMBUF, + i_target); + } + else { // got and error.. bad address.. write an errorlog.. l_invalidAddr = true; @@ -308,8 +457,7 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType, } else { - //*** temporarily put an error log indicating not supported until we have info - // from the hardware team + // Send an errorlog because we are called with an unsupported type. TRACFCOMP(g_trac_scom, "SCOM_TRANSLATE.. Invalid target type=0x%X", l_type); /*@ @@ -373,7 +521,7 @@ errlHndl_t scomPerformTranslate(TARGETING::EntityPath i_epath, TARGETING::TYPE i_ctype, TARGETING::TYPE i_ptype, int i_shift, - int i_mask, + uint64_t i_mask, TARGETING::Target * &o_target, uint64_t &i_addr ) { diff --git a/src/usr/scom/scomtrans.H b/src/usr/scom/scomtrans.H index e65cc3511..d57e414dd 100644 --- a/src/usr/scom/scomtrans.H +++ b/src/usr/scom/scomtrans.H @@ -35,16 +35,29 @@ namespace SCOM enum ScomTransMask { - SCOM_TRANS_EX_MASK = 0x000000007F000000, - SCOM_TRANS_MCS_MASK = 0x000000007FFFFF80, - SCOM_TRANS_MBA_MASK = 0x000000007FFFF800, + SCOM_TRANS_EX_MASK = 0xFFFFFFFF7F000000, + SCOM_TRANS_MCS_MASK = 0xFFFFFFFF7FFFFF80, + SCOM_TRANS_MBA_MASK = 0xFFFFFFFF7FFFFC00, + SCOM_TRANS_XBUS_MASK = 0x00000000FFFFFC00, + SCOM_TRANS_IND_MCS_DMI_MASK = 0x80000060FFFFFFFF, + SCOM_TRANS_IND_MBA_MASK = 0x80000000FFFFFFFF, + SCOM_TRANS_ABUS_MASK = 0x000000FFFFFFFC00, + SCOM_TRANS_INDIRECT_MASK = 0x8000000000000000, }; enum ScomTransBaseAddr { - SCOM_TRANS_EX_BASEADDR = 0x0000000010000000, - SCOM_TRANS_MCS_BASEADDR = 0x0000000002011800, - SCOM_TRANS_MBA_BASEADDR = 0x0000000003010000, + SCOM_TRANS_EX_BASEADDR = 0x0000000010000000, + SCOM_TRANS_MCS_BASEADDR = 0x0000000002011800, + SCOM_TRANS_MCS_DMI_BASEADDR = 0x0000000002011A00, + SCOM_TRANS_IND_MCS_BASEADDR = 0x8000000002011A00, + SCOM_TRANS_MBA_BASEADDR = 0x0000000003010400, + // SCOM_TRANS_MBS_DPHY_BASEADDR = 0x0000000003011000, + SCOM_TRANS_XBUS_BASEADDR = 0x0000000004011000, + SCOM_TRANS_ABUS_BASEADDR = 0x0000000008010C00, + SCOM_TRANS_IND_MBA_BASEADDR = 0x800000000301143f, + SCOM_TRANS_IND_MCS_DMI_BASEADDR = 0x8000000002011A3F, + SCOM_TRANS_INDIRECT_ADDRESS = 0x8000000000000000, }; @@ -95,7 +108,7 @@ errlHndl_t scomPerformTranslate(TARGETING::EntityPath i_epath, TARGETING::TYPE i_ctype, TARGETING::TYPE i_ptype, int i_shift, - int i_mask, + uint64_t i_mask, TARGETING::Target * &o_target, uint64_t &i_addr ); diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H index 7d88b0da0..65ddd78ef 100644 --- a/src/usr/scom/test/scomtest.H +++ b/src/usr/scom/test/scomtest.H @@ -34,7 +34,7 @@ #include <errl/errlentry.H> #include <devicefw/userif.H> #include <fsi/fsiif.H> -#include <sys/time.h> //mc99 remove +#include <targeting/util.H> extern trace_desc_t* g_trac_scom; @@ -92,18 +92,18 @@ public: else if((TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL == scom_targets[x]) || (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom)) { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is the MASTER Sentinal or is set to use Xscom, exiting test", x ); + TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is the MASTER Sentinal or is set to use Xscom, exiting test", x ); scom_targets[x] = NULL; //remove from our list } // skip if fsi scom is not enabled else if(0 == scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom) { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> useFsiScom set to zero on target %d", x ); + TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> useFsiScom set to zero on target %d", x ); scom_targets[x] = NULL; //remove from our list } else if( !FSI::isSlavePresent(scom_targets[x]) ) { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is not present", x ); + TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is not present", x ); scom_targets[x] = NULL; //remove from our list } } @@ -235,17 +235,17 @@ public: (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom) || (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useInbandScom)) { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is the MASTER Sentinal or is set to use Xscom or Inband Scom, exiting test", x ); + TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is the MASTER Sentinal or is set to use Xscom or Inband Scom, exiting test", x ); scom_targets[x] = NULL; //remove from our list } else if(0 == scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom) { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> useFsiScom set to zero on target %d", x ); + TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> useFsiScom set to zero on target %d", x ); scom_targets[x] = NULL; //remove from our list } else if( !FSI::isSlavePresent(scom_targets[x]) ) { - TRACFCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is not present", x ); + TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is not present", x ); scom_targets[x] = NULL; //remove from our list } } @@ -271,7 +271,7 @@ public: // write all the test registers for( uint64_t x = 0; x < NUM_ADDRS; x++ ) { - TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x, test_data[x].addr, test_data[x].target ); + TRACDCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x, test_data[x].addr, test_data[x].target ); //only run if the target exists if(test_data[x].target == NULL) @@ -298,7 +298,7 @@ public: // read all the test registers for( uint64_t x = 0; x < NUM_ADDRS; x++ ) { - TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x, test_data[x].addr, test_data[x].target ); + TRACDCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x, test_data[x].addr, test_data[x].target ); //only run if the target exists if(test_data[x].target == NULL) @@ -349,18 +349,11 @@ public: //@VBU workaround - Disable Indirect SCOM test case o //Test case read/writes to valid addresses and is //potentially destructive on VBU - TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); - syspath.addLast(TARGETING::TYPE_SYS,0); - TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); - uint8_t vpo_mode = 0; - if( sys - && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode) - && (vpo_mode == 1) ) + if (TARGETING::is_vpo()) { - return; + return; } - // Setup some targets to use enum { myPROC9, @@ -386,15 +379,15 @@ public: //only run if the target exists if(scom_targets[x] == NULL) { - TRACFCOMP( g_trac_scom, "ScomTest - TARGET = NULL - 1 x = %d", x); + TRACDCOMP( g_trac_scom, "ScomTest - TARGET = NULL - 1 x = %d", x); continue; } else if ((scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) && (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0)) { - // If both FSI and XSCOM are not enabled.. then ignore.. - TRACFCOMP(g_trac_scom, "INDIRECT SCOM>> SKIPPING "); - scom_targets[x] = NULL; //remove from our list + // If both FSI and XSCOM are not enabled.. then ignore.. + TRACDCOMP(g_trac_scom, "INDIRECT SCOM>> SKIPPING "); + scom_targets[x] = NULL; //remove from our list } } @@ -500,15 +493,9 @@ public: //@VBU workaround - Disable Indirect SCOM test case o //Test case read/writes to valid addresses and is //potentially destructive on VBU - TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); - syspath.addLast(TARGETING::TYPE_SYS,0); - TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); - uint8_t vpo_mode = 0; - if( sys - && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode) - && (vpo_mode == 1) ) + if (TARGETING::is_vpo()) { - return; + return; } // Setup some targets to use @@ -539,7 +526,7 @@ public: (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0)) { // If both FSI and XSCOM are not enabled.. then ignore.. - TRACFCOMP(g_trac_scom, "TRANSLATE SCOM>> SKIPPING "); + TRACDCOMP(g_trac_scom, "TRANSLATE SCOM>> SKIPPING "); scom_targets[myProc0] = NULL; //remove from our list } @@ -566,9 +553,9 @@ public: uint64_t addr; uint64_t data; } test_data[] = { - { scom_targets[myEX1], 0x100F0120 ,0x7676767676767676}, - { scom_targets[myEX5], 0x100F0166, 0x9191919191919191}, - { scom_targets[myEX5], 0x130F0166, 0xabcdabcdabcdabcd}, // invalid unit 0 address + { scom_targets[myEX1], 0x10040000 ,0x7676767676767676}, + { scom_targets[myEX5], 0x10040002, 0x9191919191919191}, + { scom_targets[myEX5], 0x13040002, 0xabcdabcdabcdabcd}, // invalid unit 0 address { scom_targets[myEX1], 0x000F0166, 0xabcdabcdabcdabcd}, // invalid address range for target }; const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); @@ -668,15 +655,9 @@ public: //@VBU workaround - Disable Indirect SCOM test case o //Test case read/writes to valid addresses and is //potentially destructive on VBU - TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); - syspath.addLast(TARGETING::TYPE_SYS,0); - TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); - uint8_t vpo_mode = 0; - if( sys - && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode) - && (vpo_mode == 1) ) + if (TARGETING::is_vpo()) { - return; + return; } // Setup some targets to use @@ -709,7 +690,7 @@ public: (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0)) { // If both FSI and XSCOM are not enabled.. then ignore.. - TRACFCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS>> SKIPPING "); + TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS>> SKIPPING "); scom_targets[myProc0] = NULL; //remove from our list } @@ -754,10 +735,6 @@ public: { scom_targets[myMCS4], 0x0201184A, 0x3333333344444444}, { scom_targets[myMCS2], 0x0201184A, 0x5555555566666666}, { scom_targets[myMCS7], 0x0201184A, 0x7777777788888888}, -// { scom_targets[myMCS4], 0x02011C4A, 0x0101010101010101}, // invalid - // Unit for - // the - // target { scom_targets[myMCS4], 0x0601184A, 0x0101010101010101}, // invalid address range { scom_targets[myMCS4], 0x0200184A, 0x2323232323232323}, // Invalid address range for target }; @@ -842,6 +819,184 @@ public: } + void test_TranslateScom_MCS_DMI(void) +{ + + TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI Start" ); + errlHndl_t l_err = NULL; + + uint64_t fails = 0; + uint64_t total = 0; + + + + //@VBU workaround - Disable Indirect SCOM test case o + //Test case read/writes to valid addresses and is + //potentially destructive on VBU + if (TARGETING::is_vpo()) + { + return; + } + + // Setup some targets to use + enum { + myProc0, + myMCS1, + myMCS2, + myMCS7, + myMCS4, + NUM_TARGETS + }; + + TARGETING::Target* scom_targets[NUM_TARGETS]; + for( uint64_t x = 0; x < NUM_TARGETS; x++ ) + { + scom_targets[x] = NULL; + } + + // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes + TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL); + epath.addLast(TARGETING::TYPE_SYS,0); + epath.addLast(TARGETING::TYPE_NODE,0); + epath.addLast(TARGETING::TYPE_PROC,0); + + scom_targets[myProc0] = TARGETING::targetService().toTarget(epath); + + // Only check the Proc or Membuf targets to look at the SCOM attributes + if ((scom_targets[myProc0] != NULL) && + (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) && + (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0)) + { + // If both FSI and XSCOM are not enabled.. then ignore.. + TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS_DMI>> SKIPPING "); + scom_targets[myProc0] = NULL; //remove from our list + } + + + if (scom_targets[myProc0] != NULL) + { + // Add the MCS(1) to the path and create new target + epath.addLast(TARGETING::TYPE_MCS,1); + scom_targets[myMCS1] = TARGETING::targetService().toTarget(epath); + + // remote MCS(1) (off of sys-0/node-0/proc-0/MCS1) + epath.removeLast(); + + // add MCS4 target. + epath.addLast(TARGETING::TYPE_MCS,4); + scom_targets[myMCS4] = TARGETING::targetService().toTarget(epath); + + // remote MCS4 target (off of sys-0/node-0/proc-0/MCS4) + epath.removeLast(); + + // add MCS2 target. + epath.addLast(TARGETING::TYPE_MCS,2); + scom_targets[myMCS2] = TARGETING::targetService().toTarget(epath); + + // remove MCS2 target (off of sys-0/node-0/proc-0/MCS4) + epath.removeLast(); + + // add MCS7 target. + epath.addLast(TARGETING::TYPE_MCS,7); + scom_targets[myMCS7] = TARGETING::targetService().toTarget(epath); + } + + // scratch data to use + //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid + // corrupting the HW. + struct { + TARGETING::Target* target; + uint64_t addr; + uint64_t data; + } test_data[] = { + { scom_targets[myMCS1], 0x800EAC0002011A3F ,0x1111111122222222}, + { scom_targets[myMCS4], 0x800EAC0002011A3F, 0x3333333344444444}, + { scom_targets[myMCS2], 0x800EAC0002011A3F, 0x5555555566666666}, + { scom_targets[myMCS7], 0x800EAC0002011A3F, 0x7777777788888888}, + { scom_targets[myMCS4], 0x800EAC2002011A3F, 0x0101010101010101}, // invalid address range + { scom_targets[myMCS4], 0x800EAC4002011E3F, 0x2323232323232323}, // Invalid address range for target + }; + const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); + + size_t op_size = sizeof(uint32_t); + + // write all the test registers + for( uint64_t x = 0; x < NUM_ADDRS; x++ ) + { + //only run if the target exists + if(test_data[x].target == NULL) + { + continue; + } + + op_size = sizeof(uint64_t); + + total++; + l_err = deviceWrite( test_data[x].target, + &(test_data[x].data), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + if( l_err ) + { + if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2)) + { + TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS_DMI.. Expected Error log returned> x = %d", x ); + } + else + { + TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MCS_DMI> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_Translate_SCOM_mcs_DMI> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + } + + delete l_err; + } + } + + // allocate space for read data + uint64_t read_data[NUM_ADDRS]; + + memset(read_data, 0, sizeof read_data); + + // read all the test registers + for( uint64_t x = 0; x < NUM_ADDRS-2; x++ ) + { + //only run if the target exists + if(test_data[x].target == NULL) + { + continue; + } + + op_size = sizeof(uint64_t); + + total++; + l_err = deviceRead( test_data[x].target, + &(read_data[x]), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + + if( l_err ) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_TranslateScom_MCS_DMI> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + delete l_err; + } + else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF)) + // else if((read_data[x]) != (test_data[x].data)) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data); + TS_FAIL( "ScomTest::test_TranslateScom_MCS_DMI> ERROR : Data miss-match between read and expected data" ); + fails++; + } + + } + + TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_MCS_DMI> %d/%d fails", fails, total ); + + } void test_TranslateScom_MBA_MBS(void) { @@ -854,15 +1009,9 @@ public: //@VBU workaround - Disable Indirect SCOM test case o //Test case read/writes to valid addresses and is //potentially destructive on VBU - TARGETING::EntityPath syspath(TARGETING::EntityPath::PATH_PHYSICAL); - syspath.addLast(TARGETING::TYPE_SYS,0); - TARGETING::Target* sys = TARGETING::targetService().toTarget(syspath); - uint8_t vpo_mode = 0; - if( sys - && sys->tryGetAttr<TARGETING::ATTR_IS_SIMULATION>(vpo_mode) - && (vpo_mode == 1) ) + if (TARGETING::is_vpo()) { - return; + return; } // Setup some targets to use @@ -894,7 +1043,7 @@ public: (scom_targets[myMembuf0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0)) { // If both FSI and XSCOM are not enabled.. then ignore.. - TRACFCOMP(g_trac_scom, "TRANSLATE_SCOM_MBA_MBS>> SKIPPING "); + TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MBA_MBS>> SKIPPING "); scom_targets[myMembuf0] = NULL; //remove from our list } @@ -923,10 +1072,13 @@ public: uint64_t addr; uint64_t data; } test_data[] = { - { scom_targets[myMBA0], 0x03010655 ,0x1111111122222222}, - { scom_targets[myMBA1], 0x03010655, 0x3333333344444444}, - { scom_targets[myMBS], 0x02011417, 0x1231231231231231}, - { scom_targets[myMBA0], 0x03010E55, 0x0101010101010101}, // invalid passing in a non-0 unit address + { scom_targets[myMBA0], 0x03010655 ,0x111111111111DDDD}, + { scom_targets[myMBA1], 0x03010655, 0x333333334444EEEE}, + { scom_targets[myMBA0], 0x8000C0140301143F,0x1111111111111212}, + { scom_targets[myMBA1], 0x8000C0140301143F, 0x333333334444abcd}, + { scom_targets[myMBS], 0x02011417, 0x123123123123FFFF}, + { scom_targets[myMBA0], 0x8000C0140301183F,0x111111111111ccee}, // invalid non zero indirect address + { scom_targets[myMBA0], 0x03010E55, 0x010101010101CCCC}, // invalid passing in a non-0 unit address }; const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); @@ -950,18 +1102,18 @@ public: DEVICE_SCOM_ADDRESS(test_data[x].addr) ); if( l_err ) { - // checking the read of NUM_ADDRs - 1 because the last entry written above failed as expected. - if (x == (NUM_ADDRS-1)) - { - TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Errorlog Returned> x = %d", x ); - } - else - { - TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MBA_MBS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); - TS_FAIL( "ScomTest::test_Translate_SCOM_MBA_MBS> ERROR : Unexpected error log from write1" ); - fails++; - errlCommit(l_err,SCOM_COMP_ID); - } + // checking the read of NUM_ADDRs - 1 because the last entry written above failed as expected. + if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2)) + { + TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Errorlog Returned> x = %d", x ); + } + else + { + TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MBA_MBS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_Translate_SCOM_MBA_MBS> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + } delete l_err; } @@ -971,7 +1123,7 @@ public: uint64_t read_data[NUM_ADDRS]; // read all the test registers - for( uint64_t x = 0; x < NUM_ADDRS-1; x++ ) + for( uint64_t x = 0; x < NUM_ADDRS-2; x++ ) { memset(read_data, 0, sizeof read_data); @@ -997,6 +1149,16 @@ public: fails++; errlCommit(l_err,SCOM_COMP_ID); } + else if ((x == 2) || (x==3)) + { + if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF)) + + { + TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data); + TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Data miss-match between read and expected data" ); + fails++; + } + } else if((read_data[x]) != (test_data[x].data)) { TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MBA_MBS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data); @@ -1011,8 +1173,354 @@ public: } + void test_TranslateScom_ABUS(void) +{ + + TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_ABUS Start" ); + errlHndl_t l_err = NULL; + + uint64_t fails = 0; + uint64_t total = 0; + + //@VBU workaround - Disable Indirect SCOM test case o + //Test case read/writes to valid addresses and is + //potentially destructive on VBU + if (TARGETING::is_vpo()) + { + return; + } + + // Setup some targets to use + enum { + myProc0, + myABUS0, + myABUS1, + myABUS2, + NUM_TARGETS + }; + + TARGETING::Target* scom_targets[NUM_TARGETS]; + for( uint64_t x = 0; x < NUM_TARGETS; x++ ) + { + scom_targets[x] = NULL; + } + + // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes + TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL); + epath.addLast(TARGETING::TYPE_SYS,0); + epath.addLast(TARGETING::TYPE_NODE,0); + epath.addLast(TARGETING::TYPE_PROC,0); + + scom_targets[myProc0] = TARGETING::targetService().toTarget(epath); + + // Only check the Proc or Membuf targets to look at the SCOM attributes + if ((scom_targets[myProc0] != NULL) && + (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) && + (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0)) + { + // If both FSI and XSCOM are not enabled.. then ignore.. + TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_ABUS>> SKIPPING "); + scom_targets[myProc0] = NULL; //remove from our list + } + + + if (scom_targets[myProc0] != NULL) + { + // Add the ABUS 0 to the path and create new target + epath.addLast(TARGETING::TYPE_ABUS,0); + scom_targets[myABUS0] = TARGETING::targetService().toTarget(epath); + + // remote ABUS 0 (off of sys-0/node-0/proc-0/ABUS0) + epath.removeLast(); + + // add ABUS 1 target. + epath.addLast(TARGETING::TYPE_ABUS,1); + scom_targets[myABUS1] = TARGETING::targetService().toTarget(epath); + + // remote ABUS1 target (off of sys-0/node-0/proc-0/ABUS1) + epath.removeLast(); + // add ABUS2 target. + epath.addLast(TARGETING::TYPE_ABUS,2); + scom_targets[myABUS2] = TARGETING::targetService().toTarget(epath); + } + + // scratch data to use + //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid + // corrupting the HW. + struct { + TARGETING::Target* target; + uint64_t addr; + uint64_t data; + } test_data[] = { + + { scom_targets[myABUS0], 0x800C4C0008010C3F ,0x1111111101010101}, + { scom_targets[myABUS1], 0x800C4C0008010C3F, 0x3333333311111111}, + { scom_targets[myABUS2], 0x800C4C0008010C3F, 0x5555555521212121}, + { scom_targets[myABUS0], 0x800C4C0208010C3F, 0x0101010101010101}, // invalid address range - non zero + { scom_targets[myABUS2], 0x800C4C0004010C3F, 0x2323232323232323}, // Invalid address range for target + }; + const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); + + size_t op_size = sizeof(uint32_t); + + // write all the test registers + for( uint64_t x = 0; x < NUM_ADDRS; x++ ) + { + //only run if the target exists + if(test_data[x].target == NULL) + { + continue; + } + + op_size = sizeof(uint64_t); + + total++; + l_err = deviceWrite( test_data[x].target, + &(test_data[x].data), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + if( l_err ) + { + if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2)) + { + TRACDCOMP( g_trac_scom, "ScomTest::test_translate ABUS.. Expected Error log returned> x = %d", x ); + } + else + { + TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_ABUS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_Translate_SCOM_ABUS> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + } + + delete l_err; + } + } + + // allocate space for read data + uint64_t read_data[NUM_ADDRS]; + + memset(read_data, 0, sizeof read_data); + + // read all the test registers + for( uint64_t x = 0; x < NUM_ADDRS-2; x++ ) + { + //only run if the target exists + if(test_data[x].target == NULL) + { + continue; + } + + op_size = sizeof(uint64_t); + + total++; + l_err = deviceRead( test_data[x].target, + &(read_data[x]), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + + if( l_err ) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + delete l_err; + } + else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF)) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data); + TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Data miss-match between read and expected data" ); + fails++; + } + + } + + TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_ABUS> %d/%d fails", fails, total ); + + } + + + void test_TranslateScom_XBUS(void) +{ + + TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_XBUS Start" ); + errlHndl_t l_err = NULL; + + uint64_t fails = 0; + uint64_t total = 0; + + //@VBU workaround - Disable Indirect SCOM test case o + //Test case read/writes to valid addresses and is + //potentially destructive on VBU + if (TARGETING::is_vpo()) + { + return; + } + + + // Setup some targets to use + enum { + myProc0, + myXBUS0, + myXBUS1, + myXBUS2, + myXBUS3, + NUM_TARGETS + }; + + TARGETING::Target* scom_targets[NUM_TARGETS]; + for( uint64_t x = 0; x < NUM_TARGETS; x++ ) + { + scom_targets[x] = NULL; + } + + // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes + TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL); + epath.addLast(TARGETING::TYPE_SYS,0); + epath.addLast(TARGETING::TYPE_NODE,0); + epath.addLast(TARGETING::TYPE_PROC,0); + + scom_targets[myProc0] = TARGETING::targetService().toTarget(epath); + + // Only check the Proc or Membuf targets to look at the SCOM attributes + if ((scom_targets[myProc0] != NULL) && + (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) && + (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0)) + { + // If both FSI and XSCOM are not enabled.. then ignore.. + TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_XBUS>> SKIPPING "); + scom_targets[myProc0] = NULL; //remove from our list + } + + + if (scom_targets[myProc0] != NULL) + { + // Add the XBUS 0 to the path and create new target + epath.addLast(TARGETING::TYPE_XBUS,0); + scom_targets[myXBUS0] = TARGETING::targetService().toTarget(epath); + + // remove XBUS 0 (off of sys-0/node-0/proc-0/XBUS0) + epath.removeLast(); + + // add XBUS 1 target. + epath.addLast(TARGETING::TYPE_XBUS,1); + scom_targets[myXBUS1] = TARGETING::targetService().toTarget(epath); + + // remove XBUS1 target (off of sys-0/node-0/proc-0/XBUS1) + epath.removeLast(); + + // add XBUS2 target. + epath.addLast(TARGETING::TYPE_XBUS,2); + scom_targets[myXBUS2] = TARGETING::targetService().toTarget(epath); + + // remove XBUS2 target (off of sys-0/node-0/proc-0/XBUS2) + epath.removeLast(); + + // add XBUS3 target. + epath.addLast(TARGETING::TYPE_XBUS,3); + scom_targets[myXBUS3] = TARGETING::targetService().toTarget(epath); + + } + + // scratch data to use + //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid + // corrupting the HW. + struct { + TARGETING::Target* target; + uint64_t addr; + uint64_t data; + } test_data[] = { + + { scom_targets[myXBUS0], 0x800000200401103F ,0x1111111101010101}, + { scom_targets[myXBUS1], 0x800000200401103F, 0x3333333311111111}, + { scom_targets[myXBUS2], 0x800000200401103F, 0x555555552121aaaa}, + { scom_targets[myXBUS3], 0x800000200401103F, 0x555555552121bbbb}, + { scom_targets[myXBUS0], 0x8000002004011C3F, 0x0101010101010101}, // invalid address range - non zero + { scom_targets[myXBUS2], 0x800000200401003F, 0x2323232323232323}, // Invalid address range for target + }; + const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); + + size_t op_size = sizeof(uint32_t); + + // write all the test registers + for( uint64_t x = 0; x < NUM_ADDRS; x++ ) + { + //only run if the target exists + if(test_data[x].target == NULL) + { + continue; + } + + op_size = sizeof(uint64_t); + + total++; + l_err = deviceWrite( test_data[x].target, + &(test_data[x].data), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + if( l_err ) + { + if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2)) + { + TRACDCOMP( g_trac_scom, "ScomTest::test_translate XBUS.. Expected Error log returned> x = %d", x ); + } + else + { + TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_XBUS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_Translate_SCOM_XBUS> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + } + + delete l_err; + } + } + + // allocate space for read data + uint64_t read_data[NUM_ADDRS]; + + memset(read_data, 0, sizeof read_data); + + // read all the test registers + for( uint64_t x = 0; x < NUM_ADDRS-2; x++ ) + { + //only run if the target exists + if(test_data[x].target == NULL) + { + continue; + } + + op_size = sizeof(uint64_t); + + total++; + l_err = deviceRead( test_data[x].target, + &(read_data[x]), + op_size, + DEVICE_SCOM_ADDRESS(test_data[x].addr) ); + + if( l_err ) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_XBUS> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() ); + TS_FAIL( "ScomTest::test_TranslateScom_XBUS> ERROR : Unexpected error log from write1" ); + fails++; + errlCommit(l_err,SCOM_COMP_ID); + delete l_err; + } + else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF)) + { + TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_XBUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data); + TS_FAIL( "ScomTest::test_TranslateScom_XBUS> ERROR : Data miss-match between read and expected data" ); + fails++; + } + + } + + TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_XBUS> %d/%d fails", fails, total ); + + } //@todo - write tests to verify connection between XSCOM and FSISCOM //@todo - write error path testcase for FSI scom using bad address diff --git a/src/usr/targeting/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/xmltohb/simics_MURANO.system.xml index 56935a1cd..b086f800f 100644 --- a/src/usr/targeting/xmltohb/simics_MURANO.system.xml +++ b/src/usr/targeting/xmltohb/simics_MURANO.system.xml @@ -29,7 +29,7 @@ * MAXIMUM config has 4 Murano chips * each Murano has 6 ex chiplets (4,5,6,12,13,14) - * each Muran has 3 ABUS (0,1,2) and 1 XBUS (1) units + * each Murano has 3 ABUS (0,1,2) and 4 XBUS (0,1,2,3) units * each Murano has 4 MCS chiplets (4-7) * each MCS chiplet connects to 1 Centaur membuf chip * each Centaur membuf chip has 2 MBA chiplets @@ -532,6 +532,130 @@ </attribute> </targetInstance> +<!-- murano n0p0 ABUS units --> + +<targetInstance> + <id>sys0node0proc0abus0</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0abus1</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0abus2</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- murano n0p0 XBUS units --> + +<targetInstance> + <id>sys0node0proc0xbus0</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0xbus1</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0xbus2</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0xbus3</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + + <!-- Murano n0p1 processor chip --> <targetInstance> @@ -954,6 +1078,130 @@ </attribute> </targetInstance> +<!-- murano n0p1 ABUS units --> + +<targetInstance> + <id>sys0node0proc1abus0</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1abus1</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1abus2</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- murano n0p1 XBUS units --> + +<targetInstance> + <id>sys0node0proc1xbus0</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1xbus1</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1xbus2</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1xbus3</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + + <!-- Murano n0p2 processor chip --> <targetInstance> @@ -1377,6 +1625,130 @@ </attribute> </targetInstance> +<!-- murano n0p2 ABUS units --> + +<targetInstance> + <id>sys0node0proc2abus0</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2abus1</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2abus2</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- murano n0p2 XBUS units --> + +<targetInstance> + <id>sys0node0proc2xbus0</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2xbus1</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2xbus2</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2xbus3</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + + <!-- Murano n0p3 processor chip --> <targetInstance> @@ -1799,6 +2171,128 @@ </attribute> </targetInstance> +<!-- murano n0p3 ABUS units --> + +<targetInstance> + <id>sys0node0proc3abus0</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3abus1</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3abus2</id> + <type>unit-abus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- murano n0p3 XBUS units --> + +<targetInstance> + <id>sys0node0proc3xbus0</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3xbus1</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3xbus2</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3xbus3</id> + <type>unit-xbus-murano</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> <!-- Centaur n0p0 : start --> diff --git a/src/usr/targeting/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/xmltohb/simics_VENICE.system.xml index 12306583b..8d03cca1e 100644 --- a/src/usr/targeting/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/xmltohb/simics_VENICE.system.xml @@ -30,6 +30,7 @@ * MAXIMUM config has 8 Venice chips * each Venice has 12 ex chiplets (1-6,9-14) (@fixme : targets don't match this numbering RTC:38384) + * each VENICE has 3 ABUS (0,1,2) and 4 XBUS (0,1,2,3) units * each Venice has 8 MCS chiplets * each MCS chiplet connects to 1 Centaur membuf chip * each Centaur membuf chip has 2 MBA chiplets @@ -503,6 +504,131 @@ </attribute> </targetInstance> + +<!-- Venice n0p0 ABUS units --> + +<targetInstance> + <id>sys0node0proc0abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- Venice n0p0 XBUS units --> + +<targetInstance> + <id>sys0node0proc0xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc0xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-0/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + + <!-- Venice n0p1 processor chip --> <targetInstance> @@ -932,6 +1058,130 @@ </attribute> </targetInstance> +<!-- Venice n0p1 ABUS units --> + +<targetInstance> + <id>sys0node0proc1abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- Venice n0p1 XBUS units --> + +<targetInstance> + <id>sys0node0proc1xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc1xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-1/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + + <!-- Venice n0p2 processor chip --> <targetInstance> @@ -1362,8 +1612,133 @@ </attribute> </targetInstance> +<!-- Venice n0p2 ABUS units --> + +<targetInstance> + <id>sys0node0proc2abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- Venice n0p2 XBUS units --> + +<targetInstance> + <id>sys0node0proc2xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc2xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-2/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + + <!-- Venice n0p3 processor chip --> + <targetInstance> <id>sys0node0proc3</id> <type>chip-processor-venice</type> @@ -1377,7 +1752,7 @@ </default> </attribute> <attribute> - <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 --> + <id>XSCOM_CHIP_INFO</id> <!-- @fixme: Story 35529 --> <default> <field><id>nodeId</id><value>0</value></field> <field><id>chipId</id><value>0</value></field> @@ -1791,6 +2166,129 @@ </attribute> </targetInstance> +<!-- Venice n0p3 ABUS units --> + +<targetInstance> + <id>sys0node0proc3abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- Venice n0p3 XBUS units --> + +<targetInstance> + <id>sys0node0proc3xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc3xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-3/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + <!-- Venice n0p4 processor chip --> <targetInstance> @@ -2125,7 +2623,7 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-6</default> - </attribute> + </attribute> <attribute> <id>CHIP_UNIT</id> <default>6</default> @@ -2142,7 +2640,7 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/mcs-7</default> - </attribute> + </attribute> <attribute> <id>CHIP_UNIT</id> <default>7</default> @@ -2161,7 +2659,7 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/pervasive-0</default> - </attribute> + </attribute> </targetInstance> <!-- Vencie n0p4 powerbus unit --> @@ -2176,7 +2674,7 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/powerbus-0</default> - </attribute> + </attribute> </targetInstance> <!-- Vencie n0p4 PCI units --> @@ -2191,7 +2689,7 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/pci-0</default> - </attribute> + </attribute> </targetInstance> <targetInstance> @@ -2204,7 +2702,7 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/pci-1</default> - </attribute> + </attribute> </targetInstance> <targetInstance> @@ -2217,6 +2715,131 @@ <attribute> <id>AFFINITY_PATH</id> <default>affinity:sys-0/node-0/proc-4/pci-2</default> + </attribute> +</targetInstance> + + +<!-- Venice n0p4 ABUS units --> + +<targetInstance> + <id>sys0node0proc4abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-4/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc4abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-4/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc4abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-4/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + + +<!-- Venice n0p4 XBUS units --> + +<targetInstance> + <id>sys0node0proc4xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-4/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc4xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-4/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc4xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-4/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc4xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-4/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> </attribute> </targetInstance> @@ -2649,6 +3272,129 @@ </attribute> </targetInstance> +<!-- Venice n0p5 ABUS units --> + +<targetInstance> + <id>sys0node0proc5abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-5/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc5abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-5/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc5abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-5/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- Venice n0p5 XBUS units --> + +<targetInstance> + <id>sys0node0proc5xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-5/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc5xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-5/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc5xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-5/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc5xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-5/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + <!-- Venice n0p6 processor chip --> <targetInstance> @@ -3078,6 +3824,130 @@ </attribute> </targetInstance> +<!-- Venice n0p6 ABUS units --> + +<targetInstance> + <id>sys0node0proc6abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-6/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc6abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-6/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc6abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-6/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- Venice n0p6 XBUS units --> + +<targetInstance> + <id>sys0node0proc6xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-6/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc6xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-6/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc6xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-6/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc6xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-6/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + + <!-- Venice n0p7 processor chip --> <targetInstance> @@ -3465,7 +4335,7 @@ </attribute> </targetInstance> -<!-- Venice n0p7 PCI unit --> +<!-- Venice n0p7 PCI units --> <targetInstance> <id>sys0node0proc7pci0</id> @@ -3506,6 +4376,129 @@ </attribute> </targetInstance> +<!-- Venice n0p7 ABUS units --> + +<targetInstance> + <id>sys0node0proc7abus0</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/abus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-7/abus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc7abus1</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/abus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-7/abus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc7abus2</id> + <type>unit-abus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/abus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-7/abus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<!-- Venice n0p7 XBUS units --> + +<targetInstance> + <id>sys0node0proc7xbus0</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/xbus-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-7/xbus-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc7xbus1</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/xbus-1</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-7/xbus-1</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>1</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc7xbus2</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/xbus-2</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-7/xbus-2</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>2</default> + </attribute> +</targetInstance> + +<targetInstance> + <id>sys0node0proc7xbus3</id> + <type>unit-xbus-venice</type> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/xbus-3</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/proc-7/xbus-3</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>3</default> + </attribute> +</targetInstance> + <!-- Centaur n0p0 : start --> <targetInstance> diff --git a/src/usr/targeting/xmltohb/target_types.xml b/src/usr/targeting/xmltohb/target_types.xml index ed8dfe03b..46bd00ffd 100644 --- a/src/usr/targeting/xmltohb/target_types.xml +++ b/src/usr/targeting/xmltohb/target_types.xml @@ -484,6 +484,80 @@ </attribute> </targetType> +<targetType> + <id>unit-abus-power8</id> + <parent>unit</parent> + <attribute> + <id>TYPE</id> + <default>ABUS</default> + </attribute> + <attribute><id>CHIP_UNIT</id></attribute> +</targetType> + +<targetType> + <id>unit-abus-salerno</id> + <parent>unit-abus-power8</parent> + <attribute> + <id>MODEL</id> + <default>SALERNO</default> + </attribute> +</targetType> + +<targetType> + <id>unit-abus-venice</id> + <parent>unit-abus-power8</parent> + <attribute> + <id>MODEL</id> + <default>VENICE</default> + </attribute> +</targetType> + +<targetType> + <id>unit-abus-murano</id> + <parent>unit-abus-power8</parent> + <attribute> + <id>MODEL</id> + <default>MURANO</default> + </attribute> +</targetType> + +<targetType> + <id>unit-xbus-power8</id> + <parent>unit</parent> + <attribute> + <id>TYPE</id> + <default>XBUS</default> + </attribute> + <attribute><id>CHIP_UNIT</id></attribute> +</targetType> + +<targetType> + <id>unit-xbus-salerno</id> + <parent>unit-xbus-power8</parent> + <attribute> + <id>MODEL</id> + <default>SALERNO</default> + </attribute> +</targetType> + +<targetType> + <id>unit-xbus-venice</id> + <parent>unit-xbus-power8</parent> + <attribute> + <id>MODEL</id> + <default>VENICE</default> + </attribute> +</targetType> + +<targetType> + <id>unit-xbus-murano</id> + <parent>unit-xbus-power8</parent> + <attribute> + <id>MODEL</id> + <default>MURANO</default> + </attribute> +</targetType> + <!-- Hybrid targets --> <targetType> |
