1 files changed, 52 insertions, 2 deletions
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index c9382e9bb..9fce73d3d 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -1805,7 +1805,7 @@
                          on the completion of a write command to update its
                          internal memory.</description>
             <type>uint64_t</type>
-            <default>0x0A</default>
+            <default>0x0</default>
         </field>
     </complexType>
     <persistency>non-volatile</persistency>
@@ -1881,7 +1881,7 @@
                          on the completion of a write command to update its
                          internal memory.</description>
             <type>uint64_t</type>
-            <default>0x0A</default>
+            <default>0x0</default>
         </field>
     </complexType>
     <persistency>non-volatile</persistency>
@@ -16828,6 +16828,38 @@ Measured in GB</description>
     <readable/>
 </attribute>
 
+<attribute><!-- Deprecated : @todo-Remove with RTC:160417 -->
+    <id>PROC_PCIE_LANE_EQUALIZATION</id>
+    <description>PCIE Lane Equalization values for each PHB
+        Creator: MRW
+        Purpose: Holds settings which are loaded into the HW to optimize the
+            PCIE lane signal eye between the chips + PCIE endpoints
+        Data Format: 4 PHBs x 32 bytes of EQ data per PHB.  Each PHB has an EQ
+            value for each of its 16 lanes.  Each value is a uint16 formatted as
+            follows:
+                Bit 0:3   - up_rx_hint (bit 0 reserved)
+                Bit 4:7   - up_tx_preset
+                Bit 8:11  - dn_rx_hint (bit 0 reserved)
+                Bit 12:15 - dn_tx_preset
+    </description>
+    <simpleType>
+        <uint8_t><default>0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
+            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
+            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
+            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x0,
+            0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x77,
+            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
+            0x77,0x77,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
+            0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
+            0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
+            0x0,0x0</default>
+        </uint8_t>
+        <array>4,32</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+</attribute>
+
 <attribute>
     <id>PROC_PCIE_IS_SLOT</id>
     <description>Indicates whether PCIE lanes terminate at a pluggable slot
@@ -32273,4 +32305,22 @@ Measured in GB</description>
     <writeable/>
 </attribute>
 
+<attribute>
+    <id>MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id>
+    <description>
+        This is the fapi position of the port that failed to calculate
+        memory throttles given the passed in watt target and or utilization
+    </description>
+    <simpleType>
+    <uint64_t></uint64_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>