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-rw-r--r--src/usr/isteps/nvdimm/errlud_nvdimm.C3
-rw-r--r--src/usr/isteps/nvdimm/nvdimm.C59
-rw-r--r--src/usr/isteps/nvdimm/nvdimm.H23
-rw-r--r--src/usr/isteps/nvdimm/nvdimmErrorLog.C140
-rwxr-xr-xsrc/usr/isteps/nvdimm/nvdimmdd.H5
-rw-r--r--src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H9
-rw-r--r--src/usr/isteps/nvdimm/runtime/nvdimm_rt.C147
7 files changed, 273 insertions, 113 deletions
diff --git a/src/usr/isteps/nvdimm/errlud_nvdimm.C b/src/usr/isteps/nvdimm/errlud_nvdimm.C
index 9f916e040..f5c6c0eb9 100644
--- a/src/usr/isteps/nvdimm/errlud_nvdimm.C
+++ b/src/usr/isteps/nvdimm/errlud_nvdimm.C
@@ -178,6 +178,8 @@ UdNvdimmOPParms::UdNvdimmOPParms( const nvdimm_reg_t &i_RegInfo )
// 1 byte : CSAVE_INFO
// 1 byte : CSAVE_FAIL_INFO0
// 1 byte : CSAVE_FAIL_INFO1
+ // 1 byte : CSAVE_TIMEOUT_INFO0
+ // 1 byte : CSAVE_TIMEOUT_INFO1
// 1 byte : ERROR_THRESHOLD_STATUS
// 1 byte : NVDIMM_READY
// 1 byte : NVDIMM_CMD_STATUS0
@@ -192,6 +194,7 @@ UdNvdimmOPParms::UdNvdimmOPParms( const nvdimm_reg_t &i_RegInfo )
// 1 byte : RESTORE_TIMEOUT1
// 1 byte : ARM_STATUS
// 1 byte : SET_EVENT_NOTIFICATION_STATUS
+ // 1 byte : ENCRYPTION_CONFIG_STATUS
char * l_pBuf = reinterpret_cast<char *>( reallocUsrBuf(sizeof(i_RegInfo)));
memcpy(l_pBuf, &i_RegInfo, sizeof(i_RegInfo));
diff --git a/src/usr/isteps/nvdimm/nvdimm.C b/src/usr/isteps/nvdimm/nvdimm.C
index 359f72230..06f666c5c 100644
--- a/src/usr/isteps/nvdimm/nvdimm.C
+++ b/src/usr/isteps/nvdimm/nvdimm.C
@@ -131,6 +131,10 @@ static constexpr size_t MAX_TPM_SIZE = 34;
static constexpr uint8_t KEY_TERMINATE_BYTE = 0x00;
static constexpr uint8_t KEY_ABORT_BYTE = 0xFF;
+// NVDIMM CSAVE_FAIL_INFO1 Bit mask
+// Currently only bits 1:6 need to be checked during init
+static constexpr uint8_t CSAVE_FAIL_BITS_MASK = 0x7E;
+
#ifndef __HOSTBOOT_RUNTIME
// Warning thresholds
static constexpr uint8_t THRESHOLD_ES_LIFETIME = 0x07; // 7%
@@ -552,8 +556,7 @@ errlHndl_t nvdimmReady(Target *i_nvdimm)
// If nvdimm is not ready for access by now, this is
// a failing indication on the NV controller
- l_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
@@ -1245,17 +1248,8 @@ errlHndl_t nvdimmRestore(TargetHandleList& i_nvdimmList, uint8_t &i_mpipl)
ERRORLOG::ErrlEntry::NO_SW_CALLOUT);
break;
}
- }
- if (l_err)
- {
- TRACFCOMP(g_trac_nvdimm, "restore encountered an error");
- break;
- }
-
- // Exit self-refresh
- for (const auto & l_nvdimm : i_nvdimmList)
- {
+ // Exit self-refresh
TargetHandleList l_mcaList;
getParentAffinityTargets(l_mcaList, l_nvdimm, CLASS_UNIT, TYPE_MCA);
assert(l_mcaList.size(), "nvdimmRestore() failed to find parent MCA.");
@@ -1344,12 +1338,10 @@ errlHndl_t nvdimmEraseCheck(Target *i_nvdimm)
{
// For both Erase timeout and Erase fail
// Callout nvdimm on high, gard and deconfig
- l_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_HIGH,
- HWAS::DECONFIG,
- HWAS::GARD_Fatal);
-
+ l_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_HIGH,
+ HWAS::DECONFIG,
+ HWAS::GARD_Fatal);
// Collect register data for FFDC Traces
nvdimmTraceRegs ( i_nvdimm, l_RegInfo );
@@ -1721,8 +1713,7 @@ errlHndl_t nvdimm_restore(TargetHandleList &i_nvdimmList)
// Invalid restore could be due to dram not in self-refresh
// or controller issue. Data should not be trusted at this point
- l_err->addPartCallout( l_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ l_err->addHwCallout( l_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
@@ -1901,6 +1892,8 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
errlHndl_t l_err = nullptr;
bool l_continue = true;
uint8_t l_data = 0;
+ uint8_t l_failinfo0 = 0;
+ uint8_t l_failinfo1 = 0;
nvdimm_reg_t l_RegInfo;
uint32_t l_poll = 0;
@@ -2015,8 +2008,7 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
{
// May have to move the error handling to the caller
// as different op could have different error severity
- l_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
@@ -2027,13 +2019,27 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
}
}
- // Check CSAVE_ERROR Register
- l_err = nvdimmReadReg( i_nvdimm, CSAVE_FAIL_INFO0, l_data );
+ // Check CSAVE FAIL INFO registers for fail errors
+ l_err = nvdimmReadReg( i_nvdimm, CSAVE_FAIL_INFO0, l_failinfo0 );
if (l_err)
{
break;
}
- else if (l_data != ZERO)
+ l_err = nvdimmReadReg ( i_nvdimm, CSAVE_FAIL_INFO1, l_failinfo1 );
+ if (l_err)
+ {
+ break;
+ }
+ // Apply mask for relevant 1:6 bits to failinfo1
+ l_failinfo1 &= CSAVE_FAIL_BITS_MASK;
+
+ // Check CSAVE_STATUS Register
+ l_err = nvdimmReadReg( i_nvdimm, CSAVE_STATUS, l_data );
+ if (l_err)
+ {
+ break;
+ }
+ else if ((l_data == SAVE_ERROR) && ((l_failinfo0 != ZERO) || (l_failinfo1 != ZERO)))
{
/*@
*@errortype
@@ -2066,8 +2072,7 @@ errlHndl_t nvdimm_init(Target *i_nvdimm)
if ( l_RegInfo.CSave_Info != VALID_IMAGE )
{
// Callout and gard dimm if image is not valid
- l_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
diff --git a/src/usr/isteps/nvdimm/nvdimm.H b/src/usr/isteps/nvdimm/nvdimm.H
index af77866ff..a99f1180a 100644
--- a/src/usr/isteps/nvdimm/nvdimm.H
+++ b/src/usr/isteps/nvdimm/nvdimm.H
@@ -354,6 +354,8 @@ enum i2c_out_values : uint8_t
ES_POLICY_ERROR = 0x02,
ARM_ERROR = 0X02,
RSTR_ERROR = 0x02,
+ SAVE_ERROR = 0x02,
+ ARM_CLEAR = 0x20,
};
// Timeout-related enum
@@ -467,7 +469,28 @@ enum event_n : uint8_t
{
PERSISTENCY_NOTIFICATION = 0x01,
SET_EVENT_NOTIFICATION_ERROR = 0x02,
+ WARNING_THRESHOLD_NOTIFICATION = 0x02,
PERSISTENCY_ENABLED = 0x04,
+ WARNING_THRESHOLD_ENABLED = 0x08,
+ ENABLE_NOTIFICATIONS = 0x03,
+ NOTIFICATIONS_ENABLED = 0x0C,
+};
+
+// MBACALFIR register addresses
+enum mbacal_addresses : uint32_t
+{
+ MBACALFIR_AND_MASK_REG = 0x07010904,
+ MBACALFIR_OR_MASK_REG = 0x07010905,
+ MBACALFIR_ACTION0_REG = 0x07010906,
+ MBACALFIR_ACTION1_REG = 0x07010907,
+};
+
+// MBACALFIR bit masks for event n
+enum mbacal_bitmask_values : uint64_t
+{
+ MBACALFIR_EVENTN_AND_BIT = 0xff7fffffffffffff,
+ MBACALFIR_EVENTN_OR_BIT = 0x0080000000000000,
+ MBACALFIR_UNMASK_BIT = 0xff7fffffffffffff,
};
/**
diff --git a/src/usr/isteps/nvdimm/nvdimmErrorLog.C b/src/usr/isteps/nvdimm/nvdimmErrorLog.C
index ccd1ad801..87866f2e1 100644
--- a/src/usr/isteps/nvdimm/nvdimmErrorLog.C
+++ b/src/usr/isteps/nvdimm/nvdimmErrorLog.C
@@ -32,7 +32,6 @@
#include <targeting/common/util.H>
#include <targeting/common/utilFilter.H>
#include <fapi2.H>
-#include <lib/shared/nimbus_defaults.H>
#include <isteps/nvdimm/nvdimmreasoncodes.H>
#include <isteps/nvdimm/nvdimm.H>
#include "errlud_nvdimm.H"
@@ -254,6 +253,14 @@ void nvdimmTraceRegs(Target *i_nvdimm, nvdimm_reg_t& o_RegInfo)
errlCommit( l_err, NVDIMM_COMP_ID );
}
o_RegInfo.Set_Event_Notification_Status = l_data;
+
+ // Read NVDIMM Encryption Configuration and Status Register for Security Errors
+ l_err = nvdimmReadReg(i_nvdimm, ENCRYPTION_CONFIG_STATUS, l_data);
+ if(l_err)
+ {
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ }
+ o_RegInfo.Encryption_Config_Status = l_data;
}
/**
@@ -294,16 +301,16 @@ bool nvdimmCalloutDimm(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
}
else
{
// Callout, deconfig and gard the dimm
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW,
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
}
@@ -332,17 +339,16 @@ bool nvdimmCalloutDimm(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
-
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
}
else
{
// Callout, deconfig and gard the dimm
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW,
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
}
@@ -371,10 +377,11 @@ bool nvdimmCalloutDimm(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
// Set ATTR_NV_STATUS_FLAG to partially working as data may still persist
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
- // Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ // Callout dimm and gard
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_Fatal);
}
else
{
@@ -385,12 +392,11 @@ bool nvdimmCalloutDimm(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
errlCommit( l_err, NVDIMM_COMP_ID );
}
- // Callout, deconfig and gard the dimm
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ // Callout the dimm but do not deconfig or gard
+ o_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_LOW,
HWAS::NO_DECONFIG,
- HWAS::GARD_Fatal);
+ HWAS::GARD_NULL);
}
break;
@@ -400,9 +406,10 @@ bool nvdimmCalloutDimm(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
case HEALTH_POST_ARM:
{
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
// Set ATTR_NV_STATUS_FLAG to partially working as data may persist despite errors
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
@@ -461,16 +468,16 @@ bool nvdimmBPMCableCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
}
else
{
// Callout dimm, deconfig and gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW,
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
}
@@ -507,16 +514,16 @@ bool nvdimmBPMCableCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
}
else
{
// Callout dimm, deconfig and gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW,
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
}
@@ -553,9 +560,10 @@ bool nvdimmBPMCableCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
}
else
{
@@ -566,9 +574,8 @@ bool nvdimmBPMCableCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
errlCommit( l_err, NVDIMM_COMP_ID );
}
// Callout dimm, deconfig and gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW,
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_HIGH,
HWAS::DECONFIG,
HWAS::GARD_Fatal);
}
@@ -586,9 +593,10 @@ bool nvdimmBPMCableCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
o_err->addPartCallout( i_nvdimm,
HWAS::BPM_CABLE_PART_TYPE,
HWAS::SRCI_PRIORITY_HIGH);
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
// Set ATTR_NV_STATUS_FLAG to partially working as data may still persist
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
@@ -631,9 +639,10 @@ bool nvdimmBPMCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
HWAS::SRCI_PRIORITY_HIGH);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
// Set ATTR_NV_STATUS_FLAG to partially working as data may still persist
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
@@ -650,9 +659,10 @@ bool nvdimmBPMCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
HWAS::SRCI_PRIORITY_HIGH);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
// Set ATTR_NV_STATUS_FLAG to partially working as data may still persist
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
@@ -680,9 +690,10 @@ bool nvdimmBPMCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
HWAS::SRCI_PRIORITY_HIGH);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
// Check arm status and set dimm status accordingly
if(!l_continue)
@@ -712,9 +723,10 @@ bool nvdimmBPMCallout(Target *i_nvdimm, uint8_t i_step, errlHndl_t& o_err)
HWAS::SRCI_PRIORITY_HIGH);
// Callout dimm but do not deconfig or gard
- o_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ o_err->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
// Set ATTR_NV_STATUS_FLAG to partially working as data may still persist
nvdimmSetStatusFlag(i_nvdimm, NSTD_ERR_VAL_SR);
@@ -1052,9 +1064,8 @@ errlHndl_t nvdimmHealthStatusCheck(Target *i_nvdimm, uint8_t i_step, bool& o_con
if(l_arm_timeout)
{
- // Callout, deconfig and gard the dimm
- l_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ // Callout and gard the dimm
+ l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_LOW,
HWAS::NO_DECONFIG,
HWAS::GARD_Fatal);
@@ -1288,9 +1299,10 @@ errlHndl_t nvdimmHealthStatusCheck(Target *i_nvdimm, uint8_t i_step, bool& o_con
ERRORLOG::ErrlEntry::NO_SW_CALLOUT );
o_continue = true;
// Callout dimm but no deconfig and gard
- l_err_t->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
+ l_err_t->addHwCallout( i_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
}
}
diff --git a/src/usr/isteps/nvdimm/nvdimmdd.H b/src/usr/isteps/nvdimm/nvdimmdd.H
index 37fa4a188..c48e03f07 100755
--- a/src/usr/isteps/nvdimm/nvdimmdd.H
+++ b/src/usr/isteps/nvdimm/nvdimmdd.H
@@ -122,6 +122,7 @@ struct nvdimm_reg_t
uint8_t Arm_Timeout0;
uint8_t Arm_Timeout1;
uint8_t Set_Event_Notification_Status;
+ uint8_t Encryption_Config_Status;
/**
* @brief Construct a default nvdimm_reg_t
@@ -151,8 +152,8 @@ struct nvdimm_reg_t
Arm_Status(0),
Arm_Timeout0(0),
Arm_Timeout1(0),
- Set_Event_Notification_Status(0)
-
+ Set_Event_Notification_Status(0),
+ Encryption_Config_Status(0)
{
}
diff --git a/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H b/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H
index 1e951a96b..ca3d6dbb6 100644
--- a/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H
+++ b/src/usr/isteps/nvdimm/plugins/errludP_nvdimm.H
@@ -198,7 +198,7 @@ public:
char* l_databuf = static_cast<char*>(i_pBuffer);
i_parser.PrintHeading("NVDIMM I2C Register Traces");
- //***** Memorr Layout *****
+ //***** Memory Layout *****
// 1 byte : MODULE_HEALTH
// 1 byte : MODULE_HEALTH_STATUS0
// 1 byte : MODULE_HEALTH_STATUS1
@@ -224,6 +224,7 @@ public:
// 1 byte : ARM_TIMEOUT0
// 1 byte : ARM_TIMEOUT1
// 1 byte : SET_EVENT_NOTIFICATION_STATUS
+ // 1 byte : ENCRYPTION_CONFIG_STATUS
//
i_parser.PrintNumber("Module Health Register: ","%.2lX",TO_UINT8(l_databuf));
@@ -244,6 +245,10 @@ public:
++l_databuf;
i_parser.PrintNumber("CSave Timeout Info1 Register: ","%.2lX",TO_UINT8(l_databuf));
++l_databuf;
+ i_parser.PrintNumber("CSave Timeout Info0 Register: ","%.2lX",TO_UINT8(l_databuf));
+ ++l_databuf;
+ i_parser.PrintNumber("CSave Timeout Info1 Register: ","%.2lX",TO_UINT8(l_databuf));
+ ++l_databuf;
i_parser.PrintNumber("Error Threshold Status Register: ","%.2lX",TO_UINT8(l_databuf));
++l_databuf;
i_parser.PrintNumber("NVDIMM Ready Register: ","%.2lX",TO_UINT8(l_databuf));
@@ -276,6 +281,8 @@ public:
++l_databuf;
i_parser.PrintNumber("Set Event Notification Status Register: ","%.2lX",TO_UINT8(l_databuf));
++l_databuf;
+ i_parser.PrintNumber("NVDIMM Encryption Configuration and Status Register: ","%.2lX",TO_UINT8(l_databuf));
+ ++l_databuf;
}
// Disabled
diff --git a/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C b/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C
index 42a7b49d3..d615aa546 100644
--- a/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C
+++ b/src/usr/isteps/nvdimm/runtime/nvdimm_rt.C
@@ -41,7 +41,6 @@
#include <usr/runtime/rt_targeting.H>
#include <runtime/interface.h>
#include <arch/ppc.H>
-#include <lib/shared/nimbus_defaults.H>
#include <isteps/nvdimm/nvdimmreasoncodes.H>
#include "../errlud_nvdimm.H"
#include "../nvdimmErrorLog.H"
@@ -142,10 +141,9 @@ errlHndl_t nvdimmCheckArmSuccess(Target *i_nvdimm, bool i_arm_timeout)
// Failure to arm could mean internal NV controller error or
// even error on the battery pack. NVDIMM will lose persistency
// if failed to arm trigger
- l_err->addPartCallout( i_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ l_err->addHwCallout( i_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
- HWAS::DECONFIG,
+ HWAS::NO_DECONFIG,
HWAS::GARD_Fatal);
}
@@ -162,6 +160,9 @@ bool nvdimmArm(TargetHandleList &i_nvdimmTargetList)
bool l_arm_timeout = false;
uint8_t l_data;
auto l_RegInfo = nvdimm_reg_t();
+ uint64_t l_writeData;
+ uint32_t l_writeAddress;
+ size_t l_writeSize = sizeof(l_writeData);
TRACFCOMP(g_trac_nvdimm, ENTER_MRK"nvdimmArm() %d",
i_nvdimmTargetList.size());
@@ -169,6 +170,27 @@ bool nvdimmArm(TargetHandleList &i_nvdimmTargetList)
errlHndl_t l_err = nullptr;
errlHndl_t l_err_t = nullptr;
+ // Mask MBACALFIR EventN to separate ARM handling
+ for (TargetHandleList::iterator it = i_nvdimmTargetList.begin();
+ it != i_nvdimmTargetList.end();)
+ {
+ TargetHandleList l_mcaList;
+ getParentAffinityTargets(l_mcaList, *it, CLASS_UNIT, TYPE_MCA);
+ assert(l_mcaList.size(), "nvdimmArm() failed to find parent MCA.");
+
+ l_writeAddress = MBACALFIR_OR_MASK_REG;
+ l_writeData = MBACALFIR_EVENTN_OR_BIT;
+ l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize,
+ DEVICE_SCOM_ADDRESS(l_writeAddress));
+ if(l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed",
+ l_writeAddress);
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ }
+ it++;
+ }
+
for (auto const l_nvdimm : i_nvdimmTargetList)
{
l_arm_timeout = false;
@@ -202,9 +224,8 @@ bool nvdimmArm(TargetHandleList &i_nvdimmTargetList)
l_err->setSev(ERRORLOG::ERRL_SEV_PREDICTIVE);
l_err->collectTrace(NVDIMM_COMP_NAME);
- // Callout nvdimm on high, gard and deconfig
- l_err->addPartCallout( l_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
+ // Callout the nvdimm on high and gard
+ l_err->addHwCallout( l_nvdimm,
HWAS::SRCI_PRIORITY_HIGH,
HWAS::NO_DECONFIG,
HWAS::GARD_Fatal);
@@ -213,6 +234,15 @@ bool nvdimmArm(TargetHandleList &i_nvdimmTargetList)
break;
}
+ // Clear ARM status register
+ l_err = nvdimmWriteReg(l_nvdimm, NVDIMM_MGT_CMD0, ARM_CLEAR);
+ if (l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, ERR_MRK"nvdimmArm() nvdimm[%X] - error clearing ARM status register",
+ get_huid(l_nvdimm));
+ break;
+ }
+
l_err = NVDIMM::nvdimmChangeArmState(l_nvdimm, ARM_TRIGGER);
// If we run into any error here we will just
// commit the error log and move on. Let the
@@ -365,24 +395,26 @@ bool nvdimmArm(TargetHandleList &i_nvdimmTargetList)
errlCommit(l_err, NVDIMM_COMP_ID);
}
- // Enable event notification
- l_err = nvdimmWriteReg(l_nvdimm, SET_EVENT_NOTIFICATION_CMD, PERSISTENCY_NOTIFICATION);
+ // Enable Persistency and Warning Threshold notifications
+ l_err = nvdimmWriteReg(l_nvdimm, SET_EVENT_NOTIFICATION_CMD, ENABLE_NOTIFICATIONS);
if (l_err)
{
- TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X] error initiating erase!!",
+ TRACFCOMP(g_trac_nvdimm, ERR_MRK"NDVIMM HUID[%X] setting persistency notification",
TARGETING::get_huid(l_nvdimm));
- errlCommit(l_err, NVDIMM_COMP_ID);
+ break;
}
// Check notification status and errors
l_err = nvdimmReadReg(l_nvdimm, SET_EVENT_NOTIFICATION_STATUS, l_data);
if (l_err)
{
- errlCommit( l_err, NVDIMM_COMP_ID );
+ break;
}
- else if (((l_data & SET_EVENT_NOTIFICATION_ERROR) == SET_EVENT_NOTIFICATION_ERROR) || ((l_data & PERSISTENCY_ENABLED) != PERSISTENCY_ENABLED))
+ else if (((l_data & SET_EVENT_NOTIFICATION_ERROR) == SET_EVENT_NOTIFICATION_ERROR)
+ || ((l_data & NOTIFICATIONS_ENABLED) != NOTIFICATIONS_ENABLED))
{
- TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed to set event notification", get_huid(l_nvdimm));
+ TRACFCOMP(g_trac_nvdimm, "nvdimmArm() nvdimm[%X] failed to set event notification",
+ get_huid(l_nvdimm));
// Set NVDIMM Status flag to partial working, as error detected but data might persist
nvdimmSetStatusFlag(l_nvdimm, NSTD_ERR_VAL_SR);
@@ -407,11 +439,11 @@ bool nvdimmArm(TargetHandleList &i_nvdimmTargetList)
l_err->collectTrace( NVDIMM_COMP_NAME );
- // Callout, deconfig and gard the dimm
- l_err->addPartCallout( l_nvdimm,
- HWAS::NV_CONTROLLER_PART_TYPE,
- HWAS::SRCI_PRIORITY_LOW);
-
+ // Callout the dimm
+ l_err->addHwCallout( l_nvdimm,
+ HWAS::SRCI_PRIORITY_LOW,
+ HWAS::NO_DECONFIG,
+ HWAS::GARD_NULL);
// Read relevant regs for trace data
nvdimmTraceRegs(l_nvdimm, l_RegInfo);
@@ -438,6 +470,83 @@ bool nvdimmArm(TargetHandleList &i_nvdimmTargetList)
}
+ // Check for uncommited i2c fail error logs
+ if (l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, "nvdimmArm() failed an i2c read/write");
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ nvdimmDisarm(i_nvdimmTargetList);
+ return false;
+ }
+
+ // Unmask MBACALFIR EventN and set to recoverable
+ for (TargetHandleList::iterator it = i_nvdimmTargetList.begin();
+ it != i_nvdimmTargetList.end();)
+ {
+ TargetHandleList l_mcaList;
+ getParentAffinityTargets(l_mcaList, *it, CLASS_UNIT, TYPE_MCA);
+ assert(l_mcaList.size(), "nvdimmArm() failed to find parent MCA.");
+
+ // Set MBACALFIR_ACTION0 to recoverable
+ l_writeAddress = MBACALFIR_ACTION0_REG;
+ l_writeData = 0;
+ l_err = deviceRead(l_mcaList[0], &l_writeData, l_writeSize,
+ DEVICE_SCOM_ADDRESS(l_writeAddress));
+ if(l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed",
+ l_writeAddress);
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ }
+
+
+ l_writeData &= MBACALFIR_EVENTN_AND_BIT;
+ l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize,
+ DEVICE_SCOM_ADDRESS(l_writeAddress));
+ if(l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed",
+ l_writeAddress);
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ }
+
+ // Set MBACALFIR_ACTION1 to recoverable
+ l_writeAddress = MBACALFIR_ACTION1_REG;
+ l_writeData = 0;
+ l_err = deviceRead(l_mcaList[0], &l_writeData, l_writeSize,
+ DEVICE_SCOM_ADDRESS(l_writeAddress));
+ if(l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed",
+ l_writeAddress);
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ }
+
+ l_writeData |= MBACALFIR_EVENTN_OR_BIT;
+ l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize,
+ DEVICE_SCOM_ADDRESS(l_writeAddress));
+ if(l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed",
+ l_writeAddress);
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ }
+
+ // Unmask MBACALFIR[8]
+ l_writeAddress = MBACALFIR_AND_MASK_REG;
+ l_writeData = MBACALFIR_UNMASK_BIT;
+ l_err = deviceWrite(l_mcaList[0], &l_writeData, l_writeSize,
+ DEVICE_SCOM_ADDRESS(l_writeAddress));
+ if(l_err)
+ {
+ TRACFCOMP(g_trac_nvdimm, "SCOM to address 0x%08x failed",
+ l_writeAddress);
+ errlCommit( l_err, NVDIMM_COMP_ID );
+ }
+
+ it++;
+ }
+
TRACFCOMP(g_trac_nvdimm, EXIT_MRK"nvdimmArm() returning %d",
o_arm_successful);
return o_arm_successful;
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