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-rwxr-xr-xsrc/usr/hwpf/hwp/initfiles/sample.initfile100
-rw-r--r--src/usr/hwpf/test/hwpftest.H38
2 files changed, 76 insertions, 62 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/sample.initfile b/src/usr/hwpf/hwp/initfiles/sample.initfile
index 17ee552a5..e4a537878 100755
--- a/src/usr/hwpf/hwp/initfiles/sample.initfile
+++ b/src/usr/hwpf/hwp/initfiles/sample.initfile
@@ -33,7 +33,7 @@ define def_not_equal_test = (ATTR_SCRATCH_UINT64_1 != ATTR_SCRATCH_UINT64_2);
#--******************************************************************************
scom 0x0000000013010002 {
scom_data ;
- 0x0000000000000181 ;
+ 0xAABBC00000000000 ;
}
#--******************************************************************************
@@ -42,7 +42,7 @@ scom 0x0000000013010002 {
scom 0x0000000013030007 {
scom_data, expr ;
- 0x0000000000000182, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ;
+ 0x00000CDE00000000, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ;
}
#--******************************************************************************
@@ -75,77 +75,83 @@ scom 0x000000000006800c {
#--******************************************************************************
#-- Basic SCOM with bits
#--******************************************************************************
+#@todo
+#@VBU workaround - Disable sample addresses
+#All SCR reg addresses below are only supported from chip release 052 and beyond.
+#Release 051, which is used by current VBU model, contain different addresses for
+#these registers.
+#Disable them for now, needs to re-enable them when VBU upgrade to use chip release 052
-scom 0x0000000013013283 {
- bits , scom_data ;
- 0:11 , 0b001111001001 ;
- 12 , 0b1 ;
- 13 , 0b1 ;
- 14:59, 0b0000001100000110010000000000010000010010000000 ;
-}
+#scom 0x0000000013013283 {
+# bits , scom_data ;
+# 0:11 , 0b001111001001 ;
+# 12 , 0b1 ;
+# 13 , 0b1 ;
+# 14:59, 0b0000001100000110010000000000010000010010000000 ;
+#}
#--******************************************************************************
#-- Complext SCOM with Bit Support, define, and attributes
#--******************************************************************************
-scom 0x0000000013013284 {
- bits , scom_data, expr ;
- 0:11 , 0b001111001001, any ;
- 12 , 0b1, def_equal_test ;
- 12 , 0b0, def_not_equal_test ;
- 13 , 0b1, ATTR_SCRATCH_UINT8_1 > ATTR_SCRATCH_UINT8_2 ;
- 14:59, 0b0000001100000110010000000000010000010010000000, ATTR_SCRATCH_UINT64_1 == ATTR_SCRATCH_UINT64_2 ;
-}
+#scom 0x0000000013013284 {
+# bits , scom_data, expr ;
+# 0:11 , 0b001111001001, any ;
+# 12 , 0b1, def_equal_test ;
+# 12 , 0b0, def_not_equal_test ;
+# 13 , 0b1, ATTR_SCRATCH_UINT8_1 > ATTR_SCRATCH_UINT8_2 ;
+# 14:59, 0b0000001100000110010000000000010000010010000000, ATTR_SCRATCH_UINT64_1 == ATTR_SCRATCH_UINT64_2 ;
+#}
#--******************************************************************************
#-- Complex SCOM with Bit Support, and logical operators
#--******************************************************************************
-scom 0x0000000013013285 {
- bits , scom_data, expr ;
- 12 , 0b1, def_equal_test && def_not_equal_test ;
- 12 , 0b0, def_equal_test || def_not_equal_test ;
- 14 , 0b1, ATTR_SCRATCH_UINT32_1 < ATTR_SCRATCH_UINT32_2 ;
- 15 , 0b1, ATTR_SCRATCH_UINT32_1 > ATTR_SCRATCH_UINT32_2 ;
- 16 , 0b1, ATTR_SCRATCH_UINT32_1 >= ATTR_SCRATCH_UINT32_2 ;
- 17 , 0b1, ATTR_SCRATCH_UINT32_1 <= ATTR_SCRATCH_UINT32_2 ;
- 18 , 0b1, ATTR_SCRATCH_UINT32_1 == ATTR_SCRATCH_UINT32_2 ;
- 19 , 0b1, ATTR_SCRATCH_UINT32_1 != ATTR_SCRATCH_UINT32_2 ;
- 20 , 0b1, (ATTR_SCRATCH_UINT32_1 + ATTR_SCRATCH_UINT32_2) == 4 ;
- 21:59, 0b000000110000011001000000000001000001001, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ;
-}
+#scom 0x0000000013013285 {
+# bits , scom_data, expr ;
+# 12 , 0b1, def_equal_test && def_not_equal_test ;
+# 12 , 0b0, def_equal_test || def_not_equal_test ;
+# 14 , 0b1, ATTR_SCRATCH_UINT32_1 < ATTR_SCRATCH_UINT32_2 ;
+# 15 , 0b1, ATTR_SCRATCH_UINT32_1 > ATTR_SCRATCH_UINT32_2 ;
+# 16 , 0b1, ATTR_SCRATCH_UINT32_1 >= ATTR_SCRATCH_UINT32_2 ;
+# 17 , 0b1, ATTR_SCRATCH_UINT32_1 <= ATTR_SCRATCH_UINT32_2 ;
+# 18 , 0b1, ATTR_SCRATCH_UINT32_1 == ATTR_SCRATCH_UINT32_2 ;
+# 19 , 0b1, ATTR_SCRATCH_UINT32_1 != ATTR_SCRATCH_UINT32_2 ;
+# 20 , 0b1, (ATTR_SCRATCH_UINT32_1 + ATTR_SCRATCH_UINT32_2) == 4 ;
+# 21:59, 0b000000110000011001000000000001000001001, ATTR_SCRATCH_UINT8_1 == ATTR_SCRATCH_UINT8_2 ;
+#}
#--******************************************************************************
#-- SCOM with 'ec' column - Use scratch for now since all attributes work
#--******************************************************************************
-scom 0x0000000013013286 {
- scom_data, ATTR_SCRATCH_UINT32_1 ;
- 0x0000000000000192, 1 ;
-}
+#scom 0x0000000013013286 {
+# scom_data, ATTR_SCRATCH_UINT32_1 ;
+# 0x0000000000000192, 1 ;
+#}
#--******************************************************************************
#-- Basic SCOM with an array
#--******************************************************************************
-scom 0x0000000013013287 {
- scom_data, expr ;
- 0x0000000000000182, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1 ;
-}
+#scom 0x0000000013013287 {
+# scom_data, expr ;
+# 0x0000000000000182, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1 ;
+#}
#--******************************************************************************
#-- SCOM with 'ec' & expr column - Use scratch for now since all attributes work
#--******************************************************************************
-scom 0x0000000013013288 {
- scom_data, ATTR_SCRATCH_UINT32_1 expr;
- 0x0000000000000192, 3, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1;
-}
+#scom 0x0000000013013288 {
+# scom_data, ATTR_SCRATCH_UINT32_1 expr;
+# 0x0000000000000192, 3, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1;
+#}
#--******************************************************************************
#-- Complex SCOM with Bit Support, logical operators and 'ec' column
#--******************************************************************************
-scom 0x0000000013013289 {
- bits , scom_data ATTR_SCRATCH_UINT32_1 expr;
- 23 , 0b1, any, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1;
- 23 , 0b0, 1, any;
-}
+#scom 0x0000000013013289 {
+# bits , scom_data ATTR_SCRATCH_UINT32_1 expr;
+# 23 , 0b1, any, ATTR_SCRATCH_UINT8_ARRAY_1[2] == ATTR_SCRATCH_UINT8_1;
+# 23 , 0b0, 1, any;
+#}
diff --git a/src/usr/hwpf/test/hwpftest.H b/src/usr/hwpf/test/hwpftest.H
index ef497c0cc..42fdbccbf 100644
--- a/src/usr/hwpf/test/hwpftest.H
+++ b/src/usr/hwpf/test/hwpftest.H
@@ -175,21 +175,29 @@ public:
{0x000000000006002c, 0, 0x0000000000000183},
{0x000000000006800b, 0, 0},
{0x000000000006800c, 0, 0x8000000000000000 >> 0x17},
- {0x0000000013010002, 0, 0x0000000000000181},
- {0x0000000013013283, 0, 0x3c90000000000000 |
- 0x8000000000000000 >> 0x0c |
- 0x8000000000000000 >> 0x0d |
- 0x0306400412000000 >> 0x0e},
- {0x0000000013013284, 0, 0x3c90000000000000},
- {0x0000000013013285, 0, 0x8000000000000000 >> 0x0f |
- 0x8000000000000000 >> 0x10 |
- 0x8000000000000000 >> 0x13 |
- 0x0306400412000000 >> 0x15 },
- {0x0000000013013286, 0, 0},
- {0x0000000013013287, 0, 0x0000000000000182},
- {0x0000000013013288, 0, 0x0000000000000192},
- {0x0000000013013289, 0, 0x8000000000000000 >> 0x17},
- {0x0000000013030007, 0, 0x0000000000000182}
+ {0x0000000013010002, 0, 0xAABBC00000000000},
+ {0x0000000013030007, 0, 0x00000CDE00000000},
+ /*
+ * @todo
+ * @VBU workaround
+ * All SCR reg addresses below are only supported from chip release 052 and beyond.
+ * Release 051, which is used by current VBU model, contain different addresses for
+ * these registers.
+ * Disable them for now, needs to re-enable them when VBU upgrade to use chip release 052
+ {0x0000000013013283, 0, 0x3c90000000000000 |
+ 0x8000000000000000 >> 0x0c |
+ 0x8000000000000000 >> 0x0d |
+ 0x0306400412000000 >> 0x0e},
+ {0x0000000013013284, 0, 0x3c90000000000000},
+ {0x0000000013013285, 0, 0x8000000000000000 >> 0x0f |
+ 0x8000000000000000 >> 0x10 |
+ 0x8000000000000000 >> 0x13 |
+ 0x0306400412000000 >> 0x15 },
+ {0x0000000013013286, 0, 0},
+ {0x0000000013013287, 0, 0x0000000000000182},
+ {0x0000000013013288, 0, 0x0000000000000192},
+ {0x0000000013013289, 0, 0x8000000000000000 >> 0x17}
+ */
};
fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
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