diff options
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/mba_def.initfile | 61 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/mbs_def.initfile | 56 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile | 386 |
3 files changed, 293 insertions, 210 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index f69cc6400..9985b7014 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,12 @@ -#-- $Id: mba_def.initfile,v 1.44 2013/05/06 15:28:35 yctschan Exp $ +#-- $Id: mba_def.initfile,v 1.46 2013/07/17 18:23:53 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.46|tschang | 7/17/13|updated refresh interval and refresh check interval calculations +#-- 1.45|tschang | 6/04/13|using ATTR_EFF_DRAM_RRD, etc timing parms for settings +#-- setting RD ODT according to Menlo's equation #-- 1.44|tschang | 5/06/13|added 2n_mode to timing parms equations #-- 1.43|tschang | 5/01/13|def_refresh_interval optimized to avoid divide by 0 condition #-- 1.42|tschang | 5/01/13|cfg_min_domain_reduction disabled as requested by performance team @@ -1983,10 +1986,7 @@ scom 0x0301040B { 48:51 , 0b1001 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 2400); # WWDM_dly 12 D 52:55 , 0b0100 + def_margin2 , 1 , any; # RROP_dly is 4 for all cfgs 13 D 56:59 , 0b0100 + def_margin2 , 1 , any; # WWOP_dly is 4 for all cfgs 14 D - 60:63 , 0b0100 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly4 == 1); # TMR0Q_Trrd 15 - 60:63 , 0b0101 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly5 == 1); # TMR0Q_Trrd 15 - 60:63 , 0b0110 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly6 == 1); # TMR0Q_Trrd 15 - 60:63 , 0b0111 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly7 == 1); # TMR0Q_Trrd 15 + 60:63 , ATTR_EFF_DRAM_TRRD , 1 , any; # TMR0Q_Trrd } # MBA_TMR1Q mba01 timer settings @@ -2018,6 +2018,7 @@ scom 0x0301040C { 7:13 , 0b0110001 , 1 , (def_mba_tmr1q_cfg_twap49 == 1); # cfg_twap 17 7:13 , 0b0110011 , 1 , (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap 17 7:13 , 0b0110101 , 1 , (def_mba_tmr1q_cfg_twap53 == 1); # cfg_twap 17 +# 14:19 , ATTR_EFF_DRAM_TFAW, 1 , any; # cfg_tfaw # uncomment when Anuwat has added in fix 14:19 , 0b010100 , 1 , (def_mba_tmr1q_cfg_tfaw_dly20 == 1); # cfg_tfaw 18 14:19 , 0b010110 , 1 , (def_mba_tmr1q_cfg_tfaw_dly22 == 1); # cfg_tfaw 18 14:19 , 0b010111 , 1 , (def_mba_tmr1q_cfg_tfaw_dly23 == 1); # cfg_tfaw 18 @@ -2056,6 +2057,11 @@ define def_WL_AL0 = (ATTR_EFF_DRAM_CWL - 7); define def_WL_AL_MINUS1 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7); define def_WL_AL_MINUS2 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 2 - 7); +define def_RDODT_start_udimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 1); +define def_RDODT_start_rdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 2); +define def_RDODT_start_lrdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 6); +define def_RDODT_duration = (5); + # MBA_DSM0Q mba01 data state machine settings #< B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x0870466094038800 #> B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x08704660A4838800 @@ -2063,18 +2069,14 @@ define def_WL_AL_MINUS2 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 2 - 7); scom 0x0301040A { bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b000000 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly0 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000001 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly1 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000010 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly2 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000011 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly3 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000100 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly4 == 1); # CFG_RODT_start_dly 21 - 6:11 , 0b000101 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly5 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b000110 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly6 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b000111 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly7 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b001000 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly8 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b001001 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly9 == 1); # CFG_RODT_end_dly 22 - 12:17 , 0b000000 , 1 , any; # CFG_WODT_start_dly is 1 for all cfgs 23 D - 18:23 , 0b000101 , 1 , any; # CFG_WODT_end_dly is 6 for all cfgs 24 D + 0:5 , def_RDODT_start_udimm , 1 , (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_start_dly 21 + 0:5 , def_RDODT_start_rdimm , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_start_dly 21 + 0:5 , def_RDODT_start_lrdimm , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_start_dly 21 + 6:11 , def_RDODT_start_udimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_end_dly 22 + 6:11 , def_RDODT_start_rdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_end_dly 22 + 6:11 , def_RDODT_start_lrdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_end_dly 22 + 12:17 , 0b000000 , 1 , any; # CFG_WODT_start_dly is 0 for all cfgs 23 D + 18:23 , 0b000101 , 1 , any; # CFG_WODT_end_dly is 5 for all cfgs 24 D 24:29 , 0b011000 , 1 , any; # wrdone_dly is 24 for all cfgs 25 D 30:35 , def_WL_AL0 + 1 , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly 30:35 , def_WL_AL0 , 1 , (((ATTR_EFF_DIMM_TYPE == 0) || (ATTR_EFF_DIMM_TYPE == 2)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly @@ -2100,31 +2102,34 @@ scom 0x0301040A { 36:41 , 0b011011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly 27 36:41 , 0b011100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly 27 36:41 , 0b011101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly 27 - 43:48 , 0b000101 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b000110 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b000111 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b001000 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY8 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b001001 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY9 == 1); # CFG_RODT_BC4_END_DLY 28 - 49:54 , 0b000100 , 1 , any; # CFG_WODT_BC4_END_DLY is 4 for all cfgs 29 D + 43:48 , def_RDODT_start_udimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_BC4_END_DLY 28 + 43:48 , def_RDODT_start_rdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_BC4_END_DLY 28 + 43:48 , def_RDODT_start_lrdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_BC4_END_DLY 28 + 49:54 , 0b000011 , 1 , any; # CFG_WODT_BC4_END_DLY is 3 for all cfgs 29 D } ## Refresh Interval Calculuation -## refresh_interval = ((ATTR_EFF_DRAM_TRFI/(def_num_ranks/2))/8); -define def_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); -define def_refresh_interval = ((2*ATTR_EFF_DRAM_TRFI)/(8*def_num_ranks)); +## refresh_interval = ((ATTR_EFF_DRAM_TRFI/(def_num_ranks))/8); +#define def_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); +define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); +define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); +define def_mba01_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba01_num_ranks)); +define def_mba23_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba23_num_ranks)); +define def_refresh_check_interval = (ATTR_EFF_DRAM_TRFI/8); # same for both mba01 and mba23 # MBAREF0Q mba01 refresh settings # scom 0x03010432 { bits , scom_data , ATTR_FUNCTIONAL, expr; 4:7 , 0b0111 , 1 , any; # MBAREF0Q_refresh priority threshold is 0x7 for all cfgs 30 ?# refresh interval = tREFI(7.8) / # ranks per port / DRAM clk(ns) / 0.008 - 8:18 , def_refresh_interval, 1 , any; # MBAREF0Q_refresh intveral set to 176 decimal 31 ? !!FIXME# reset check interval = tREFI(7.8) / DRAM clk(ns) / 0.008 + 8:18 , def_mba01_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 0; # see calculation above + 8:18 , def_mba23_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 1; # see calculation above 19:29 , 0b00011000010, 1 , any; # MBAREF0Q_refresh reset interval set to 194 decimal 32 ? !!FIXME 30:39 , ATTR_EFF_DRAM_TRFC, 1 , any; # MBAREF0Q_cfg_trfc 33 40:49 , 0b0000100000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly32 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0000110000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly48 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0001000000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly64 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 - 50:60 , 0b01100001100, 1 , any; # MBAREF0Q_refresh check intveral set to 780 decimal 35 + 50:60 , def_refresh_check_interval, 1 , any; # MBAREF0Q_refresh check intveral set to 780 decimal 35 } # MBAPC0Q power control settings reg 1 diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index 73e583ae7..240245a94 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,9 +1,14 @@ -#-- $Id: mbs_def.initfile,v 1.31 2013/04/17 14:41:41 yctschan Exp $ +#-- $Id: mbs_def.initfile,v 1.36 2013/07/08 14:37:16 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- -#-- 1.30 |tschang |04/17/13| hash mode updated for type 1a/1b/5b +#-- 1.36 |tschang |07/03/13| L4.ATTR_FUNCTIONAL for cache enable for some bits I missed +#-- 1.35 |tschang |07/02/13| L4.ATTR_FUNCTIONAL for cache enable +#-- 1.34 |tschang |06/11/13| removed mask out bit 8 - internal parity error - HW244827 and HW251643 +#-- 1.33 |tschang |06/06/13| mask out bit 8 - internal parity error - HW244827 and HW251643 +#-- 1.32 |tschang |04/24/13| fixed 1d cfg type +#-- 1.31 |tschang |04/17/13| hash mode updated for type 1a/1b/5b #-- 1.30 |tschang |04/16/13| updated file for new IBM_TYPE defnitions #-- 1.29 |tschang |04/08/13| added MBI cfg register initialization for Irving #-- 1.26 |tschang |03/13/13| changed cache interleave mode to have ATTR_MSS_CACHE_ENABLE as a condition @@ -78,6 +83,8 @@ define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT define MBA0 = TGT1; define MBA1 = TGT2; +define L4 = TGT3; + # MBA0.ATTR_CHIP_UNIT_POS - that should equal 0 # MBA1.ATTR_CHIP_UNIT_POS should equal @@ -106,17 +113,19 @@ define def_mba01_1b_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) ## 1C 1 and 2 sockets not supported #define def_mba01_1c_1socket = 0; #define def_mba01_1c_2socket = 0; -define def_mba01_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1c_cdimm = ((((MBA0.ATTR_CHIP_UNIT_POS == 1 ) && (MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 +#define def_mba01_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +#define def_mba01_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +define def_mba01_1c_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba01_1d_1socket; +define def_mba01_1c_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba01_1d_2socket; +define def_mba01_1c_cdimm = (((MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 ) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 )) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute #define def_mba01_1d_1socket = 0; #define def_mba01_1d_2socket = 0; #define def_mba01_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba01_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_1d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); +define def_mba01_1d_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); +define def_mba01_1d_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba01_2a_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); @@ -202,8 +211,10 @@ define def_mba23_1b_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) ## 1C 1 and 2 sockets not supported #define def_mba23_1c_1socket = 0; #define def_mba23_1c_2socket = 0; -define def_mba23_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +#define def_mba23_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +#define def_mba23_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +define def_mba23_1c_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba23_1d_1socket; +define def_mba23_1c_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba23_1d_2socket; define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute @@ -211,8 +222,8 @@ define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) & #define def_mba23_1d_2socket = 0; #define def_mba23_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba23_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -#efine def_mba23_1d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -#efine def_mba23_1d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); +define def_mba23_1d_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); +define def_mba23_1d_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba23_2a_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); @@ -394,6 +405,16 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb #define def_01ATTR_EFF_MBA_POS = 0; # -MW not needed? #define def_23ATTR_EFF_MBA_POS = 1; # -MW not needed? +#--****************************************************************************** +#-- MBS FIR MASK Register +#--****************************************************************************** +# scom 0x02011403 { +# bits , scom_data ; +# 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 +# +# } + + # YCT added for Irving #--****************************************************************************** #-- MBI Configuration Register @@ -470,12 +491,11 @@ scom 0x02011411 { # MBCCFGQ MBC Configuration Register scom 0x0201140F { bits, scom_data , expr; - 0 , 0b0 , (ATTR_MSS_CACHE_ENABLE == 0); # MBCCFGQ_cache_enable - 0 , 0b1 , (ATTR_MSS_CACHE_ENABLE != 0); # MBCCFGQ_cache_enable -# 1 , 0b0 , any ; # -MW match dials + 0 , 0b0 , (L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0); # MBCCFGQ_cache_enable + 0 , 0b1 , (L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0); # MBCCFGQ_cache_enable 1 , 0b0 , any ; # MBCCFGQ_cfg_dyn_whap_en - 2 , 0b0 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 0) || (ATTR_MSS_CACHE_ENABLE != 1)); # MBCCFGQ_cleaner_enable - 2 , 0b1 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (ATTR_MSS_CACHE_ENABLE == 1)); # MBCCFGQ_cleaner_enable + 2 , 0b0 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBCCFGQ_cleaner_enable + 2 , 0b1 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBCCFGQ_cleaner_enable 3 , 0b0 , any ; # MBCCFGQ_cache_only_enable 4 , 0b0 , any ; # MBCCFGQ_lru_dmap_en 5 , 0b0 , any ; # MBCCFGQ_lru_random_en @@ -610,8 +630,8 @@ scom 0x0201140B { # 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode - 12 , 0b0 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0) || (ATTR_MSS_CACHE_ENABLE != 1)); # MBAXCR01Q_MBA01_Interleave_Mode - 12 , 0b1 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1) && (ATTR_MSS_CACHE_ENABLE == 1)); # MBAXCR01Q_MBA01_Interleave_Mod + 12 , 0b0 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA01_Interleave_Mode + 12 , 0b1 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA01_Interleave_Mod } diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile index 0c3d2ed1f..f51f1f319 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.dmi.scom.initfile,v 1.17 2013/04/18 19:13:44 jgrell Exp $ +#-- $Id: p8.dmi.scom.initfile,v 1.22 2013/07/30 20:45:32 jgrell Exp $ #################################################################### @@ -7,14 +7,18 @@ ## Based on SETUP_ID_MODE DMI_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb ## -## Created on Mon Apr 15 15:03:50 CDT 2013, by jgrell +## Created on Tue Jul 30 10:22:10 CDT 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- + ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback + ## -- mbs13071200| mbs |07-12-13| Updates for HW239870 and HW258990 + ## -- | | | Disable recal adjustment for allv1 (DFE bug) ## -- jgr13041800| jgr |04-18-13| Added rx_max_ber_check_count setting to 0x03 + ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel @@ -66,8 +70,8 @@ include edi.io.define define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); -define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 7)); -define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 6)); +define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); +define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); @@ -93,19 +97,19 @@ scom 0x800AF06002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP scom 0x800B786002011A3F { bits, scom_data, expr; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id3; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id0; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id3; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id0; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id3; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; @@ -121,20 +125,20 @@ scom 0x800B786002011A3F { rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id3; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id0; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id0; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id3; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id3; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id3; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; @@ -154,19 +158,61 @@ scom 0x800B786002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP scom 0x800B806002011A3F { bits, scom_data, expr; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id3; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id3; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id3; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id3; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id3; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id3; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id3; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id3; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id3; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; @@ -187,10 +233,19 @@ scom 0x800B806002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG scom 0x800A186002011A3F { bits, scom_data, expr; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id3; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id0; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id1; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id2; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id3; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id0; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id1; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id2; +} + +#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP +scom 0x800B406002011A3F { + bits, scom_data, expr; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG @@ -458,25 +513,6 @@ scom 0x8009C06002011A3F { rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2; } -#RX3.RXCTL.RX_CTL_REGS.RX_MODE1_PP -scom 0x800B086002011A3F { - bits, scom_data, expr; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id3; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id0; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id0; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id3; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id0; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id0; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2; -} - #RX3.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x8008186002011A3F { bits, scom_data, expr; @@ -531,34 +567,14 @@ scom 0x800AB86002011A3F { rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id3; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id3; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id0; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id1; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id2; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; @@ -603,108 +619,141 @@ scom 0x800AB86002011A3F { rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; } +#RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP +scom 0x800B906002011A3F { + bits, scom_data, expr; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; +} + #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP scom 0x800B986002011A3F { bits, scom_data, expr; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP scom 0x800BA06002011A3F { bits, scom_data, expr; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B606002011A3F { bits, scom_data, expr; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B686002011A3F { bits, scom_data, expr; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; @@ -719,19 +768,19 @@ scom 0x800B686002011A3F { rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } @@ -752,19 +801,19 @@ scom 0x800B706002011A3F { rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; @@ -888,10 +937,10 @@ scom 0x8008986002011A3F { rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1; rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id2; rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2; - rx_sls_timeout_sel, 0b001, def_bus_id3; - rx_sls_timeout_sel, 0b001, def_bus_id0; - rx_sls_timeout_sel, 0b001, def_bus_id1; - rx_sls_timeout_sel, 0b001, def_bus_id2; + rx_sls_timeout_sel, 0b110, def_bus_id3; + rx_sls_timeout_sel, 0b110, def_bus_id0; + rx_sls_timeout_sel, 0b110, def_bus_id1; + rx_sls_timeout_sel, 0b110, def_bus_id2; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; @@ -933,19 +982,19 @@ scom 0x8009586002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG scom 0x800A306002011A3F { bits, scom_data, expr; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id3; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id0; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id3; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id3; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id0; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id3; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; @@ -1188,6 +1237,15 @@ scom 0x800CC46002011A3F { tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2; } +#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP +scom 0x800EAC6002011A3F { + bits, scom_data, expr; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; +} + #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C946002011A3F { bits, scom_data, expr; |
