diff options
Diffstat (limited to 'src/usr/hwpf/hwp/activate_powerbus/proc_build_smp')
9 files changed, 733 insertions, 326 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C index 23682da3e..7ca990bd8 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_adu_utils.C,v 1.6 2012/08/21 05:16:27 jmcgill Exp $ +// $Id: proc_adu_utils.C,v 1.7 2013/09/26 17:56:54 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_adu_utils.C,v $ //------------------------------------------------------------------------------ // *| @@ -300,7 +300,6 @@ fapi::ReturnCode proc_adu_utils_send_fbc_op( { fapi::ReturnCode rc; uint32_t rc_ecmd = 0; - ecmdDataBufferBase pmisc_data(64), pmisc_mask(64); ecmdDataBufferBase ctl_data(64); ecmdDataBufferBase cmd_data(64); uint8_t struct_data_to_insert; @@ -339,43 +338,6 @@ fapi::ReturnCode proc_adu_utils_send_fbc_op( break; } - - // build ADU pMisc Mode register content - if (i_use_hp) - { - FAPI_DBG("proc_adu_utils_send_fbc_op: Writing ADU pMisc Mode register"); - // switch AB bit - rc_ecmd |= pmisc_data.writeBit( - ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT, - i_adu_hp_ctl.do_switch_ab); - rc_ecmd |= pmisc_mask.setBit( - ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT); - // switch CD bit - rc_ecmd |= pmisc_data.writeBit( - ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT, - i_adu_hp_ctl.do_switch_cd); - rc_ecmd |= pmisc_mask.setBit( - ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT); - rc.setEcmdError(rc_ecmd); - - if (!rc.ok()) - { - FAPI_ERR("proc_adu_utils_send_fbc_op: Error 0x%x setting up ADU pMisc Mode register data buffer", - rc_ecmd); - break; - } - // write ADU pMisc Mode register content - rc = fapiPutScomUnderMask(i_target, - ADU_PMISC_MODE_0x0202000B, - pmisc_data, - pmisc_mask); - if (!rc.ok()) - { - FAPI_ERR("proc_adu_utils_send_fbc_op: fapiPutUnderMask error (ADU_PMISC_MODE_0x0202000B)"); - break; - } - } - // build ADU Control register content FAPI_DBG("proc_adu_utils_send_fbc_op: Writing ADU Control register"); // ttype field diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H index c376a729f..171f68352 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_adu_utils.H,v 1.5 2013/04/15 18:31:39 jmcgill Exp $ +// $Id: proc_adu_utils.H,v 1.6 2013/09/26 17:57:02 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_adu_utils.H,v $ //------------------------------------------------------------------------------ // *| @@ -281,8 +281,6 @@ struct proc_adu_utils_fbc_op_hp_ctl { uint32_t pre_init_delay; // cycle delay to pause after programmed // command (clean cresp) before issuing // post-init command - bool do_switch_ab; // enable AB switch? - bool do_switch_cd; // enable CD switch? }; // ADU status structure @@ -377,10 +375,6 @@ const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_LO_START_BIT = 9; const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_LO_END_BIT = 16; const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_OVERWRITE_BIT = 17; -// ADU pMISC Mode register field/bit definitions -const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT = 30; -const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT = 31; - // ADU Data register field/bit definitions const uint32_t ADU_DATA_START_BIT = 0; const uint32_t ADU_DATA_END_BIT = 63; diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C index f796a5341..5d98e2d88 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.C,v 1.9 2013/07/30 20:51:09 jmcgill Exp $ +// $Id: proc_build_smp.C,v 1.10 2013/09/26 18:14:05 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $ //------------------------------------------------------------------------------ // *| @@ -589,18 +589,15 @@ fapi::ReturnCode proc_build_smp_process_chip( //------------------------------------------------------------------------------ // function: set chip master status (node/system) for PB operations -// parameters: i_first_chip_in_sys => first chip processed in system? -// i_first_chip_in_node => first chip processed in node? -// i_op => procedure operation phase/mode -// io_smp_chip => structure encapsulating single chip in -// SMP topology -// io_smp => structure encapsulating SMP -// o_master_chip_sys => indication that this chip is current -// system master +// parameters: i_first_chip_in_node => first chip processed in node? +// i_op => procedure operation phase/mode +// io_smp_chip => structure encapsulating single chip in +// SMP topology +// io_smp => structure encapsulating SMP // returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges // are valid, // RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master -// is detected based on chip state and input paramters, +// error is detected based on chip state and input paramters, // RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation // is specified // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not @@ -608,17 +605,14 @@ fapi::ReturnCode proc_build_smp_process_chip( // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_master_config( - const bool i_first_chip_in_sys, const bool i_first_chip_in_node, const proc_build_smp_operation i_op, proc_build_smp_chip& io_smp_chip, - proc_build_smp_system& io_smp, - bool & o_master_chip_sys) + proc_build_smp_system& io_smp) { fapi::ReturnCode rc; ecmdDataBufferBase data(64); bool error = false; - o_master_chip_sys = false; // mark function entry FAPI_DBG("proc_build_smp_set_master_config: Start"); @@ -641,48 +635,27 @@ fapi::ReturnCode proc_build_smp_set_master_config( io_smp_chip.master_chip_node_curr = (data.isBitSet(PB_HP_MODE_CHG_RATE_GP_MASTER_BIT)); - // check/set expectation for NEXT state based on current HW programming + // check/set expectation for CURR/NEXT states based on HW state // as well as input parameters // HBI if (i_op == SMP_ACTIVATE_PHASE1) { - // check input state + // each chip should match the flush state of the fabric logic if (!io_smp_chip.master_chip_sys_curr || io_smp_chip.master_chip_node_curr) { error = true; + break; } - // set next state based on input parameters - io_smp_chip.master_chip_sys_next = i_first_chip_in_sys; - io_smp_chip.master_chip_node_next = i_first_chip_in_node; - // set current system master pointer - if (!io_smp.master_chip_curr_set && - io_smp_chip.master_chip_sys_curr) - { - o_master_chip_sys = true; - } + // set next state + io_smp_chip.master_chip_node_next = i_first_chip_in_node; } // FSP else if (i_op == SMP_ACTIVATE_PHASE2) { - // if designated as new master, should already be one - if (!io_smp_chip.master_chip_sys_curr && - i_first_chip_in_sys) - { - error = true; - } - - // set next state based on input parameters - io_smp_chip.master_chip_sys_next = i_first_chip_in_sys; + // set next state io_smp_chip.master_chip_node_next = io_smp_chip.master_chip_node_curr; - - // set current system master pointer - if (!io_smp.master_chip_curr_set && - io_smp_chip.master_chip_sys_curr) - { - o_master_chip_sys = true; - } } // unsupported operation else @@ -695,22 +668,61 @@ fapi::ReturnCode proc_build_smp_set_master_config( break; } - // error for supported operation - if (error) + // mark system master for launching fabric reconfiguration operations + // also track which slave fabrics will be quiesced + if (io_smp_chip.chip->master_chip_sys_next) { - FAPI_ERR("proc_build_smp_set_master_config: Node/system master designation error"); - const uint8_t& OP = i_op; - const bool& MASTER_CHIP_SYS_CURR = io_smp_chip.master_chip_sys_curr; - const bool& MASTER_CHIP_NODE_CURR = io_smp_chip.master_chip_node_curr; - const bool& FIRST_CHIP_IN_SYS = i_first_chip_in_sys; - const bool& FIRST_CHIP_IN_NODE = i_first_chip_in_node; - FAPI_SET_HWP_ERROR( - rc, - RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR); - break; + // this chip will not be quiesced, to enable switch AB + io_smp_chip.issue_quiesce_next = false; + + // in both activation scenarios, we expect that: + // - only a single chip is designated to be the new master + // - the newly designated master is currently configured + // as a master within the scope of its current enclosing fabric + if (!io_smp.master_chip_curr_set && + io_smp_chip.master_chip_sys_curr) + { + io_smp.master_chip_curr_set = true; + io_smp.master_chip_curr_node_id = io_smp_chip.node_id; + io_smp.master_chip_curr_chip_id = io_smp_chip.chip_id; + } + else + { + error = true; + break; + } + } + else + { + // this chip will not be the new master, but is one now + // use it to quisece all chips in its fabric + if (io_smp_chip.master_chip_sys_curr) + { + io_smp_chip.issue_quiesce_next = true; + } + else + { + io_smp_chip.issue_quiesce_next = false; + } } + } while(0); + // error for supported operation + if (rc.ok() && error) + { + FAPI_ERR("proc_build_smp_set_master_config: Node/system master designation error"); + const uint8_t& OP = i_op; + const bool& MASTER_CHIP_SYS_CURR = io_smp_chip.master_chip_sys_curr; + const bool& MASTER_CHIP_NODE_CURR = io_smp_chip.master_chip_node_curr; + const bool& MASTER_CHIP_SYS_NEXT = io_smp_chip.chip->master_chip_sys_next; + const bool& MASTER_CHIP_NODE_NEXT = io_smp_chip.master_chip_node_next; + const bool& SYS_RECONFIG_MASTER_SET = io_smp.master_chip_curr_set; + FAPI_SET_HWP_ERROR( + rc, + RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR); + } + // mark function exit FAPI_DBG("proc_build_smp_set_master_config: End"); return rc; @@ -722,7 +734,6 @@ fapi::ReturnCode proc_build_smp_set_master_config( // on its fabric node/chip ID // parameters: io_smp_chip => structure encapsulating single chip in // SMP topology -// i_first_chip_in_sys => first chip processed in system? // i_op => procedure operation phase/mode // io_smp => structure encapsulating full SMP // returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges @@ -740,7 +751,6 @@ fapi::ReturnCode proc_build_smp_set_master_config( //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_insert_chip( proc_build_smp_chip& io_smp_chip, - const bool i_first_chip_in_sys, const proc_build_smp_operation i_op, proc_build_smp_system& io_smp) { @@ -751,8 +761,6 @@ fapi::ReturnCode proc_build_smp_insert_chip( proc_fab_smp_chip_id chip_id = io_smp_chip.chip_id; // first chip found in node? bool first_chip_in_node = false; - // chip is current SMP master? - bool master_chip_sys_curr; // mark function entry FAPI_DBG("proc_build_smp_insert_chip: Start"); @@ -809,12 +817,10 @@ fapi::ReturnCode proc_build_smp_insert_chip( // determine node/system master status FAPI_DBG("proc_build_smp_insert_chip: Determining node/system master status"); - rc = proc_build_smp_set_master_config(i_first_chip_in_sys, - first_chip_in_node, + rc = proc_build_smp_set_master_config(first_chip_in_node, i_op, io_smp_chip, - io_smp, - master_chip_sys_curr); + io_smp); if (!rc.ok()) { FAPI_ERR("proc_build_smp_insert_chip: Error from proc_fab_smp_set_master_config"); @@ -823,13 +829,6 @@ fapi::ReturnCode proc_build_smp_insert_chip( // insert chip into SMP io_smp.nodes[node_id].chips[chip_id] = io_smp_chip; - // save pointer to current system master chip? - if (master_chip_sys_curr) - { - io_smp.master_chip_curr_set = true; - io_smp.master_chip_curr_node_id = node_id; - io_smp.master_chip_curr_chip_id = chip_id; - } } while(0); @@ -856,8 +855,10 @@ fapi::ReturnCode proc_build_smp_insert_chip( // RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails, // RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate // fabric node/chip IDs are detected, +// RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR if input parameters +// do not specify a new fabric system master, // RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master -// is detected based on chip state and input paramters, +// error is detected based on chip state and input paramters, // RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation // is specified // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not @@ -877,30 +878,77 @@ fapi::ReturnCode proc_build_smp_process_chips( // loop over all chips passed from platform to HWP std::vector<proc_build_smp_proc_chip>::iterator i; - for (i = i_proc_chips.begin(); i != i_proc_chips.end(); i++) + std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter; + std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter; + io_smp.master_chip_curr_set = false; + + do { - // process platform provided data in chip argument, - // query chip specific attributes - proc_build_smp_chip smp_chip; - rc = proc_build_smp_process_chip(&(*i), - smp_chip); + + for (i = i_proc_chips.begin(); i != i_proc_chips.end(); i++) + { + // process platform provided data in chip argument, + // query chip specific attributes + proc_build_smp_chip smp_chip; + rc = proc_build_smp_process_chip(&(*i), + smp_chip); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_process_chip"); + break; + } + + // insert chip into SMP data structure given node & chip ID + rc = proc_build_smp_insert_chip(smp_chip, + i_op, + io_smp); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_insert_chip"); + break; + } + } if (!rc.ok()) { - FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_process_chip"); break; } - // insert chip into SMP data structure given node & chip ID - rc = proc_build_smp_insert_chip(smp_chip, - (i == i_proc_chips.begin()), - i_op, - io_smp); + if (!io_smp.master_chip_curr_set) + { + FAPI_ERR("proc_build_smp_process_chips: No system master specified!"); + const uint8_t& OP = i_op; + FAPI_SET_HWP_ERROR( + rc, + RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR); + break; + } + + for (n_iter = io_smp.nodes.begin(); + (n_iter != io_smp.nodes.end()) && (rc.ok()); + n_iter++) + { + for (p_iter = n_iter->second.chips.begin(); + (p_iter != n_iter->second.chips.end()) && (rc.ok()); + p_iter++) + { + if (((i_op == SMP_ACTIVATE_PHASE1) && + (p_iter->second.issue_quiesce_next)) || + ((i_op == SMP_ACTIVATE_PHASE2) && + (n_iter->first != io_smp.master_chip_curr_node_id))) + { + p_iter->second.quiesced_next = true; + } + else + { + p_iter->second.quiesced_next = false; + } + } + } if (!rc.ok()) { - FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_insert_chip"); break; } - } + } while(0); // mark function exit FAPI_DBG("proc_build_smp_process_chips: End"); @@ -918,7 +966,6 @@ fapi::ReturnCode proc_build_smp( { fapi::ReturnCode rc; proc_build_smp_system smp; - smp.master_chip_curr_set = false; // mark function entry FAPI_DBG("proc_build_smp: Start"); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H index 2f3330554..0bc9d64a5 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.H,v 1.10 2013/07/30 20:51:20 jmcgill Exp $ +// $Id: proc_build_smp.H,v 1.11 2013/09/26 18:14:06 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $ //------------------------------------------------------------------------------ // *| @@ -57,10 +57,6 @@ // *! (switch A/B) // *! //------------------------------------------------------------------------------ -// *! TODO:: epsilon: need updated pre-epsilon values (current: P7 values) -// *! TODO:: switch CD: hang rate for foreign links & other lab tuned settings -// *! (current: placeholder settings from Murano sim) -// *! TODO:: phase 2 execution for Venice (FSP drawer integration) // *! TODO:: support for manufacturing AVP mode configurations //------------------------------------------------------------------------------ @@ -93,18 +89,25 @@ enum proc_build_smp_operation }; // HWP argument structure defining properties of this chip -// and links which should be considered in this invocation (X/A/F) +// and links which should be considered struct proc_build_smp_proc_chip { // target for this chip fapi::Target this_chip; + // set if this chip should be designated fabric + // master post-reconfiguration + // NOTE: this chip must currently be designated a + // master in its enclosing fabric + // PHASE1/HBI: any chip + // PHASE2/FSP: any current drawer master + bool master_chip_sys_next; - // targets defining A link connected chips + // chiplet targets connected to A links fapi::Target a0_chip; fapi::Target a1_chip; fapi::Target a2_chip; - // targets defining X link connected chips + // chiplet targets connected to X links fapi::Target x0_chip; fapi::Target x1_chip; fapi::Target x2_chip; @@ -138,7 +141,8 @@ struct proc_build_smp_chip bool master_chip_sys_curr; // node/system master designation (next) bool master_chip_node_next; - bool master_chip_sys_next; + bool issue_quiesce_next; + bool quiesced_next; // select for PCIe/DSMP mux (one per link) bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]; }; @@ -187,7 +191,8 @@ struct proc_build_smp_system { // nodes which reside in this SMP std::map<proc_fab_smp_node_id, proc_build_smp_node> nodes; - // system master chip (curr) + // current system master for the purpose of launching + // fabric reconfiguration operations bool master_chip_curr_set; proc_fab_smp_node_id master_chip_curr_node_id; proc_fab_smp_chip_id master_chip_curr_chip_id; @@ -240,10 +245,7 @@ extern "C" //------------------------------------------------------------------------------ // function: perform fabric SMP reconfiguration operations // parameters: i_proc_chips => vector of structures defining properties of each -// chip and links which should be considered in -// this invocation (A/X/F) -// NOTE: first chip in vector will become the -// fabric master after the reconfiguration +// chip and its connected links // i_op => enumerated type representing SMP build phase // (SMP_ACTIVATE_PHASE1 = HBI, // SMP_ACTIVATE_PHASE2 = FSP) @@ -271,8 +273,10 @@ extern "C" // RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails, // RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate // fabric node/chip IDs are detected, +// RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR if input parameters +// do not specify a new fabric system master, // RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master -// is detected based on chip state and input paramters, +// error is detected based on chip state and input paramters, // RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation // is specified // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if HP shadow registers are not diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C index 9dde0ca4f..ad1080a6d 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_adu.C,v 1.7 2013/05/09 03:52:14 jmcgill Exp $ +// $Id: proc_build_smp_adu.C,v 1.8 2013/09/26 18:00:08 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.C,v $ //------------------------------------------------------------------------------ // *| @@ -52,6 +52,65 @@ extern "C" //------------------------------------------------------------------------------ +// function: set action which will occur on fabric pmisc switch command +// parameters: i_target => P8 chip target +// i_switch_ab => perform switch AB operation? +// i_switch_cd => perform switch CD operation? +// returns: FAPI_RC_SUCCESS if action is configured successfully, +// else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_build_smp_adu_set_switch_action( + const fapi::Target& i_target, + const bool i_switch_ab, + const bool i_switch_cd) +{ + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + ecmdDataBufferBase pmisc_data(64), pmisc_mask(64); + + FAPI_DBG("proc_build_smp_adu_set_switch_action: Start"); + do + { + // build ADU pMisc Mode register content + FAPI_DBG("proc_build_smp_adu_set_switch_action: Writing ADU pMisc Mode register"); + // switch AB bit + rc_ecmd |= pmisc_data.writeBit( + ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT, + i_switch_ab); + rc_ecmd |= pmisc_mask.setBit( + ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT); + // switch CD bit + rc_ecmd |= pmisc_data.writeBit( + ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT, + i_switch_cd); + rc_ecmd |= pmisc_mask.setBit( + ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT); + rc.setEcmdError(rc_ecmd); + + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_adu_set_switch_action: Error 0x%x setting up ADU pMisc Mode register data buffer", + rc_ecmd); + break; + } + // write ADU pMisc Mode register content + rc = fapiPutScomUnderMask(i_target, + ADU_PMISC_MODE_0x0202000B, + pmisc_data, + pmisc_mask); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_adu_set_switch_action: fapiPutUnderMask error (ADU_PMISC_MODE_0x0202000B)"); + break; + } + } while(0); + + FAPI_DBG("proc_build_smp_adu_set_switch_action: End"); + return rc; +} + + +//------------------------------------------------------------------------------ // function: acquire ADU atomic lock to guarantee exclusive use of its // resources // parameters: i_target => P8 chip target @@ -340,30 +399,21 @@ fapi::ReturnCode proc_build_smp_adu_check_status( // NOTE: see comments above function prototype in header -fapi::ReturnCode proc_build_smp_quiesce_pb( +fapi::ReturnCode proc_build_smp_switch_cd( proc_build_smp_chip& i_smp_chip) { fapi::ReturnCode rc; // ADU status/control information proc_adu_utils_fbc_op adu_ctl; - proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl_unused; + proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl; bool adu_is_dirty = false; // mark function entry - FAPI_DBG("proc_build_smp_quiesce_pb: Start"); + FAPI_DBG("proc_build_smp_switch_cd: Start"); do { - // build ADU control structure - adu_ctl.ttype = ADU_FBC_OP_TTYPE_PBOP; - adu_ctl.tsize = ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_EN; - adu_ctl.address = 0x0ULL; - adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM; - adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH; - adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY; - adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_OVERRIDE; - adu_ctl.use_autoinc = false; - + FAPI_DBG("proc_build_smp_switch_cd: Acquiring lock for ADU"); // acquire ADU lock // only required to obtain lock for this chip, as this function will // only be executed when fabric is configured as single chip island @@ -373,7 +423,7 @@ fapi::ReturnCode proc_build_smp_quiesce_pb( PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_acquire_lock"); + FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_acquire_lock"); break; } // NOTE: lock is now held, if an operation fails from this point @@ -387,18 +437,48 @@ fapi::ReturnCode proc_build_smp_quiesce_pb( rc = proc_build_smp_adu_reset(i_smp_chip.chip->this_chip); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_reset"); + FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_reset"); + break; + } + FAPI_DBG("proc_build_smp_switch_cd: ADU lock held"); + + // condition for switch CD operation + rc = proc_build_smp_adu_set_switch_action( + i_smp_chip.chip->this_chip, + false, + true); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_set_switch_action (set)"); break; } + // build ADU control structure + adu_ctl.ttype = ADU_FBC_OP_TTYPE_PMISC; + adu_ctl.tsize = ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB; + adu_ctl.address = 0x0ULL; + adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM; + adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH; + adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY; + adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_OVERRIDE; + adu_ctl.use_autoinc = false; + + adu_hp_ctl.do_tm_quiesce = true; + adu_hp_ctl.do_pre_quiesce = true; + adu_hp_ctl.do_post_init = true; + adu_hp_ctl.post_quiesce_delay = PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY; + adu_hp_ctl.pre_init_delay = PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY; + // launch command + FAPI_DBG("proc_build_smp_switch_cd: Issuing switch CD from %s", + i_smp_chip.chip->this_chip.toEcmdString()); rc = proc_adu_utils_send_fbc_op(i_smp_chip.chip->this_chip, adu_ctl, - false, - adu_hp_ctl_unused); + true, + adu_hp_ctl); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_adu_utils_send_fbc_op"); + FAPI_ERR("proc_build_smp_switch_cd: Error from proc_adu_utils_send_fbc_op"); break; } @@ -406,80 +486,118 @@ fapi::ReturnCode proc_build_smp_quiesce_pb( rc = proc_build_smp_adu_check_status(i_smp_chip.chip->this_chip); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_check_status"); + FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_check_status"); + break; + } + + // reset switch controls + rc = proc_build_smp_adu_set_switch_action( + i_smp_chip.chip->this_chip, + false, + false); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_set_switch_action (reset)"); break; } // release ADU lock + FAPI_DBG("proc_build_smp_switch_cd: Releasing lock for ADU"); rc = proc_build_smp_adu_release_lock( i_smp_chip.chip->this_chip, PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_release_lock"); + FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_release_lock"); break; } + FAPI_DBG("proc_build_smp_switch_cd: ADU lock released"); } while(0); // if error has occurred and ADU is dirty, // attempt to reset ADU and free lock (propogate rc of original fail) if (!rc.ok() && adu_is_dirty) { + FAPI_INF("proc_build_smp_switch_cd: Attempting to reset/free lock on ADU"); + (void) proc_build_smp_adu_set_switch_action(i_smp_chip.chip->this_chip, false, false); (void) proc_build_smp_adu_reset(i_smp_chip.chip->this_chip); (void) proc_build_smp_adu_release_lock(i_smp_chip.chip->this_chip, 1); } // mark function exit - FAPI_DBG("proc_build_smp_quiesce_pb: End"); + FAPI_DBG("proc_build_smp_switch_cd: End"); return rc; } // NOTE: see comments above function prototype in header -fapi::ReturnCode proc_build_smp_switch_cd( - proc_build_smp_chip& i_smp_chip) +fapi::ReturnCode proc_build_smp_quiesce_pb( + proc_build_smp_system& i_smp, + const proc_build_smp_operation i_op) { fapi::ReturnCode rc; + std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter; + std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter; + std::vector<proc_build_smp_chip*>::iterator quiesce_iter; // ADU status/control information proc_adu_utils_fbc_op adu_ctl; proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl; bool adu_is_dirty = false; // mark function entry - FAPI_DBG("proc_build_smp_switch_cd: Start"); + FAPI_DBG("proc_build_smp_quiesce_pb: Start"); do { - // acquire ADU lock - // only required to obtain lock for this chip, as this function will - // only be executed when fabric is configured as single chip island - rc = proc_build_smp_adu_acquire_lock( - i_smp_chip.chip->this_chip, - PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS, - PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK); - if (!rc.ok()) + FAPI_DBG("proc_build_smp_quiesce_pb: Acquiring lock for all ADU units in fabric"); + // loop through all chips, lock & reset ADU + for (n_iter = i_smp.nodes.begin(); + (n_iter != i_smp.nodes.end()) && (rc.ok()); + n_iter++) { - FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_acquire_lock"); - break; - } - // NOTE: lock is now held, if an operation fails from this point - // to the end of the procedure: - // o attempt to cleanup/release lock (so that procedure does not - // leave the ADU in a locked state) - // o return rc of original fail - adu_is_dirty = true; + for (p_iter = n_iter->second.chips.begin(); + (p_iter != n_iter->second.chips.end()) && (rc.ok()); + p_iter++) + { + // acquire ADU lock + rc = proc_build_smp_adu_acquire_lock( + p_iter->second.chip->this_chip, + ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS): + (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS)), + ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK): + (PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK))); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_acquire_lock"); + break; + } + // NOTE: lock is now held, if an operation fails from this point + // to the end of the procedure: + // o attempt to cleanup/release lock (so that procedure does not + // leave the ADU in a locked state) + // o return rc of original fail + adu_is_dirty = true; - // reset ADU - rc = proc_build_smp_adu_reset(i_smp_chip.chip->this_chip); + // reset ADU + rc = proc_build_smp_adu_reset(p_iter->second.chip->this_chip); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_reset"); + break; + } + } + } if (!rc.ok()) { - FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_reset"); break; } + FAPI_DBG("proc_build_smp_quiesce_pb: All ADU locks held"); // build ADU control structure - adu_ctl.ttype = ADU_FBC_OP_TTYPE_PMISC; - adu_ctl.tsize = ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB; + adu_ctl.ttype = ADU_FBC_OP_TTYPE_PBOP; + adu_ctl.tsize = ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_EN; adu_ctl.address = 0x0ULL; adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM; adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH; @@ -487,62 +605,114 @@ fapi::ReturnCode proc_build_smp_switch_cd( adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_OVERRIDE; adu_ctl.use_autoinc = false; - adu_hp_ctl.do_tm_quiesce = false; - adu_hp_ctl.do_pre_quiesce = true; - adu_hp_ctl.do_post_init = true; - adu_hp_ctl.post_quiesce_delay = PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY; - adu_hp_ctl.pre_init_delay = PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY; - adu_hp_ctl.do_switch_ab = false; - adu_hp_ctl.do_switch_cd = true; + adu_hp_ctl.do_tm_quiesce = true; + adu_hp_ctl.do_pre_quiesce = false; + adu_hp_ctl.do_post_init = false; + adu_hp_ctl.post_quiesce_delay = 0x0; + adu_hp_ctl.pre_init_delay = 0x0; - // launch command - rc = proc_adu_utils_send_fbc_op(i_smp_chip.chip->this_chip, - adu_ctl, - true, - adu_hp_ctl); - if (!rc.ok()) + // issue quiesce on all specified chips + for (n_iter = i_smp.nodes.begin(); + (n_iter != i_smp.nodes.end()) && (rc.ok()); + n_iter++) { - FAPI_ERR("proc_build_smp_switch_cd: Error from proc_adu_utils_send_fbc_op"); - break; + for (p_iter = n_iter->second.chips.begin(); + (p_iter != n_iter->second.chips.end()) && (rc.ok()); + p_iter++) + { + if (p_iter->second.issue_quiesce_next) + { + FAPI_DBG("proc_build_smp_quiesce_pb: Issuing quiesce from %s", + p_iter->second.chip->this_chip.toEcmdString()); + // launch command + rc = proc_adu_utils_send_fbc_op(p_iter->second.chip->this_chip, + adu_ctl, + true, + adu_hp_ctl); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_adu_utils_send_fbc_op"); + break; + } + + // check status + rc = proc_build_smp_adu_check_status(p_iter->second.chip->this_chip); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_check_status"); + break; + } + } + } } - - // check status - rc = proc_build_smp_adu_check_status(i_smp_chip.chip->this_chip); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_check_status"); break; } - // release ADU lock - rc = proc_build_smp_adu_release_lock( - i_smp_chip.chip->this_chip, - PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS); + FAPI_DBG("proc_build_smp_quiesce_pb: Releasing lock for all ADU units in drawer"); + // loop through all chips, unlock ADUs + for (n_iter = i_smp.nodes.begin(); + (n_iter != i_smp.nodes.end()) && (rc.ok()); + n_iter++) + { + for (p_iter = n_iter->second.chips.begin(); + (p_iter != n_iter->second.chips.end()) && (rc.ok()); + p_iter++) + { + // release ADU lock + rc = proc_build_smp_adu_release_lock( + p_iter->second.chip->this_chip, + ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS): + (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS))); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_release_lock"); + break; + } + } + } if (!rc.ok()) { - FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_release_lock"); break; } + FAPI_DBG("proc_build_smp_quiesce_pb: All ADU locks released"); } while(0); - // if error has occurred and ADU is dirty, - // attempt to reset ADU and free lock (propogate rc of original fail) + + // if error has occurred and any ADU is dirty, + // attempt to reset all ADUs and free locks (propogate rc of original fail) if (!rc.ok() && adu_is_dirty) { - (void) proc_build_smp_adu_reset(i_smp_chip.chip->this_chip); - (void) proc_build_smp_adu_release_lock(i_smp_chip.chip->this_chip, 1); + FAPI_INF("proc_build_smp_quiesce_pb: Attempting to reset/free lock on all ADUs"); + // loop through all chips, unlock ADUs + for (n_iter = i_smp.nodes.begin(); + n_iter != i_smp.nodes.end(); + n_iter++) + { + for (p_iter = n_iter->second.chips.begin(); + p_iter != n_iter->second.chips.end(); + p_iter++) + { + (void) proc_build_smp_adu_reset(p_iter->second.chip->this_chip); + (void) proc_build_smp_adu_release_lock( + p_iter->second.chip->this_chip, + 1); + } + } } - // mark function exit - FAPI_DBG("proc_build_smp_switch_cd: End"); + // mark function entry + FAPI_DBG("proc_build_smp_quiesce_pb: End"); return rc; } // NOTE: see comments above function prototype in header fapi::ReturnCode proc_build_smp_switch_ab( - proc_build_smp_chip& i_master_smp_chip, - proc_build_smp_system& i_smp) + proc_build_smp_system& i_smp, + const proc_build_smp_operation i_op) { fapi::ReturnCode rc; std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter; @@ -557,6 +727,7 @@ fapi::ReturnCode proc_build_smp_switch_ab( do { + FAPI_DBG("proc_build_smp_switch_ab: Acquiring lock for all ADU units in fabric"); // loop through all chips, lock & reset ADU for (n_iter = i_smp.nodes.begin(); (n_iter != i_smp.nodes.end()) && (rc.ok()); @@ -569,8 +740,12 @@ fapi::ReturnCode proc_build_smp_switch_ab( // acquire ADU lock rc = proc_build_smp_adu_acquire_lock( p_iter->second.chip->this_chip, - PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS, - PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK); + ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS): + (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS)), + ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK): + (PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK))); if (!rc.ok()) { FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_acquire_lock"); @@ -590,12 +765,26 @@ fapi::ReturnCode proc_build_smp_switch_ab( FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_reset"); break; } + + // condition for switch AB operation + // all chips which were not quiesced prior to switch AB will + // need to observe the switch + rc = proc_build_smp_adu_set_switch_action( + p_iter->second.chip->this_chip, + !p_iter->second.quiesced_next, + false); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_set_switch_action (set)"); + break; + } } } if (!rc.ok()) { break; } + FAPI_DBG("proc_build_smp_switch_ab: All ADU locks held"); // build ADU control structure adu_ctl.ttype = ADU_FBC_OP_TTYPE_PMISC; @@ -607,16 +796,20 @@ fapi::ReturnCode proc_build_smp_switch_ab( adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_OVERRIDE; adu_ctl.use_autoinc = false; - adu_hp_ctl.do_tm_quiesce = false; + adu_hp_ctl.do_tm_quiesce = true; adu_hp_ctl.do_pre_quiesce = true; adu_hp_ctl.do_post_init = true; - adu_hp_ctl.post_quiesce_delay = PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY; - adu_hp_ctl.pre_init_delay = PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY; - adu_hp_ctl.do_switch_ab = true; - adu_hp_ctl.do_switch_cd = false; + adu_hp_ctl.post_quiesce_delay = ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY): + (PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY)); + adu_hp_ctl.pre_init_delay = ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY): + (PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY)); // launch command - rc = proc_adu_utils_send_fbc_op(i_master_smp_chip.chip->this_chip, + FAPI_DBG("proc_build_smp_switch_ab: Issuing switch AB from %s", + i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip.toEcmdString()); + rc = proc_adu_utils_send_fbc_op(i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip, adu_ctl, true, adu_hp_ctl); @@ -627,7 +820,7 @@ fapi::ReturnCode proc_build_smp_switch_ab( } // check status - rc = proc_build_smp_adu_check_status(i_master_smp_chip.chip->this_chip); + rc = proc_build_smp_adu_check_status(i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip); if (!rc.ok()) { FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_check_status"); @@ -635,6 +828,7 @@ fapi::ReturnCode proc_build_smp_switch_ab( } // loop through all chips, unlock ADUs + FAPI_DBG("proc_build_smp_switch_ab: Releasing lock for all ADU units in drawer"); for (n_iter = i_smp.nodes.begin(); (n_iter != i_smp.nodes.end()) && (rc.ok()); n_iter++) @@ -643,10 +837,23 @@ fapi::ReturnCode proc_build_smp_switch_ab( (p_iter != n_iter->second.chips.end()) && (rc.ok()); p_iter++) { + // reset switch action + rc = proc_build_smp_adu_set_switch_action( + p_iter->second.chip->this_chip, + false, + false); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_set_switch_action (clear)"); + break; + } + // release ADU lock rc = proc_build_smp_adu_release_lock( p_iter->second.chip->this_chip, - PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS); + ((i_op == SMP_ACTIVATE_PHASE1)? + (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS): + (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS))); if (!rc.ok()) { FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_release_lock"); @@ -654,13 +861,18 @@ fapi::ReturnCode proc_build_smp_switch_ab( } } } + if (!rc.ok()) + { + break; + } + FAPI_DBG("proc_build_smp_switch_ab: All ADU locks released"); } while(0); - // if error has occurred and any ADU is dirty, // attempt to reset all ADUs and free locks (propogate rc of original fail) if (!rc.ok() && adu_is_dirty) { + FAPI_INF("proc_build_smp_switch_ab: Attempting to reset/free lock on all ADUs"); // loop through all chips, unlock ADUs for (n_iter = i_smp.nodes.begin(); n_iter != i_smp.nodes.end(); @@ -670,6 +882,7 @@ fapi::ReturnCode proc_build_smp_switch_ab( p_iter != n_iter->second.chips.end(); p_iter++) { + (void) proc_build_smp_adu_set_switch_action(p_iter->second.chip->this_chip, false, false); (void) proc_build_smp_adu_reset(p_iter->second.chip->this_chip); (void) proc_build_smp_adu_release_lock( p_iter->second.chip->this_chip, diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H index be4d538b3..b102f8213 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_adu.H,v 1.3 2013/02/25 14:50:53 jmcgill Exp $ +// $Id: proc_build_smp_adu.H,v 1.4 2013/09/26 18:00:09 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.H,v $ //------------------------------------------------------------------------------ // *| @@ -61,6 +61,9 @@ const bool PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK = true; const uint32_t PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY = 4096; const uint32_t PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY = 512; +// ADU pMISC Mode register field/bit definitions +const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT = 30; +const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT = 31; extern "C" { @@ -68,9 +71,8 @@ extern "C" { // Function prototypes //------------------------------------------------------------------------------ - //------------------------------------------------------------------------------ -// function: perform fabric quiesce on a single chip +// function: perform fabric C/D configuration switch on a single chip // parameters: i_smp_chip => structure encapsulating chip // returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of @@ -83,12 +85,19 @@ extern "C" { // for switch operation, // else error //------------------------------------------------------------------------------ -fapi::ReturnCode proc_build_smp_quiesce_pb( +fapi::ReturnCode proc_build_smp_switch_cd( proc_build_smp_chip& i_smp_chip); + //------------------------------------------------------------------------------ -// function: perform fabric C/D configuration switch on a single chip -// parameters: i_smp_chip => structure encapsulating chip +// function: quiesce slave fabrics by issuing fabric quiesce operation on +// specified chips +// NOTE: ADU atomic lock will be obtained for all chips prior +// to issuing quiesce operation on specified chips +// parameters: i_smp => structure encapsulating SMP +// i_op => enumerated type representing SMP build phase +// (SMP_ACTIVATE_PHASE1 = HBI, +// SMP_ACTIVATE_PHASE2 = FSP) // returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of // ADU atomic lock, @@ -100,19 +109,20 @@ fapi::ReturnCode proc_build_smp_quiesce_pb( // for switch operation, // else error //------------------------------------------------------------------------------ -fapi::ReturnCode proc_build_smp_switch_cd( - proc_build_smp_chip& i_smp_chip); +fapi::ReturnCode proc_build_smp_quiesce_pb( + proc_build_smp_system& i_smp, + const proc_build_smp_operation i_op); //------------------------------------------------------------------------------ -// function: perform fabric A/B configuration switch on all chips present in -// SMP (defined by i_smp) +// function: perform fabric A/B configuration switch on all chips present in SMP // NOTE: ADU atomic lock will be obtained for all chips prior to // issuing switch from master chip (defined by // i_master_smp_chip) -// parameters: i_master_smp_chip => structure encapsulating current SMP master -// chip -// i_smp => structure encapsulating SMP +// parameters: i_smp => structure encapsulating SMP +// i_op => enumerated type representing SMP build phase +// (SMP_ACTIVATE_PHASE1 = HBI, +// SMP_ACTIVATE_PHASE2 = FSP) // returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of // ADU atomic lock, @@ -125,8 +135,9 @@ fapi::ReturnCode proc_build_smp_switch_cd( // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_switch_ab( - proc_build_smp_chip& i_master_smp_chip, - proc_build_smp_system& i_smp); + proc_build_smp_system& i_smp, + const proc_build_smp_operation i_op); + } // extern "C" diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml index c70c6f450..1203a3ae7 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_build_smp_errors.xml,v 1.4 2013/05/22 15:46:58 mjjones Exp $ --> +<!-- $Id: proc_build_smp_errors.xml,v 1.5 2013/09/26 18:16:09 jmcgill Exp $ --> <!-- Error definitions for proc_build_smp --> <hwpErrors> <!-- *********************************************************************** --> @@ -45,8 +45,14 @@ <ffdc>OP</ffdc> <ffdc>MASTER_CHIP_SYS_CURR</ffdc> <ffdc>MASTER_CHIP_NODE_CURR</ffdc> - <ffdc>FIRST_CHIP_IN_SYS</ffdc> - <ffdc>FIRST_CHIP_IN_NODE</ffdc> + <ffdc>MASTER_CHIP_SYS_NEXT</ffdc> + <ffdc>MASTER_CHIP_NODE_NEXT</ffdc> + <ffdc>SYS_RECONFIG_MASTER_SET</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR</rc> + <description>Input parameters do not specify a new fabric system master.</description> + <ffdc>OP</ffdc> </hwpError> <hwpError> <rc>RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR</rc> diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C index 57204afa1..fb198f0e5 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_ab.C,v 1.5 2013/01/21 03:11:32 jmcgill Exp $ +// $Id: proc_build_smp_fbc_ab.C,v 1.9 2013/10/24 19:59:08 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.C,v $ //------------------------------------------------------------------------------ // *| @@ -143,13 +143,19 @@ fapi::ReturnCode proc_build_smp_get_f_owpack_config( //------------------------------------------------------------------------------ // function: read PB Link Mode register and extract per-link training delays -// parameters: i_smp_chip => structure encapsulating SMP chip -// i_num_links => number of links to process -// i_scom_addr => address for SCOM register containing link -// delay values -// i_link_delay_start => per-link delay field start bit offsets -// i_link_delay_end => per-link delay field end bit offsets -// o_link_delays => array of link round trip delay values +// parameters: i_smp_chip => structure encapsulating SMP chip +// i_num_links => number of links to process +// i_scom_addr => address for SCOM register containing link +// delay values +// i_link_delay_start => per-link delay field start bit offsets +// i_link_delay_end => per-link delay field end bit offsets +// i_link_en => per-link enable values +// i_link_target => link endpoint targets +// o_link_delay_local => array of link round trip delay values +// (measured by local chip) +// o_link_delay_remote => array of link round trip delay values +// (measured by remote chips) +// o_link_number_remote => array of link numbers // returns: FAPI_RC_SUCCESS if SCOM is successful & output link delays are // valid, // else error @@ -160,7 +166,11 @@ fapi::ReturnCode proc_build_smp_get_link_delays( const uint32_t i_scom_addr, const uint32_t i_link_delay_start[], const uint32_t i_link_delay_end[], - uint16_t o_link_delays[]) + const bool i_link_en[], + fapi::Target* i_link_target[], + uint16_t o_link_delay_local[], + uint16_t o_link_delay_remote[], + uint8_t o_link_number_remote[]) { fapi::ReturnCode rc; uint32_t rc_ecmd = 0x0; @@ -171,7 +181,7 @@ fapi::ReturnCode proc_build_smp_get_link_delays( do { - // read PB Link Mode register + // read PB Link Mode register on local chip rc = fapiGetScom(i_smp_chip.chip->this_chip, i_scom_addr, data); @@ -185,20 +195,97 @@ fapi::ReturnCode proc_build_smp_get_link_delays( // extract & return link training delays for (uint8_t l = 0; l < i_num_links; l++) { - rc_ecmd |= data.extractToRight( - &(o_link_delays[l]), - i_link_delay_start[l], - (i_link_delay_end[l]- - i_link_delay_start[l]+1)); + if (!i_link_en[l]) + { + o_link_delay_local[l] = 0xFF; + } + else + { + rc_ecmd |= data.extractToRight( + &(o_link_delay_local[l]), + i_link_delay_start[l], + (i_link_delay_end[l]- + i_link_delay_start[l]+1)); + + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_get_link_delays: Error 0x%x accessing data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + } + } + if (!rc.ok()) + { + break; + } - if (rc_ecmd) + // process remote links + for (uint8_t l = 0; l < i_num_links; l++) + { + if (!i_link_en[l]) { - FAPI_ERR("proc_build_smp_get_link_delays: Error 0x%x accessing data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; + o_link_delay_remote[l] = 0xFF; + } + else + { + fapi::Target parent_target; + uint8_t remote_link_number = 0x0; + + // determine link number on remote end (equivalent to chiplet #) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, + i_link_target[l], + remote_link_number); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_get_link_delays: Error querying ATTR_CHIP_UNIT_POS"); + break; + } + o_link_number_remote[l] = remote_link_number; + + // obtain parent chip target + rc = fapiGetParentChip(*(i_link_target[l]), + parent_target); + + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_get_link_delays: Error from fapiGetParentChip"); + break; + } + + // read PB link Mode Register using parent target + rc = fapiGetScom(parent_target, + i_scom_addr, + data); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_get_link_delays: fapiGetScom error (%08X)", + i_scom_addr); + break; + } + + // extract proper data + rc_ecmd |= data.extractToRight( + &(o_link_delay_remote[l]), + i_link_delay_start[remote_link_number], + (i_link_delay_end[remote_link_number]- + i_link_delay_start[remote_link_number]+1)); + + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_get_link_delays: Error 0x%x accessing data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } } } + if (!rc.ok()) + { + break; + } + } while(0); // mark function exit @@ -217,7 +304,10 @@ fapi::ReturnCode proc_build_smp_get_link_delays( // i_link_delay_start => per-link delay field start bit offsets // i_link_delay_end => per-link delay field end bit offsets // i_link_en => per-link enable values -// i_link_id => per-link ID values +// i_link_id => per-link destination chip/node ID values +// i_link_target => per-link destination targets +// i_allow_aggregate => permit aggregate configuration? +// i_x_not_a => link type (true=X, false=A) // o_link_addr_dis => per-link address disable values // (true=address only, false=address/data) // o_link_aggregate => enable aggregate link mode? @@ -235,16 +325,19 @@ fapi::ReturnCode proc_build_smp_calc_link_setup( const uint32_t i_link_delay_end[], const bool i_link_en[], const uint8_t i_link_id[], + fapi::Target * i_link_target[], + const bool i_allow_aggregate, + const bool i_x_not_a, bool o_link_addr_dis[], bool &o_link_aggregate) { fapi::ReturnCode rc; - // mark precisely which links target each ID - bool id_active[i_num_ids][i_num_links]; // mark number of links targeting each ID uint8_t id_active_count[i_num_ids]; // link round trip delay values - uint16_t link_delays[i_num_links]; + uint16_t link_delay_local[i_num_links]; + uint16_t link_delay_remote[i_num_links]; + uint8_t link_number_remote[i_num_links]; // mark function entry FAPI_DBG("proc_build_smp_calc_link_setup: Start"); @@ -255,10 +348,6 @@ fapi::ReturnCode proc_build_smp_calc_link_setup( for (uint8_t id = 0; id < i_num_ids; id++) { id_active_count[id] = 0; - for (uint8_t l = 0; l < i_num_links; l++) - { - id_active[id][l] = false; - } } // process all links @@ -268,7 +357,6 @@ fapi::ReturnCode proc_build_smp_calc_link_setup( if (i_link_en[l]) { id_active_count[i_link_id[l]]++; - id_active[i_link_id[l]][l] = true; } // set default value for link address disable (enable coherency) o_link_addr_dis[l] = false; @@ -282,7 +370,8 @@ fapi::ReturnCode proc_build_smp_calc_link_setup( if (id_active_count[id] > 1) { // design only supports one set of aggregate links per chip - if (o_link_aggregate) + // currently procedure does not support aggregate F links + if (!i_allow_aggregate || o_link_aggregate) { FAPI_ERR("proc_build_smp_calc_link_setup: Invalid aggregate link configuration"); FAPI_SET_HWP_ERROR( @@ -296,7 +385,7 @@ fapi::ReturnCode proc_build_smp_calc_link_setup( // (disable coherency) for (uint8_t l = 0; l < i_num_links; l++) { - if (id_active[id][l]) + if (i_link_en[l]) { o_link_addr_dis[l] = true; } @@ -309,29 +398,103 @@ fapi::ReturnCode proc_build_smp_calc_link_setup( i_scom_addr, i_link_delay_start, i_link_delay_end, - link_delays); + i_link_en, + i_link_target, + link_delay_local, + link_delay_remote, + link_number_remote); if (rc) { FAPI_ERR("proc_build_smp_calc_link_setup: Error from proc_build_smp_get_link_delays"); break; } - // search link delays to find smallest value - uint8_t coherent_link_id = 0; - uint16_t min_delay = 0xFFFF; for (uint8_t l = 0; l < i_num_links; l++) { - if (i_link_en[l] && (link_delays[l] <= min_delay)) + FAPI_DBG("proc_build_smp_calc_link_setup: link_delay_local[%d]: %d", l, link_delay_local[l]); + } + for (uint8_t l = 0; l < i_num_links; l++) + { + FAPI_DBG("proc_build_smp_calc_link_setup: link_delay_remote[%d]: %d", l, link_delay_remote[l]); + } + for (uint8_t l = 0; l < i_num_links; l++) + { + FAPI_DBG("proc_build_smp_calc_link_setup: link_number_remote[%d]: %d", l, link_number_remote[l]); + } + + // sum local/remote delay factors & scan for smallest value + uint32_t link_delay_total[i_num_links]; + uint8_t coherent_link_index = 0xFF; + uint32_t coherent_link_delay = 0xFFFFFFFF; + for (uint8_t l = 0; l < i_num_links; l++) + { + link_delay_total[l] = link_delay_local[l] + link_delay_remote[l]; + if (i_link_en[l] && + (link_delay_total[l] < coherent_link_delay)) { - coherent_link_id = l; - min_delay = link_delays[l]; + coherent_link_delay = link_delay_total[l]; + FAPI_DBG("proc_build_smp_calc_link_setup: Setting coherent_link_delay = %d", coherent_link_delay); } } - // assign this link to carry coherency - o_link_addr_dis[coherent_link_id] = false; + // ties must be broken consistently on both connected chips + // search if a tie has occurred + uint8_t matches = 0; + for (uint8_t l = 0; l < i_num_links; l++) + { + if (i_link_en[l] && + (link_delay_total[l] == coherent_link_delay)) + { + matches++; + coherent_link_index = l; + } + } + + // if no ties, we're done + // mark lowest aggregate latency link as coherent link + // else, break tie + // select link with lowest link number on chip with smaller ID + // (chip ID if X links, node ID if A links) + uint8_t id_local = ((i_x_not_a)?((uint8_t) i_smp_chip.chip_id):((uint8_t) i_smp_chip.node_id)); + if (matches != 1) + { + FAPI_DBG("proc_build_smp_calc_link_setup: Breaking tie"); + if (id_local < id) + { + for (uint8_t l = 0; l < i_num_links; l++) + { + if (i_link_en[l] && + (link_delay_total[l] == coherent_link_delay)) + { + coherent_link_index = l; + break; + } + } + FAPI_DBG("proc_build_smp_calc_link_setup: Selecting coherent link = link %d baaed on this chip (%d)", coherent_link_index, id_local); + } + else + { + uint8_t lowest_remote_link_number = 0xFF; + for (uint8_t l = 0; l < i_num_links; l++) + { + if ((i_link_en[l]) && + (link_delay_total[l] == coherent_link_delay) && + (link_number_remote[l] < lowest_remote_link_number)) + { + lowest_remote_link_number= link_number_remote[l]; + coherent_link_index = l; + } + } + FAPI_DBG("proc_build_smp_calc_link_setup: Selecting coherent link = linkd %d based on remote chip ID (%d)", coherent_link_index, id); + } + } + o_link_addr_dis[coherent_link_index] = false; } } + if (!rc.ok()) + { + break; + } } while(0); // mark function exit @@ -739,6 +902,7 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( ecmdDataBufferBase data(64); // set of per-link destination chip targets fapi::Target * a_target[PROC_FAB_SMP_NUM_A_LINKS]; + fapi::Target * f_target[PROC_FAB_SMP_NUM_F_LINKS]; // per-link enables bool a_en[PROC_FAB_SMP_NUM_A_LINKS]; bool f_en[PROC_FAB_SMP_NUM_F_LINKS]; @@ -804,6 +968,8 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( f_id[0] = i_smp_chip.chip->f0_node_id; f_en[1] = i_smp_chip.chip->enable_f1; f_id[1] = i_smp_chip.chip->f1_node_id; + f_target[0] = NULL; + f_target[1] = NULL; for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++) { @@ -831,6 +997,9 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( PB_A_MODE_LINK_DELAY_END_BIT, a_en, a_id, + a_target, + true, + false, a_addr_dis, a_link_aggregate); if (rc) @@ -873,6 +1042,9 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( PB_IOF_MODE_LINK_DELAY_END_BIT, f_en, f_id, + f_target, + false, + false, f_addr_dis, f_link_aggregate); if (rc) @@ -950,7 +1122,7 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( // pb_cfg_master_chip rc_ecmd |= data.writeBit(PB_HP_MODE_MASTER_CHIP_BIT, - i_smp_chip.master_chip_sys_next?1:0); + i_smp_chip.chip->master_chip_sys_next?1:0); // pb_cfg_a_aggregate rc_ecmd |= data.writeBit(PB_HP_MODE_A_AGGREGATE_BIT, @@ -958,7 +1130,7 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( // pb_cfg_tm_master rc_ecmd |= data.writeBit(PB_HP_MODE_TM_MASTER_BIT, - i_smp_chip.master_chip_sys_next?1:0); + i_smp_chip.chip->master_chip_sys_next?1:0); // pb_cfg_chg_rate_gp_master rc_ecmd |= data.writeBit(PB_HP_MODE_CHG_RATE_GP_MASTER_BIT, @@ -966,7 +1138,7 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( // pb_cfg_chg_rate_sp_master rc_ecmd |= data.writeBit(PB_HP_MODE_CHG_RATE_SP_MASTER_BIT, - i_smp_chip.master_chip_sys_next?1:0); + i_smp_chip.chip->master_chip_sys_next?1:0); // pb_cfg_pump_mode rc_ecmd |= data.writeBit(PB_HP_MODE_PUMP_MODE_BIT, @@ -1190,6 +1362,9 @@ fapi::ReturnCode proc_build_smp_set_pb_hpx_mode( PB_X_MODE_LINK_DELAY_END_BIT, x_en, x_id, + x_target, + true, + true, x_addr_dis, x_link_aggregate); if (rc) @@ -1317,7 +1492,18 @@ fapi::ReturnCode proc_build_smp_set_fbc_ab( do { - // loop through all chips + // quiesce 'slave' fabrics in preparation for joining + // PHASE1 -> quiesce all chips except the chip which is the new fabric master + // PHASE2 -> quiesce all drawers except the drawer containing the new fabric master + rc = proc_build_smp_quiesce_pb(i_smp, i_op); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_quiesce_pb"); + break; + } + + // program CURR register set only for chips which were just quiesced + // program NEXT register set for all chips for (n_iter = i_smp.nodes.begin(); (n_iter != i_smp.nodes.end()) && (rc.ok()); n_iter++) @@ -1326,26 +1512,10 @@ fapi::ReturnCode proc_build_smp_set_fbc_ab( (p_iter != n_iter->second.chips.end()) && (rc.ok()); p_iter++) { - // in SMP activate phase1, quisece hostboot slave chips - if ((i_op == SMP_ACTIVATE_PHASE1) && - (!p_iter->second.master_chip_sys_next)) - { - rc = proc_build_smp_quiesce_pb(p_iter->second); - if (!rc.ok()) - { - FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_quiesce_pb"); - break; - } - } - - // always program NEXT register set - // only program CURR register set for hostboot slave chips in - // SMP activate phase 1 rc = proc_build_smp_set_pb_hp_mode( p_iter->second, i_smp, - ((i_op == SMP_ACTIVATE_PHASE1) && - (!p_iter->second.master_chip_sys_next)), + p_iter->second.quiesced_next, true); if (!rc.ok()) { @@ -1356,8 +1526,7 @@ fapi::ReturnCode proc_build_smp_set_fbc_ab( rc = proc_build_smp_set_pb_hpx_mode( p_iter->second, i_smp, - ((i_op == SMP_ACTIVATE_PHASE1) && - (!p_iter->second.master_chip_sys_next)), + p_iter->second.quiesced_next, true); if (!rc.ok()) { @@ -1371,19 +1540,16 @@ fapi::ReturnCode proc_build_smp_set_fbc_ab( break; } - // issue switch AB from current SMP master chip - proc_fab_smp_node_id node_id = i_smp.master_chip_curr_node_id; - proc_fab_smp_chip_id chip_id = i_smp.master_chip_curr_chip_id; - rc = proc_build_smp_switch_ab( - i_smp.nodes[node_id].chips[chip_id], - i_smp); + // issue switch AB reconfiguration from chip designated as new master + // (which is guaranteed to be a master now) + rc = proc_build_smp_switch_ab(i_smp, i_op); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_switch_ab"); break; } - // reset NEXT register set (copy CURR->NEXT) + // reset NEXT register set (copy CURR->NEXT) for all chips for (n_iter = i_smp.nodes.begin(); (n_iter != i_smp.nodes.end()) && (rc.ok()); n_iter++) @@ -1407,6 +1573,11 @@ fapi::ReturnCode proc_build_smp_set_fbc_ab( } } } + if (!rc.ok()) + { + break; + } + } while(0); // mark function exit diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H index f157b2865..f847b0f9b 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_cd.H,v 1.10 2013/08/29 20:41:09 jmcgill Exp $ +// $Id: proc_build_smp_fbc_cd.H,v 1.11 2013/09/26 18:01:39 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.H,v $ //------------------------------------------------------------------------------ // *| @@ -496,7 +496,6 @@ extern "C" //------------------------------------------------------------------------------ // function: program fabric configuration register (hotplug, C/D set) // parameters: i_smp => structure encapsulating SMP topology -// i_op => enumerated type representing SMP build phase // returns: FAPI_RC_SUCCESS if register reads are successful and all shadow // registers are equivalent, // RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency |
