diff options
Diffstat (limited to 'src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule')
| -rw-r--r-- | src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule | 212 |
1 files changed, 212 insertions, 0 deletions
diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule b/src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule new file mode 100644 index 000000000..8a1280c70 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule @@ -0,0 +1,212 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # TP Chiplet Registers + ############################################################################ + + register TP_CHIPLET_CS_FIR + { + name "EH.TPCHIP.TPC.XFIR"; + scomaddr 0x01040000; + capture group default; + }; + + register TP_CHIPLET_RE_FIR + { + name "EH.TPCHIP.TPC.RFIR"; + scomaddr 0x01040001; + capture group default; + }; + + register TP_CHIPLET_FIR_MASK + { + name "EH.TPCHIP.TPC.FIR_MASK"; + scomaddr 0x01040002; + capture type secondary; + capture group default; + }; + + register TP_CHIPLET_SPA + { + name "EH.TPCHIP.TPC.EPS.FIR.SPATTN"; + scomaddr 0x01040004; + capture group default; + }; + + register TP_CHIPLET_SPA_MASK + { + name "EH.TPCHIP.TPC.EPS.FIR.SPA_MASK"; + scomaddr 0x01040007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # TP Chiplet LFIR + ############################################################################ + + register TP_LFIR + { + name "EH.TPCHIP.TPC.LOCAL_FIR"; + scomaddr 0x0104000a; + reset (&, 0x0104000b); + mask (|, 0x0104000f); + capture group default; + }; + + register TP_LFIR_MASK + { + name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0104000d; + capture type secondary; + capture group default; + }; + + register TP_LFIR_ACT0 + { + name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x01040010; + capture type secondary; + capture group never; + }; + + register TP_LFIR_ACT1 + { + name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x01040011; + capture type secondary; + capture group never; + }; + + ############################################################################ + # TP Chiplet OCCFIR + ############################################################################ + + register OCCFIR + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIR"; + scomaddr 0x01010800; + reset (&, 0x01010801); + mask (|, 0x01010805); + capture group default; + }; + + register OCCFIR_MASK + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRMASK"; + scomaddr 0x01010803; + capture type secondary; + capture group default; + }; + + register OCCFIR_ACT0 + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT0"; + scomaddr 0x01010806; + capture type secondary; + capture group default; + }; + + register OCCFIR_ACT1 + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT1"; + scomaddr 0x01010807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # TP Chiplet PBAMFIR + ############################################################################ + + register PBAMFIR + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_REG"; + scomaddr 0x01010c00; + reset (&, 0x01010c01); + mask (|, 0x01010c05); + capture group default; + }; + + register PBAMFIR_MASK + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_MASK_REG"; + scomaddr 0x01010c03; + capture type secondary; + capture group default; + }; + + register PBAMFIR_ACT0 + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_ACTION0_REG"; + scomaddr 0x01010c06; + capture type secondary; + capture group default; + }; + + register PBAMFIR_ACT1 + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_ACTION1_REG"; + scomaddr 0x01010c07; + capture type secondary; + capture group default; + }; + + ############################################################################ + # TP Chiplet PMCFIR + ############################################################################ + + register PMCFIR + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ERR_REG"; + scomaddr 0x01010840; + reset (&, 0x01010841); + mask (|, 0x01010845); + capture group default; + }; + + register PMCFIR_MASK + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ERR_MASK_REG"; + scomaddr 0x01010843; + capture type secondary; + capture group default; + }; + + register PMCFIR_ACT0 + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ACTION0_REG"; + scomaddr 0x01010846; + capture type secondary; + capture group default; + }; + + register PMCFIR_ACT1 + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ACTION1_REG"; + scomaddr 0x01010847; + capture type secondary; + capture group default; + }; + |
