diff options
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C | 88 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 43 |
2 files changed, 43 insertions, 88 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C index db0a3d737..7c381f53b 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C @@ -155,95 +155,7 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PRO "Error from FAPI_ATTR_SET (ATTR_PROC_NPU_ENABLED)"); } - // invoke IOO (OBUS FBC IO) SCOM initfiles l_obus_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_OBUS>(); - - for (auto l_obus_target : l_obus_chiplets) - { - uint8_t l_unit_pos; - uint8_t l_obus_mode; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_obus_target, l_unit_pos), - "Error from FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS)"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OPTICS_CONFIG_MODE, l_obus_target, l_obus_mode), - "Error from FAPI_ATTR_GET(ATTR_OPTICS_CONFIG_MODE)"); - - //Update NDL IOValid data as needed - if (!l_no_ndl_iovalid && (l_unit_pos == 0 || l_unit_pos == 3) && // NDL only exists on obus 0 and 3 - l_obus_mode == fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_NV && // configured for NV link - l_npu_enabled) // NPU is enabled - { - - l_obrick_targets = l_obus_target.getChildren<fapi2::TARGET_TYPE_OBUS_BRICK>(); - - for (auto l_obrick_target : l_obrick_targets) - { - fapi2::toString(l_obrick_target, l_chipletTargetStr, sizeof(l_chipletTargetStr)); - FAPI_DBG("Setting NDL IOValid for %s...", l_chipletTargetStr); - - uint8_t l_unit_pos; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_obrick_target, l_unit_pos), - "Error from FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS)"); - - //Mapping from John Irish (jdirish@us.ibm.com) - //OBus Register bit NV instance NV pos - //OB0 NV0 io_valid(A) STK0.NTL0.. 0 - //OB0 NV1 io_valid(B) STK0.NTL1.. 1 - //OB0 NV2 io_valid(C) STK1.NTL0.. 2 - //OB3 NV2 io_valid(C) STK1.NTL1.. 3 - //OB3 NV1 io_valid(B) STK2.NTL0.. 4 - //OB3 NV0 io_valid(A) STK2.NTL1.. 5 - switch (l_unit_pos) - { - case OBRICK0_POS: - l_ob0data.setBit<PERV_OB_CPLT_CONF1_OBRICKA_IOVALID>(); - break; - - case OBRICK1_POS: - l_ob0data.setBit<PERV_OB_CPLT_CONF1_OBRICKB_IOVALID>(); - break; - - case OBRICK2_POS: - l_ob0data.setBit<PERV_OB_CPLT_CONF1_OBRICKC_IOVALID>(); - break; - - //OBRICK3..8 associated with OBUS 1 & 2 do not have NDL - - case OBRICK9_POS: - l_ob3data.setBit<PERV_OB_CPLT_CONF1_OBRICKC_IOVALID>(); - break; - - case OBRICK10_POS: - l_ob3data.setBit<PERV_OB_CPLT_CONF1_OBRICKB_IOVALID>(); - break; - - case OBRICK11_POS: - l_ob3data.setBit<PERV_OB_CPLT_CONF1_OBRICKA_IOVALID>(); - break; - - default: - FAPI_ASSERT(false, fapi2::P9_CHIPLET_SCOMINIT_UNSUPPORTED_OBRICK_POS_ERR().set_TARGET(l_obrick_target), - "ERROR; Unsupported NV position."); - - } - - } - - } - - } - - //Write the NDL IOValid registers as needed. - if (l_ob0data != 0) - { - FAPI_TRY(putScom(i_target, PERV_OB0_CPLT_CONF1_OR, l_ob0data)); - } - - if (l_ob3data != 0) - { - FAPI_TRY(putScom(i_target, PERV_OB3_CPLT_CONF1_OR, l_ob3data)); - } - - l_mcs_targets = i_target.getChildren<fapi2::TARGET_TYPE_MCS>(); l_mi_targets = i_target.getChildren<fapi2::TARGET_TYPE_MI>(); l_dmi_targets = i_target.getChildren<fapi2::TARGET_TYPE_DMI>(); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 62190ec83..b76762dfc 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -5671,4 +5671,47 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW404391_SCAN</id>> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD2.1+: Workaround glxmux xstate issue by adjusting scan flush + state of selected latches in NVDL and PHY logic + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x21</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW404391_SCOM</id>> + <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD2.0 + Cumulus: Workaround glxmux xstate issue by applying SCOM + sequence + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> </attributes> |
