diff options
Diffstat (limited to 'src/import')
6 files changed, 40 insertions, 18 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 86a8bb070..6e3b54d49 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -457,6 +457,7 @@ HCD_CONST(PGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) /// PGPE Image +HCD_CONST(PGPE_AUX_TASK_SIZE, (2 * ONE_KB)) HCD_CONST(PGPE_IMAGE_PPMR_OFFSET, (PGPE_BOOT_LOADER_PPMR_OFFSET + PGPE_BOOT_LOADER_SIZE)) HCD_CONST(PGPE_IMAGE_SIZE, (48 * ONE_KB)) //RTC158543 @@ -516,6 +517,6 @@ HCD_CONST(OCC_WOF_TABLES_SIZE, (256 * ONE_KB)) HCD_CONST(WOF_TABLE_RESERVE, OCC_WOF_TABLES_PPMR_OFFSET - (PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET + PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE)) HCD_CONST(PGPE_IMAGE_RESERVE_SIZE, - (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE)) + (OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET - PGPE_IMAGE_PPMR_OFFSET - PGPE_IMAGE_SIZE - PGPE_AUX_TASK_SIZE)) #endif /* __HCD_MEMMAP_BASE_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H index c6d723444..95a222dfc 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H @@ -82,10 +82,10 @@ HCD_CONST(HOMER_PGPE_BOOT_COPIER_ADDR, (HOMER_PPMR_HEADER_ADDR + PPMR_HEADER_SIZE)) HCD_CONST(HOMER_OCC_PSTATE_PARAM_BLOCK_ADDR, - (HOMER_PPMR_BASE_ADDR + OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET)); + (HOMER_PPMR_BASE_ADDR + OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET)) HCD_CONST(HOMER_PGPE_PSTATE_OUTPUT_TABLES_ADDR, - (HOMER_PPMR_BASE_ADDR + PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET)); + (HOMER_PPMR_BASE_ADDR + PGPE_PSTATE_OUTPUT_TABLES_PPMR_OFFSET)) HCD_CONST(HOMER_OCC_WOF_TABLES_ADDR, - (HOMER_PPMR_BASE_ADDR + OCC_WOF_TABLES_PPMR_OFFSET)); + (HOMER_PPMR_BASE_ADDR + OCC_WOF_TABLES_PPMR_OFFSET)) #endif /* __P9_HCD_MEMMAP_HOMER_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H index ee2df7372..c1f9cecf8 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -82,6 +82,8 @@ HCD_CONST(OCC_SRAM_PGPE_BOOT_LOADER_RESET_ADDR, (OCC_SRAM_PGPE_BOOT_LOADER_ADDR + PGPE_BOOT_LOADER_RESET_ADDR_VAL)) HCD_CONST(OCC_SRAM_PGPE_PPMR_HEADER_ADDR, (OCC_SRAM_PGPE_BOOT_LOADER_ADDR - OCC_SRAM_PGPE_COPY_PPMR_HEADER_SIZE)) +HCD_CONST(OCC_SRAM_AUX_TASK_ADDR, + (OCC_SRAM_PGPE_PPMR_HEADER_ADDR - PGPE_AUX_TASK_SIZE)) /// PGPE Copy diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index ee7f48d33..76954c274 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -198,6 +198,8 @@ HCD_HDR_UINT32(g_ppmr_pgpe_sram_img_size, 0); // PGPE Actual SRAM Image Size HCD_HDR_UINT32(g_ppmr_pgpe_boot_prog_code, 0 );// for debug of PGPE booting HCD_HDR_UINT32(g_ppmr_wof_table_offset, 0 ); // Offset to start of WOF Table HCD_HDR_UINT32(g_ppmr_wof_table_length, 0 ); // Length of WOF table +HCD_HDR_UINT32(g_ppmr_aux_task_offset, 0 ); // PGPE Aux Task Offset +HCD_HDR_UINT32(g_ppmr_aux_task_length, 0 ); // PGPE Aux Task Length HCD_HDR_PAD(0x200); #ifdef __ASSEMBLER__ .endm @@ -327,17 +329,17 @@ typedef struct { #endif HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER); // PGPE_1.0 -HCD_HDR_UINT32(g_pgpe_sys_reset_addr, 0 ); // Fully qualified OCC address where pk_init resides -HCD_HDR_UINT32(g_pgpe_shared_sram_addr, 0 ); // SRAM address where shared SRAM begins -HCD_HDR_UINT32(g_pgpe_ivpr_addr, 0 ); // Beginning of PGPE region in OCC SRAM -HCD_HDR_UINT32(g_pgpe_shared_sram_len, 0 ); // Length of shared SRAM area -HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PGPE Image -HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version -HCD_HDR_UINT16(g_pgpe_flags, 0 ); // PGPE Flags -HCD_HDR_UINT16(g_pgpe_reserve1, 0 ); // Reserve field -HCD_HDR_UINT32(g_pgpe_reserve2, 0 ); // Reserve field -HCD_HDR_UINT32(g_pgpe_gppb_sram_addr, 0 ); // Offset to Global P State Parameter Block -HCD_HDR_UINT32(g_pgpe_hcode_length, 0 ); // Length of PGPE Hcode +HCD_HDR_UINT32(g_pgpe_sys_reset_addr, 0 ); // Fully qualified OCC address where pk_init resides +HCD_HDR_UINT32(g_pgpe_shared_sram_addr, 0 ); // SRAM address where shared SRAM begins +HCD_HDR_UINT32(g_pgpe_ivpr_addr, 0 ); // Beginning of PGPE region in OCC SRAM +HCD_HDR_UINT32(g_pgpe_shared_sram_len, 0 ); // Length of shared SRAM area +HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PGPE Image +HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version +HCD_HDR_UINT16(g_pgpe_flags, 0 ); // PGPE Flags +HCD_HDR_UINT16(g_pgpe_reserve1, 0 ); // Reserve field +HCD_HDR_UINT32(g_pgpe_reserve2, 0 ); // Reserve field +HCD_HDR_UINT32(g_pgpe_gppb_sram_addr, 0 ); // Offset to Global P State Parameter Block +HCD_HDR_UINT32(g_pgpe_hcode_length, 0 ); // Length of PGPE Hcode HCD_HDR_UINT32(g_pgpe_gppb_mem_offset, 0 ); // Offset to start of Global PS Param Block wrt start of HOMER. HCD_HDR_UINT32(g_pgpe_gppb_length, 0 ); // Length of Global P State Parameter Block @@ -620,6 +622,7 @@ typedef struct uint8_t l1BootLoader[PGPE_BOOT_COPIER_SIZE]; uint8_t l2BootLoader[PGPE_BOOT_LOADER_SIZE]; uint8_t pgpeSramImage[PGPE_IMAGE_SIZE]; // Includes the Global Pstate Parameter Block + uint8_t aux_task[PGPE_AUX_TASK_SIZE]; uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE]; uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)]; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index d0e945946..9b98d7535 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -288,6 +288,7 @@ ImgSizeBank::ImgSizeBank() iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL, (char*)"PGPE Boot Loader")] = PGPE_BOOT_LOADER_SIZE;; iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, (char*)"PGPE Hcode")] = PGPE_IMAGE_SIZE; iv_secSize[ImgSec(PLAT_PGPE, PGPE_SRAM_IMAGE, (char*)"PGPE SRAM Image")] = PGPE_IMAGE_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_AUX_TASK, (char*)"PGPE Aux Task")] = PGPE_AUX_TASK_SIZE; } /** @@ -1658,13 +1659,24 @@ fapi2::ReturnCode buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip io_ppmrHdr.g_ppmr_hcode_offset = io_ppmrHdr.g_ppmr_bl_offset + PGPE_BOOT_LOADER_SIZE; io_ppmrHdr.g_ppmr_hcode_length = ppeSection.iv_size; + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.aux_task, + pPgpeImg, + P9_XIP_SECTION_PGPE_AUX_TASK, + PLAT_PGPE, + i_procFuncModel.getChipLevel(), + ppeSection ); + + io_ppmrHdr.g_ppmr_aux_task_offset = io_ppmrHdr.g_ppmr_aux_task_offset + PGPE_AUX_TASK_SIZE; + io_ppmrHdr.g_ppmr_aux_task_length = ppeSection.iv_size; + //Finally let us take care of endianess io_ppmrHdr.g_ppmr_bc_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bc_offset); io_ppmrHdr.g_ppmr_bl_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_offset); io_ppmrHdr.g_ppmr_bl_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_length); io_ppmrHdr.g_ppmr_hcode_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset); io_ppmrHdr.g_ppmr_hcode_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); - + io_ppmrHdr.g_ppmr_aux_task_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_aux_task_offset); + io_ppmrHdr.g_ppmr_aux_task_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_aux_task_length); } fapi_try_exit: @@ -2038,6 +2050,8 @@ fapi2::ReturnCode updatePpmrHeader( void* const i_pHomer, PpmrHeader_t& io_ppmrH FAPI_DBG("BC Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset)); FAPI_DBG("BL Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_offset)); FAPI_DBG("BL Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_length)); + FAPI_DBG("Char Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_aux_task_offset)); + FAPI_DBG("Char Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_aux_task_length)); FAPI_DBG("Hcode Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_offset)); FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length)); FAPI_DBG("GPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset)); diff --git a/src/import/chips/p9/xip/p9_xip_image.h b/src/import/chips/p9/xip/p9_xip_image.h index 859cdd89e..838f0276c 100644 --- a/src/import/chips/p9/xip/p9_xip_image.h +++ b/src/import/chips/p9/xip/p9_xip_image.h @@ -1948,7 +1948,8 @@ typedef enum P9_XIP_SECTION_PGPE_LVL1_BL = P9_XIP_SECTIONS_PLUS(1), P9_XIP_SECTION_PGPE_LVL2_BL = P9_XIP_SECTIONS_PLUS(2), P9_XIP_SECTION_PGPE_HCODE = P9_XIP_SECTIONS_PLUS(3), - P9_XIP_SECTIONS_PGPE = P9_XIP_SECTIONS_PLUS(4) // # sections + P9_XIP_SECTION_PGPE_AUX_TASK = P9_XIP_SECTIONS_PLUS(4), + P9_XIP_SECTIONS_PGPE = P9_XIP_SECTIONS_PLUS(5) // # sections } p9_xip_section_pgpe_t; #define P9_XIP_SECTION_NAMES_PGPE(var) \ @@ -1956,7 +1957,8 @@ typedef enum ".ppmr_header", \ ".lvl1_bl", \ ".lvl2_bl", \ - ".hcode") + ".hcode", \ + ".aux_task") /**************************************************************************/ /* IOPPE Image */ |
