diff options
Diffstat (limited to 'src/import')
4 files changed, 46 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index 002df9591..101bceaf3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -27379,6 +27379,28 @@ fapi_try_exit: } /// +/// @brief ATTR_DD1_SLOW_PCI_REF_CLOCK getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note MRW control to permit Normal (100 MHz) or Slow (94 MHz) operation of PCIE +/// reference clock. On Nimbus DD1 HW, Slow operation is required to achieve Gen4 +/// operation. Provided by the +/// MRW. +/// +inline fapi2::ReturnCode dd1_slow_pci_ref_clock(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_DD1_SLOW_PCI_REF_CLOCK: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// /// @brief ATTR_PROC_FABRIC_ASYNC_SAFE_MODE getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 7bdba09db..d7d0ad22a 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1844,10 +1844,10 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</id> + <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - DD1 only: leverage SS PLL to provide reduced frequency reference clock + DD1 only: enable use of SS PLL to provide reduced frequency reference clock (94 MHz, instead of nominal 100 MHz) for PCI PLL </description> <chipEcFeature> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index b146722f7..2411ca673 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -136,6 +136,24 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_DD1_SLOW_PCI_REF_CLOCK</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + MRW control to permit Normal (100 MHz) or Slow (94 MHz) operation + of PCIE reference clock. On Nimbus DD1 HW, Slow operation is required + to achieve Gen4 operation. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + NORMAL = 0x00, + SLOW = 0x01 + </enum> + <platInit/> + <writeable/> + </attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml index 3e114e76e..e4354a87d 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml @@ -153,6 +153,10 @@ <id>ATTR_PROC_EFF_FABRIC_CHIP_ID</id> <default>0x0</default> </attribute> + <attribute> + <id>ATTR_DD1_SLOW_PCI_REF_CLOCK</id> + <default>0x01</default> + </attribute> <attribute> <id>ATTR_SYSTEM_DISABLE_QUEUED_SCAN</id> <default>0x00</default> |