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-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H3
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C88
-rwxr-xr-xsrc/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C8
-rwxr-xr-xsrc/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H3
-rwxr-xr-xsrc/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C194
5 files changed, 111 insertions, 185 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index cf9e8b1a6..8e40f6dcb 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -307,14 +307,11 @@ enum
MAX_CORES_PER_EX = 2,
CORE0_CHIPLET_ID = 0x20,
PAD_OPCODE = 0x00000200, //ATTN Opcode
- BLR_INST = 0x4e800020, //blr instruction
- THREAD_RESTORE_AREA_SIZE = 2048,
PPE_RESERVE_AREA = 0x200,
FUSED_MODE = 0xBB,
NONFUSED_MODE = 0xAA,
PK_DBG_PTR_AREA_SIZE = 64,
SCOM_ENTRY_SIZE = 16, // 4B pad, 4B address, 8B data
- SCOM_RESTORE_PER_CHIPLET = 64, // size in words (16B * 16)/4
//---- QPMR ----
QPMR_OFFSET = HOMER_QPMR_REGION_NUM * ONE_MB,
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 2a4060f59..a8d74098d 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -374,55 +374,7 @@ extern "C"
return exChipletId;
}
- //-------------------------------------------------------------------------------------------------
- void initScomRegion( Homerlayout_t* i_pChipHomer, PlatId i_platId )
- {
- FAPI_DBG(">initScomRegion");
-
- do
- {
- uint32_t* pInitScom = NULL;
- uint32_t initLength = MAX_CACHE_CHIPLET;
- uint32_t fillPattern = SWIZZLE_4_BYTE(PAD_OPCODE);
-
- if( ( PLAT_SELF != i_platId ) && ( PLAT_SGPE != i_platId ) )
- {
- FAPI_ERR("SCOM Region not defined for given platform 0x%08x", i_platId );
- break;
- }
-
- if( PLAT_SELF == i_platId )
- {
- pInitScom = (uint32_t*)i_pChipHomer->cpmrRegion.selfRestoreRegion.coreScom;
- initLength = MAX_CORES_PER_CHIP;
-
- }
-
- if( PLAT_SGPE == i_platId )
- {
- pInitScom = (uint32_t*)i_pChipHomer->qpmrRegion.cacheScomRegion;
- }
-
- uint32_t wordCnt = 0;
- uint32_t scomSize = CACHE_SCOM_RESTORE_SIZE >> 2;
-
- for( wordCnt = 0; wordCnt < scomSize; wordCnt++ )
- {
- memcpy( (pInitScom + wordCnt), &fillPattern, sizeof(uint32_t) );
- }
-
- fillPattern = SWIZZLE_4_BYTE(BLR_INST);
-
- for( wordCnt = 0; wordCnt < initLength; wordCnt++ )
- {
- memcpy( (pInitScom + (wordCnt * SCOM_RESTORE_PER_CHIPLET)) , &fillPattern, sizeof(uint32_t) );
- }
- }
- while(0);
-
- FAPI_DBG("<initScomRegion");
- }
- //-------------------------------------------------------------------------------------------------
+ //-------------------------------------------------------------------------
uint32_t validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize )
{
@@ -957,8 +909,6 @@ extern "C"
break;
}
- initScomRegion( i_pChipHomer, PLAT_SGPE );
-
o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_LVL_2_BOOT_LOAD_SIZE;
FAPI_DBG("SGPE Hcode QPMR Offset = 0x%08X, Size = 0x%08X",
@@ -1075,29 +1025,10 @@ extern "C"
//Padding SPR restore area with ATTN Opcode
FAPI_INF("Padding CPMR Core Restore portion with Attn opcodes");
uint32_t wordCnt = 0;
- uint32_t l_fillBlr = SWIZZLE_4_BYTE(BLR_INST);
- uint32_t l_fillAttn = SWIZZLE_4_BYTE(PAD_OPCODE);
+ uint32_t l_fillPattern = SWIZZLE_4_BYTE(PAD_OPCODE);
while( wordCnt < CORE_RESTORE_SIZE )
{
-
- uint32_t l_fillPattern = 0;
-
- if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % THREAD_RESTORE_AREA_SIZE ) ))
- {
- l_fillPattern = l_fillBlr;
- }
- else
- {
- l_fillPattern = l_fillAttn;
- }
-
- //Lab Need: First instruction in thread SPR restore region should be a blr instruction.
- //This helps in a specific lab scenario. If Self Restore region is populated only for
- //select number of threads, other threads will not hit attention during the self restore
- //sequence. Instead, execution will hit a blr and control should return to thread launcher
- //region.
-
memcpy( (uint32_t*)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[wordCnt],
&l_fillPattern,
sizeof( uint32_t ));
@@ -1105,7 +1036,6 @@ extern "C"
}
updateCpmrHeaderSR( i_pChipHomer, i_fusedState );
- initScomRegion( i_pChipHomer, PLAT_SELF );
}
while(0);
@@ -1275,7 +1205,7 @@ extern "C"
return retCode;
}
-//------------------------------------------------------------------------------
+ //------------------------------------------------------------------------------
/**
* @brief get a blob of platform rings in a temp buffer.
@@ -1362,7 +1292,7 @@ extern "C"
return retCode;
}
-//------------------------------------------------------------------------------
+ //------------------------------------------------------------------------------
uint32_t layoutSgpeScanOverride( Homerlayout_t* i_pHomer,
void* i_pOverride,
@@ -1473,7 +1403,7 @@ extern "C"
return rc;
}
-//------------------------------------------------------------------------------
+ //------------------------------------------------------------------------------
/**
* @brief creates a lean scan ring layout for core specific rings in HOMER.
@@ -1567,7 +1497,7 @@ extern "C"
return rc;
}
-//------------------------------------------------------------------------------
+ //------------------------------------------------------------------------------
/**
* @brief creates a lean scan ring layout for core specific rings in HOMER.
* @param i_pHOMER points to HOMER image.
@@ -1727,7 +1657,7 @@ extern "C"
return rc;
}
-//------------------------------------------------------------------------------
+ //------------------------------------------------------------------------------
uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer,
void* i_pOverride,
@@ -1822,7 +1752,7 @@ extern "C"
return rc;
}
-//------------------------------------------------------------------------------
+ //------------------------------------------------------------------------------
/**
* @brief creates a lean scan ring layout for core rings in HOMER.
@@ -1964,7 +1894,7 @@ extern "C"
}
-//------------------------------------------------------------------------------
+ //------------------------------------------------------------------------------
/**
* @brief creates a scan ring layout for quad common rings in HOMER.
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
index 2842ece06..f76a4d62b 100755
--- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
+++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
@@ -526,8 +526,7 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage,
&(chipHomer->coreThreadRestore[coreId][threadId].coreArea[0]);
}
- if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) ||
- ( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) )
+ if( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*)pThreadLocation )
{
// table for given core id doesn't exit. It needs to be
// defined.
@@ -865,7 +864,6 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage,
uint32_t swizzleAttn = SWIZZLE_4_BYTE(ATTN_OPCODE);
uint32_t swizzleEntry = SWIZZLE_4_BYTE(SCOM_ENTRY_START);
uint32_t index = 0;
- uint32_t swizzleBlr = SWIZZLE_4_BYTE(BLR_INST);
for( index = 0; index < entryLimit; ++index )
{
@@ -878,8 +876,8 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage,
}
if( (( nopInst == entrySwzAddress ) ||
- ( swizzleAttn == entrySwzAddress ) ||
- ( swizzleBlr == entrySwzAddress )) && ( !pNopLocation ) )
+ ( swizzleAttn == entrySwzAddress )) &&
+ ( !pNopLocation ) )
{
pNopLocation = &pScomEntry[index];
}
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
index e9cfa29a7..80d8c4196 100755
--- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
+++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H
@@ -64,7 +64,8 @@ typedef struct
*/
typedef struct
{
- uint8_t threadArea[THREAD_AREA_SIZE];
+ uint8_t threadArea[THREAD_SECTN_SIZE];
+ uint8_t reserve[THREAD_AREA_SIZE - THREAD_SECTN_SIZE];
uint8_t coreArea[CORE_SPR_SECTN_SIZE];
} SprRestoreArea_t;
diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C
index fa13eee64..7fdc1deee 100755
--- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C
+++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -50,48 +50,48 @@ namespace stopImageSection
*/
StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode )
{
-*o_fusedMode = false;
-StopReturnCode_t l_rc = STOP_SAVE_SUCCESS;
+ *o_fusedMode = false;
+ StopReturnCode_t l_rc = STOP_SAVE_SUCCESS;
-do
-{
- if( !i_pImage )
+ do
{
- MY_ERR( "invalid pointer to HOMER image");
- l_rc = STOP_SAVE_ARG_INVALID_IMG;
- break;
- }
+ if( !i_pImage )
+ {
+ MY_ERR( "invalid pointer to HOMER image");
+ l_rc = STOP_SAVE_ARG_INVALID_IMG;
+ break;
+ }
- HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage;
- HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler );
+ HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage;
+ HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler );
- if( SWIZZLE_8_BYTE(CPMR_MAGIC_WORD) != pHomer->cpmrMagicWord )
- {
- MY_ERR("corrupt or invalid HOMER image location 0x%016llx",
- SWIZZLE_8_BYTE(pHomer->cpmrMagicWord) );
- l_rc = STOP_SAVE_ARG_INVALID_IMG;
- break;
- }
+ if( SWIZZLE_8_BYTE(CPMR_MAGIC_WORD) != pHomer->cpmrMagicWord )
+ {
+ MY_ERR("corrupt or invalid HOMER image location 0x%016llx",
+ SWIZZLE_8_BYTE(pHomer->cpmrMagicWord) );
+ l_rc = STOP_SAVE_ARG_INVALID_IMG;
+ break;
+ }
- if( (uint8_t) FUSED_MODE == pHomer->fusedModeStatus )
- {
- *o_fusedMode = true;
- break;
- }
+ if( (uint8_t) FUSED_MODE == pHomer->fusedModeStatus )
+ {
+ *o_fusedMode = true;
+ break;
+ }
- if( (uint8_t) NONFUSED_MODE == pHomer->fusedModeStatus )
- {
- break;
- }
+ if( (uint8_t) NONFUSED_MODE == pHomer->fusedModeStatus )
+ {
+ break;
+ }
- MY_ERR("Unexpected value 0x%08x for fused mode. Bad or corrupt "
- "HOMER location", pHomer->fuseModeStatus );
- l_rc = STOP_SAVE_INVALID_FUSED_CORE_STATUS ;
+ MY_ERR("Unexpected value 0x%08x for fused mode. Bad or corrupt "
+ "HOMER location", pHomer->fuseModeStatus );
+ l_rc = STOP_SAVE_INVALID_FUSED_CORE_STATUS ;
-}
-while(0);
+ }
+ while(0);
-return l_rc;
+ return l_rc;
}
//----------------------------------------------------------------------
@@ -99,81 +99,81 @@ return l_rc;
StopReturnCode_t getCoreAndThread( void* const i_pImage, const uint64_t i_pir,
uint32_t* o_pCoreId, uint32_t* o_pThreadId )
{
-StopReturnCode_t l_rc = STOP_SAVE_SUCCESS;
-
-do
-{
- // for SPR restore using 'Virtual Thread' and 'Physical Core' number
- // In Fused Mode:
- // bit b28 and b31 of PIR give physical core and b29 and b30 gives
- // virtual thread id.
- // In Non Fused Mode
- // bit 28 and b29 of PIR give both logical and physical core number
- // whereas b30 and b31 gives logical and virtual thread id.
- bool fusedMode = false;
- uint8_t coreThreadInfo = (uint8_t)i_pir;
- *o_pCoreId = 0;
- *o_pThreadId = 0;
- l_rc = isFusedMode( i_pImage, &fusedMode );
-
- if( l_rc )
- {
- MY_ERR(" Checking Fused mode. Read failed 0x%08x", l_rc );
- break;
- }
-
- if( fusedMode )
- {
- if( coreThreadInfo & FUSED_CORE_BIT1 )
- {
- *o_pThreadId = 2;
- }
-
- if( coreThreadInfo & FUSED_CORE_BIT2 )
- {
- *o_pThreadId += 1;
- }
-
- if( coreThreadInfo & FUSED_CORE_BIT0 )
- {
- *o_pCoreId = 2;
- }
+ StopReturnCode_t l_rc = STOP_SAVE_SUCCESS;
- if( coreThreadInfo & FUSED_CORE_BIT3 )
- {
- *o_pCoreId += 1;
- }
- }
- else
+ do
{
- if( coreThreadInfo & FUSED_CORE_BIT0 )
+ // for SPR restore using 'Virtual Thread' and 'Physical Core' number
+ // In Fused Mode:
+ // bit b28 and b31 of PIR give physical core and b29 and b30 gives
+ // virtual thread id.
+ // In Non Fused Mode
+ // bit 28 and b29 of PIR give both logical and physical core number
+ // whereas b30 and b31 gives logical and virtual thread id.
+ bool fusedMode = false;
+ uint8_t coreThreadInfo = (uint8_t)i_pir;
+ *o_pCoreId = 0;
+ *o_pThreadId = 0;
+ l_rc = isFusedMode( i_pImage, &fusedMode );
+
+ if( l_rc )
{
- *o_pCoreId = 2;
+ MY_ERR(" Checking Fused mode. Read failed 0x%08x", l_rc );
+ break;
}
- if ( coreThreadInfo & FUSED_CORE_BIT1 )
+ if( fusedMode )
{
- *o_pCoreId += 1;
+ if( coreThreadInfo & FUSED_CORE_BIT1 )
+ {
+ *o_pThreadId = 2;
+ }
+
+ if( coreThreadInfo & FUSED_CORE_BIT2 )
+ {
+ *o_pThreadId += 1;
+ }
+
+ if( coreThreadInfo & FUSED_CORE_BIT0 )
+ {
+ *o_pCoreId = 2;
+ }
+
+ if( coreThreadInfo & FUSED_CORE_BIT3 )
+ {
+ *o_pCoreId += 1;
+ }
}
-
- if( coreThreadInfo & FUSED_CORE_BIT2 )
+ else
{
- *o_pThreadId = 2;
+ if( coreThreadInfo & FUSED_CORE_BIT0 )
+ {
+ *o_pCoreId = 2;
+ }
+
+ if ( coreThreadInfo & FUSED_CORE_BIT1 )
+ {
+ *o_pCoreId += 1;
+ }
+
+ if( coreThreadInfo & FUSED_CORE_BIT2 )
+ {
+ *o_pThreadId = 2;
+ }
+
+ if( coreThreadInfo & FUSED_CORE_BIT3 )
+ {
+ *o_pThreadId += 1;
+ }
}
- if( coreThreadInfo & FUSED_CORE_BIT3 )
- {
- *o_pThreadId += 1;
- }
+ MY_INF("Core Type %s", fusedMode ? "Fused" : "Un-Fused" );
+ //quad field is not affected by fuse mode
+ *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 );
}
+ while(0);
- MY_INF("Core Type %s", fusedMode ? "Fused" : "Un-Fused" );
- //quad field is not affected by fuse mode
- *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 );
-}
-while(0);
-
-return l_rc;
+ return l_rc;
}
#ifdef __cplusplus
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