diff options
Diffstat (limited to 'src/import/generic')
10 files changed, 312 insertions, 249 deletions
diff --git a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H index cc61ea602..807170ceb 100644 --- a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H +++ b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H @@ -402,6 +402,138 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH> } }; +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @note attr_si_engine_fields, COLUMN_ADDR_BITS specialization +/// +template<> +struct attrEngineTraits<attr_eff_engine_fields, COLUMN_ADDR_BITS> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DRAM_COLUMN_BITS_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DRAM_COLUMN_BITS_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_COL_ADDR_BITS; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dram_column_bits(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dram_column_bits(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_efd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_ADDR_COL_MAP = + { + {0b001, fapi2::ENUM_ATTR_MEM_EFF_DRAM_COLUMN_BITS_NUM10}, + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_value = 0; + FAPI_TRY(i_spd_data.column_address_bits(l_value)) + + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_dimm, DRAM_ADDR_COL_MAP, SET_COL_ADDR_BITS, l_value, o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @note attr_si_engine_fields, ROW_ADDR_BITS specialization +/// +template<> +struct attrEngineTraits<attr_eff_engine_fields, ROW_ADDR_BITS> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DRAM_ROW_BITS_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DRAM_ROW_BITS_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_ROW_ADDR_BITS; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dram_row_bits(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dram_row_bits(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_efd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_ADDR_ROW_MAP = + { + {0b010, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM14}, + {0b011, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM15}, + {0b100, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM16}, + {0b101, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM17}, + {0b110, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM18}, + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_value = 0; + FAPI_TRY(i_spd_data.row_address_bits(l_value)) + + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_dimm, DRAM_ADDR_ROW_MAP, SET_ROW_ADDR_BITS, l_value, o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + // // SI parameters // @@ -1162,107 +1294,24 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->dram_dic(o_setting); - } -}; - -/// -/// @brief Traits for attr_engine -/// @class attrEngineTraits -/// @note attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE specialization -/// -template<> -struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE> -{ - using attr_type = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE_Type; - using attr_integral_type = std::remove_all_extents<attr_type>::type; - static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE_TargetType; - static constexpr generic_ffdc_codes FFDC_CODE = SET_SI_VREF_DQ_TRAIN_RANGE; - - /// - /// @brief attribute getter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return mss::attr::get_si_vref_dq_train_range(i_target, o_setting); - } - - /// - /// @brief attribute setter - /// @param[in] i_target the fapi2 target - /// @param[in] i_setting array to set - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& i_setting) - { - return mss::attr::set_si_vref_dq_train_range(i_target, i_setting); - } - - /// - /// @brief Computes setting for attribute - /// @param[in] i_efd_data EFD data - /// @param[out] o_setting value we want to set attr with - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, - attr_integral_type& o_setting) - { - return i_efd_data->wr_vref_dq_range(o_setting); - } -}; + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_DIC_MAP = + { + // {key byte, capacity in GBs} + {0, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_DISABLE}, + {1, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_OHM34}, + {2, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_OHM48}, + }; -/// -/// @brief Traits for attr_engine -/// @class attrEngineTraits -/// @note attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE specialization -/// -template<> -struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE> -{ - using attr_type = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE_Type; - using attr_integral_type = std::remove_all_extents<attr_type>::type; - static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE_TargetType; - static constexpr generic_ffdc_codes FFDC_CODE = SET_SI_VREF_DQ_TRAIN_VALUE; + const auto l_ocmb = i_efd_data->get_ocmb_target(); - /// - /// @brief attribute getter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return mss::attr::get_si_vref_dq_train_value(i_target, o_setting); - } + attr_integral_type l_dram_dic = 0; + FAPI_TRY(i_efd_data->dram_dic(l_dram_dic)) - /// - /// @brief attribute setter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return mss::attr::set_si_vref_dq_train_value(i_target, o_setting); - } + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, DRAM_DIC_MAP, SET_SI_DRAM_DRV_IMP_DQ_DQS, l_dram_dic, o_setting)); - /// - /// @brief Computes setting for attribute - /// @param[in] i_efd_data EFD data - /// @param[out] o_setting value we want to set attr with - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, - attr_integral_type& o_setting) - { - return i_efd_data->wr_vref_dq_value(o_setting); + fapi_try_exit: + return fapi2::current_err; } }; @@ -1627,6 +1676,78 @@ struct attrEngineTraits<attr_engine_derived_fields, MEM_DIMM_SIZE> } }; +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @note attr_engine_derived_fields, HEIGHT_3DS specialization +/// +template<> +struct attrEngineTraits<attr_engine_derived_fields, HEIGHT_3DS> +{ + using attr_type = fapi2::ATTR_MEM_3DS_HEIGHT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_3DS_HEIGHT_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_3DS_HEIGHT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_3ds_height(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_3ds_height(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + uint8_t l_master_ranks_per_dimm = 0; + uint8_t l_logical_ranks_per_dimm = 0; + + FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(i_target, l_master_ranks_per_dimm)); + FAPI_TRY(mss::attr::get_logical_ranks_per_dimm(i_target, l_logical_ranks_per_dimm)); + { + uint16_t l_result = l_logical_ranks_per_dimm / l_master_ranks_per_dimm; + + static const std::vector< std::pair<uint16_t, uint16_t> > HEIGHT_3DS_MAP = + { + // {key byte, device width (bits)} + {1, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_PLANAR}, + {2, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H2}, + {4, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H4}, + {8, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H8}, + // All others reserved + }; + + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(i_target, HEIGHT_3DS_MAP, mss::SET_3DS_HEIGHT, l_result, o_setting)); + } + fapi_try_exit: + return fapi2::current_err; + } +}; + }//mss #endif diff --git a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H index 813abbe33..911821b5f 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H @@ -98,9 +98,11 @@ enum attr_eff_engine_fields DRAM_DENSITY = 3, PRIMARY_DIE_COUNT = 4, PRIM_STACK_TYPE = 5, + COLUMN_ADDR_BITS = 6, + ROW_ADDR_BITS = 7, // Dispatcher set to last enum value - ATTR_EFF_DISPATCHER = PRIM_STACK_TYPE, + ATTR_EFF_DISPATCHER = ROW_ADDR_BITS, }; /// @@ -127,11 +129,9 @@ enum attr_si_engine_fields SI_DRAM_PREAMBLE = 13, SI_MC_DRV_EQ_DQ_DQS = 14, SI_DRAM_DRV_IMP_DQ_DQS = 15, - SI_VREF_DQ_TRAIN_RANGE = 16, - SI_VREF_DQ_TRAIN_VALUE = 17, - SI_ODT_WR = 18, - SI_ODT_RD = 19, - SI_GEARDOWN_MODE = 20, + SI_ODT_WR = 16, + SI_ODT_RD = 17, + SI_GEARDOWN_MODE = 18, // Dispatcher set to last enum value ATTR_SI_DISPATCHER = SI_GEARDOWN_MODE, @@ -154,7 +154,8 @@ enum attr_engine_derived_fields // Attrs to set MEM_DIMM_SIZE = 1, - LOGICAL_RANKS = 2, + HEIGHT_3DS = 2, // HEIGHT_3DS must be calculated after LOGICAL_RANKS + LOGICAL_RANKS = 3, // Dispatcher set to last enum value ATTR_DERIVED_DISPATCHER = LOGICAL_RANKS, diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index fd953e84e..ecc9af5ff 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -2138,6 +2138,52 @@ fapi_try_exit: } /// +/// @brief ATTR_MEM_3DS_HEIGHT getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint16_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Setting for 3DS stack. Calculated from logical_ranks / master_ranks +/// +inline fapi2::ReturnCode get_3ds_height(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint16_t& o_value) +{ + uint16_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_3DS_HEIGHT, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_3DS_HEIGHT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_3DS_HEIGHT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint16_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Setting for 3DS stack. Calculated from logical_ranks / master_ranks +/// +inline fapi2::ReturnCode get_3ds_height(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint16_t (&o_array)[2]) +{ + uint16_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_3DS_HEIGHT, i_target, l_value) ); + memcpy(o_array, &l_value, 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_3DS_HEIGHT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MEM_EFF_REGISTER_TYPE getter /// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value @@ -3288,100 +3334,6 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter -/// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) -{ - uint8_t l_value[2][4] = {}; - const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) -{ - uint8_t l_value[2][4] = {}; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter -/// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) -{ - uint8_t l_value[2][4] = {}; - const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) -{ - uint8_t l_value[2][4] = {}; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// /// @brief ATTR_MEM_SI_GEARDOWN_MODE getter /// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t&[] array reference to store the value diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H index cd904ef9b..213293fdd 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H @@ -489,26 +489,26 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b } /// - /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE + /// @brief Decodes Host RD VREF DQ -> INIT_PHY_VREF /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode wr_vref_dq_range(uint8_t& o_output) const override + virtual fapi2::ReturnCode init_phy_vref(uint8_t& o_output) const override { - FAPI_TRY(( reader<fields_t::WR_VREF_DQ_RANGE, R>(iv_target, iv_data, o_output)) ); + FAPI_TRY( (reader<fields_t::INIT_PHY_VREF, R>(iv_target, iv_data, o_output)) ); fapi_try_exit: return fapi2::current_err; } /// - /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT + /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const + virtual fapi2::ReturnCode wr_vref_dq_range(uint8_t& o_output) const override { - FAPI_TRY( (reader<fields_t::PHY_VREF_PERCENT, R>(iv_target, iv_data, o_output)) ); + FAPI_TRY(( reader<fields_t::WR_VREF_DQ_RANGE, R>(iv_target, iv_data, o_output)) ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H index d59aac75f..9a1415a75 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H @@ -244,16 +244,16 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> PHY_EQUALIZATION_LEN = 2, // Byte 44: Initial WR VREF DQ setting - WR_VREF_DQ_BYTE = 44, + INIT_VREF_DQ_BYTE = 44, WR_VREF_DQ_RANGE_START = 1, WR_VREF_DQ_RANGE_LEN = 1, WR_VREF_DQ_VALUE_START = 2, WR_VREF_DQ_VALUE_LEN = 6, // Byte 45: Host RD VREF DQ - RD_VREF_DQ_BYTE = 45, - PHY_VREF_PERCENT_START = 1, - PHY_VREF_PERCENT_LEN = 7, + INIT_PHY_VREF_BYTE = 45, + INIT_PHY_VREF_START = 1, + INIT_PHY_VREF_LEN = 7, // Byte 46: ODT WR Map CS Byte1 ODT_WR_MAP1_BYTE = 46, @@ -554,12 +554,12 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> // Byte 43: PHY Equalization static constexpr field_t PHY_EQUALIZATION{PHY_EQUALIZATION_BYTE, PHY_EQUALIZATION_START, PHY_EQUALIZATION_LEN}; - // Byte 44: Initial WR VREF DQ setting - static constexpr field_t WR_VREF_DQ_RANGE{WR_VREF_DQ_BYTE, WR_VREF_DQ_RANGE_START, WR_VREF_DQ_RANGE_LEN}; - static constexpr field_t WR_VREF_DQ_VALUE{WR_VREF_DQ_BYTE, WR_VREF_DQ_VALUE_START, WR_VREF_DQ_VALUE_LEN}; + // Byte 44: Initial VREF DQ setting + static constexpr field_t WR_VREF_DQ_RANGE{INIT_VREF_DQ_BYTE, WR_VREF_DQ_RANGE_START, WR_VREF_DQ_RANGE_LEN}; + static constexpr field_t WR_VREF_DQ_VALUE{INIT_VREF_DQ_BYTE, WR_VREF_DQ_VALUE_START, WR_VREF_DQ_VALUE_LEN}; - // Byte 45: Host RD VREF DQ - static constexpr field_t PHY_VREF_PERCENT{RD_VREF_DQ_BYTE, PHY_VREF_PERCENT_START, PHY_VREF_PERCENT_LEN}; + // Byte 45: Initial PHY VREF setting + static constexpr field_t INIT_PHY_VREF{INIT_PHY_VREF_BYTE, INIT_PHY_VREF_START, INIT_PHY_VREF_LEN}; // Byte 46: ODT WR Map CS Byte1 static constexpr field_t ODT_WR_MAP_RANK3{ODT_WR_MAP1_BYTE, ODT_WR_MAP_RANK3_START, ODT_WR_MAP_RANK3_LEN}; diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H index 784dba0f6..1acdc554d 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H @@ -784,7 +784,7 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS /// @note valid for all revs /// template< mss::spd::rev R > -class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::PHY_VREF_PERCENT, R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::INIT_PHY_VREF, R > { public: diff --git a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H index 8427b5b88..df0dbed5e 100644 --- a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H +++ b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H @@ -492,7 +492,7 @@ class base_decoder } /// - /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE + /// @brief Decodes Initial VREF DQ setting -> WR_VREF_DQ_RANGE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @@ -503,22 +503,22 @@ class base_decoder } /// - /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT + /// @brief Decodes Initial VREF DQ setting -> WR_VREF_DQ_VALUE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const + virtual fapi2::ReturnCode wr_vref_dq_value(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; } /// - /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_VALUE + /// @brief Decodes Initial PHY VREF -> INIT_PHY_VREF /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode wr_vref_dq_value(uint8_t& o_output) const + virtual fapi2::ReturnCode init_phy_vref(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index b77cbcd47..dd56562a4 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -220,6 +220,9 @@ enum generic_ffdc_codes SET_CAC_DELAY_B = 0x1077, EFD_CA_LATENCY_MODE = 0x1080, EFD_CA_PL_MODE = 0x1081, + SET_COL_ADDR_BITS = 0x1082, + SET_ROW_ADDR_BITS = 0x1083, + SET_3DS_HEIGHT = 0x1084, // Power thermal functions diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index 8e7b12bbf..3167e018a 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -187,6 +187,7 @@ </description> <initToZero></initToZero> <valueType>uint8</valueType> + <enum> NUM10 = 10</enum> <writeable/> <array>2</array> <mssAccessorName>dram_column_bits</mssAccessorName> @@ -588,6 +589,20 @@ <mssAccessorName>logical_ranks_per_dimm</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_3DS_HEIGHT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Setting for 3DS stack. Calculated from logical_ranks / master_ranks + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> + <array>2</array> + <writeable/> + <mssAccessorName>3ds_height</mssAccessorName> + </attribute> + <attribute> <id>ATTR_MEM_EFF_REGISTER_TYPE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index 1ec910f04..d8410a5a0 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -106,7 +106,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>OHM34 = 34, OHM48 = 48</enum> + <enum>DISABLE = 0, OHM34 = 34, OHM48 = 48</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_dram_drv_imp_dq_dqs</mssAccessorName> <array>2 4</array> @@ -179,35 +179,6 @@ </attribute> <attribute> - <id>ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][RANK] - vrefdq_train value. This is for DDR4 MRS6. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2 4</array> - <mssAccessorName>si_vref_dq_train_value</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][RANK] - vrefdq_train range. This is for DDR4 MRS6. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>RANGE1 = 0, RANGE2 = 1</enum> - <writeable/> - <array>2 4</array> - <mssAccessorName>si_vref_dq_train_range</mssAccessorName> - </attribute> - - <attribute> <id>ATTR_MEM_SI_GEARDOWN_MODE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> |
