diff options
Diffstat (limited to 'src/import/generic')
4 files changed, 1255 insertions, 3 deletions
diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index 96024c17e..d97816d47 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -101,6 +101,816 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel +/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none +/// +inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel +/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none +/// +inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from +/// 00 to 04. No need to calculate; User can override with desired experimental value. +/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0F, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0F: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from +/// 00 to 04. No need to calculate; User can override with desired experimental value. +/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0F, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0F: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CS_CMD_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CS_CMD_LATENCY, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CS_CMD_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CS_CMD_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CS_CMD_LATENCY, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CS_CMD_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CA_PARITY_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CA_PARITY_LATENCY, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CA_PARITY_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CA_PARITY_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CA_PARITY_LATENCY, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CA_PARITY_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC02 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. +/// No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC02, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC02: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC02 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. +/// No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC02, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC02: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC03 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC03, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC03: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC03 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC03, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC03: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC04 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value +/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC04, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC04: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC04 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value +/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC04, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC04: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC05 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate +/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble +/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC05, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC05: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC05 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate +/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble +/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC05, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC05: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0B getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User +/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0B, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0B: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0B getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User +/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0B, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0B: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC1X getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 +/// to 3F.No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC1X, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC1X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC1X getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 +/// to 3F.No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC1X, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC1X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC7X getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need +/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg +/// consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC7X, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC7X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC7X getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need +/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg +/// consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC7X, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC7X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F1RC00 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value +/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired +/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: +/// none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC00, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC00: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F1RC00 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value +/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired +/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: +/// none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC00, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC00: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_PSTATES getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Number of p-states used Always set NumPStates to 1 for Explorer. +/// +inline fapi2::ReturnCode get_pstates(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_PSTATES, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_PSTATES: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_BYTE_ENABLES getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint16_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Enable/Disable DBYTE macro (clock gating and IO tri-state) 10-bit bitmap Right aligned +/// +inline fapi2::ReturnCode get_byte_enables(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint16_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_BYTE_ENABLES, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_BYTE_ENABLES: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_NIBBLE_ENABLES getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Account/Ignore training/dfi_bist result on the selected nibble. 20-bit bitmap Right +/// aligned +/// +inline fapi2::ReturnCode get_nibble_enables(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint32_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_NIBBLE_ENABLES, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_NIBBLE_ENABLES: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_TAA_MIN getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Timing value used to calculate CAS Latency +/// +inline fapi2::ReturnCode get_taa_min(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_TAA_MIN, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_TAA_MIN: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_RANK_FOUR_MODE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note DIMM Rank 4 mode enable +/// +inline fapi2::ReturnCode get_rank4_mode(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_RANK_FOUR_MODE, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_RANK_FOUR_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_REORDER_QUEUE_SETTING getter @@ -489,7 +1299,7 @@ fapi_try_exit: /// @note ARRAY[DIMM] Column Address Bits. Decoded SPD Byte 5 (bits 2~0). Actual number of /// DRAM columns is 2^N, where N is the number of column address bits /// -inline fapi2::ReturnCode get_dram_columns_bits(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode get_dram_column_bits(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); @@ -513,7 +1323,7 @@ fapi_try_exit: /// @note ARRAY[DIMM] Column Address Bits. Decoded SPD Byte 5 (bits 2~0). Actual number of /// DRAM columns is 2^N, where N is the number of column address bits /// -inline fapi2::ReturnCode get_dram_columns_bits(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, +inline fapi2::ReturnCode get_dram_column_bits(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) { uint8_t l_value[2] = {}; @@ -1666,6 +2476,89 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_EFF_MRAM_SUPPORT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Supports MRAM or not +/// +inline fapi2::ReturnCode get_mram_support(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_MRAM_SUPPORT, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_MRAM_SUPPORT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_EFF_3DS_HEIGHT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM] Primary SDRAM Package Type. Decodes Byte 6. This byte defines the primary +/// set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = +/// 3DS +/// +inline fapi2::ReturnCode get_3ds_height(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_3DS_HEIGHT, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_3DS_HEIGHT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_EFF_DDP_COMPATIBLE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note DDP Compatibility +/// +inline fapi2::ReturnCode get_ddp_compatibility(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DDP_COMPATIBLE, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_DDP_COMPATIBLE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_EFF_TSV8H_SUPPORT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note TSVH8 Support +/// +inline fapi2::ReturnCode get_tsv8h_support(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_TSV8H_SUPPORT, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_TSV8H_SUPPORT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_EFF_VOLT_VDDR getter diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml index 9b5d3a271..d10983bdb 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml @@ -95,4 +95,306 @@ <array>72</array> </attribute> + <attribute> + <id>ATTR_MEM_GEARDOWN_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Gear Down Mode. + This is for DDR4 MRS3. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>HALF =0, QUARTER=1</enum> + <writeable/> + <array>2</array> + <mssAccessorName>geardown_mode</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0F</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0f</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_CS_CMD_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + CS to CMD/ADDR Latency. + This is for DDR4 MRS4. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>cs_cmd_latency</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_CA_PARITY_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + C/A Parity Latency Mode. This is for DDR4 MRS5. + Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>ca_parity_latency</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC02</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC02: Timing and IBT Control Word; Default value - 0x00. + Values Range from 0-8. No need to calculate; + User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc02</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC03</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC03 - CA and CS Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc03</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC04</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc04</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC05</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC05 - Clock Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc05</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0B</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0b</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC1X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc1x</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC7X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc7x</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC00</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc00</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_VREF_DQ_TRAIN_VALUE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + vrefdq_train value. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array> 2 4</array> + <mssAccessorName>vref_dq_train_value</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_VREF_DQ_TRAIN_RANGE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + vrefdq_train range. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>RANGE1 = 0, RANGE2 = 1</enum> + <writeable/> + <array> 2 4</array> + <mssAccessorName>vref_dq_train_range</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_PSTATES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Number of p-states used + Always set NumPStates to 1 for Explorer. + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>pstates</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_BYTE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Enable/Disable DBYTE macro (clock gating and IO tri-state) + 10-bit bitmap + Right aligned + </description> + <valueType>uint16</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>byte_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_NIBBLE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Account/Ignore training/dfi_bist result on the selected nibble. + 20-bit bitmap + Right aligned + </description> + <valueType>uint32</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>nibble_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_TAA_MIN</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Timing value used to calculate CAS Latency + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nck</mssUnits> + <mssAccessorName>taa_min</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_RANK_FOUR_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DIMM Rank 4 mode enable + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>rank4_mode</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index c94dc98fe..b34019c60 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -172,7 +172,7 @@ <valueType>uint8</valueType> <writeable/> <array>2</array> - <mssAccessorName>dram_columns_bits</mssAccessorName> + <mssAccessorName>dram_column_bits</mssAccessorName> </attribute> <attribute> @@ -787,4 +787,60 @@ <mssAccessorName>volt_vpp</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_EFF_MRAM_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Supports MRAM or not + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>NORMAL = 0, EVERSPIN = 1</enum> + <writeable/> + <mssAccessorName>mram_support</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_3DS_HEIGHT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Primary SDRAM Package Type. + Decodes Byte 6. + This byte defines the primary set of SDRAMs. + Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> + <writeable/> + <mssAccessorName>3ds_height</mssAccessorName> + </attribute> + +<attribute> + <id>ATTR_MEM_EFF_DDP_COMPATIBLE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DDP Compatibility + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <mssAccessorName>ddp_compatibility</mssAccessorName> + </attribute> + +<attribute> + <id>ATTR_MEM_EFF_TSV8H_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + TSVH8 Support + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <mssAccessorName>tsv8h_support</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index df5194424..008a90974 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -122,6 +122,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> + <enum>READ_PREAMBLE_BIT = 3, WRITE_PREAMBLE_BIT = 7</enum> <mssUnits>nCK</mssUnits> <mssAccessorName>si_dram_preamble</mssAccessorName> </attribute> |
