diff options
Diffstat (limited to 'src/import/generic')
3 files changed, 381 insertions, 359 deletions
diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml index 348764642..d10983bdb 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml @@ -82,8 +82,7 @@ <id>ATTR_MEM_VPD_DQ_MAP</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - ARRAY[Dimm DQ PIN] - The map from the Dual Inline Memory Module + [Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout </description> <initToZero></initToZero> @@ -96,246 +95,306 @@ <array>72</array> </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC0F</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F0RC0F - Command Latency Adder Control Word; - Default value - 04. Values Range from 00 to 04. - No need to calculate; User can override with desired experimental value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc0f</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_GEARDOWN_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Gear Down Mode. + This is for DDR4 MRS3. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>HALF =0, QUARTER=1</enum> + <writeable/> + <array>2</array> + <mssAccessorName>geardown_mode</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_CS_CMD_LATENCY</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - CS to CMD/ADDR Latency. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> - <writeable/> - <array>2</array> - <mssAccessorName>cs_cmd_latency</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0F</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0f</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_CA_PARITY_LATENCY</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - C/A Parity Latency Mode. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum> - <writeable/> - <array>2</array> - <mssAccessorName>ca_parity_latency</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_CS_CMD_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + CS to CMD/ADDR Latency. + This is for DDR4 MRS4. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>cs_cmd_latency</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC02</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F0RC02: Timing and IBT Control Word; Default value - 0x00. - Values Range from 0-8. No need to calculate; - User can override with desired experimental value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc02</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_CA_PARITY_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + C/A Parity Latency Mode. This is for DDR4 MRS5. + Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>ca_parity_latency</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC03</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F0RC03 - CA and CS Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. - Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc03</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC02</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC02: Timing and IBT Control Word; Default value - 0x00. + Values Range from 0-8. No need to calculate; + User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc02</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC04</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). - Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc04</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC03</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC03 - CA and CS Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc03</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC05</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F0RC05 - Clock Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). - Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc05</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC04</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc04</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC0B</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Operating Voltage VDD and VrefCA Source Control Word; - Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. - No need to calculate; User can override with desired experimental value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc0b</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC05</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC05 - Clock Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc05</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC1X</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F0RC1x - Internal VrefCA Control Word; - Default value - 00. Values Range from 00 to 3F. - No need to calculate; User can override with desired experimental value. - </description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0B</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc1x</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0b</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC7X</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F0RC7x: IBT Control Word; - Default value - 00. Values Range from 00 to FF.No need to calculate. - User can override with desired experimental value. - </description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC1X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc7x</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc1x</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F1RC00</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word; - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - </description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC7X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f1rc00</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc7x</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F1RC02</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word; - Default value - 00. Values Range from 00 to 0F. No need to calculate; - User can override with desired experimental value. - </description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC00</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f1rc02</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc00</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F1RC03</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word. - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f1rc03</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_VREF_DQ_TRAIN_VALUE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + vrefdq_train value. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array> 2 4</array> + <mssAccessorName>vref_dq_train_value</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F1RC04</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word; - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f1rc04</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_VREF_DQ_TRAIN_RANGE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + vrefdq_train range. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>RANGE1 = 0, RANGE2 = 1</enum> + <writeable/> + <array> 2 4</array> + <mssAccessorName>vref_dq_train_range</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F1RC05</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word. - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f1rc05</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_PSTATES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Number of p-states used + Always set NumPStates to 1 for Explorer. + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>pstates</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_BYTE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Enable/Disable DBYTE macro (clock gating and IO tri-state) + 10-bit bitmap + Right aligned + </description> + <valueType>uint16</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>byte_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_NIBBLE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Account/Ignore training/dfi_bist result on the selected nibble. + 20-bit bitmap + Right aligned + </description> + <valueType>uint32</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>nibble_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_TAA_MIN</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Timing value used to calculate CAS Latency + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nck</mssUnits> + <mssAccessorName>taa_min</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_RANK_FOUR_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DIMM Rank 4 mode enable + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>rank4_mode</mssAccessorName> + </attribute> </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index cec393f11..b34019c60 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -787,4 +787,60 @@ <mssAccessorName>volt_vpp</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_EFF_MRAM_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Supports MRAM or not + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>NORMAL = 0, EVERSPIN = 1</enum> + <writeable/> + <mssAccessorName>mram_support</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_3DS_HEIGHT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Primary SDRAM Package Type. + Decodes Byte 6. + This byte defines the primary set of SDRAMs. + Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> + <writeable/> + <mssAccessorName>3ds_height</mssAccessorName> + </attribute> + +<attribute> + <id>ATTR_MEM_EFF_DDP_COMPATIBLE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DDP Compatibility + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <mssAccessorName>ddp_compatibility</mssAccessorName> + </attribute> + +<attribute> + <id>ATTR_MEM_EFF_TSV8H_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + TSVH8 Support + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <mssAccessorName>tsv8h_support</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index 819336678..008a90974 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -100,8 +100,7 @@ <id>ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - DQ and DQS Drive Impedance. + Array[DIMM][RANK] DQ and DQS Drive Impedance. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -116,10 +115,9 @@ <id>ATTR_MEM_SI_DRAM_PREAMBLE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. - The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. - E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE + Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. + The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. + E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -127,15 +125,13 @@ <enum>READ_PREAMBLE_BIT = 3, WRITE_PREAMBLE_BIT = 7</enum> <mssUnits>nCK</mssUnits> <mssAccessorName>si_dram_preamble</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_DRAM_RTT_NOM</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - DRAM side Nominal Termination Resistance in Ohms. + Array[DIMM][RANK] DRAM side Nominal Termination Resistance in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -150,8 +146,7 @@ <id>ATTR_MEM_SI_DRAM_RTT_PARK</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - DRAM side Park Termination Resistance in Ohms. + Array[DIMM][RANK] DRAM side Park Termination Resistance in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -166,8 +161,7 @@ <id>ATTR_MEM_SI_DRAM_RTT_WR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - DRAM side Write Termination Resistance in Ohms. + Array[DIMM][RANK] DRAM side Write Termination Resistance in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -179,101 +173,23 @@ </attribute> <attribute> - <id>ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][RANK] - vrefdq_train value. This is for DDR4 MRS6. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2 4</array> - <mssAccessorName>si_vref_dq_train_value</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][RANK] - vrefdq_train range. This is for DDR4 MRS6. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>RANGE1 = 0, RANGE2 = 1</enum> - <writeable/> - <array>2 4</array> - <mssAccessorName>si_vref_dq_train_range</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_SI_GEARDOWN_MODE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][RANK] - Gear Down Mode. - This is for DDR4 MRS3. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>HALF =0, QUARTER=1</enum> - <writeable/> - <array>2 4</array> - <mssAccessorName>si_geardown_mode</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_SI_MC_DRV_DQ_DQS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Array[DIMM][RANK] - Tx drive impedance for DQ/DQS of all ranks in ohms - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssAccessorName>si_mc_drv_dq_dqs</mssAccessorName> - <array>2 4</array> - </attribute> - - <attribute> - <id>ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Array[DIMM][RANK] - Memory Controller side Receiver Equalization for Data and Data Strobe Lines. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <enum>DISABLE = 0, ENABLE = 1</enum> - <mssAccessorName>si_mc_rcv_eq_dq_dqs</mssAccessorName> - <array>2 4</array> - </attribute> - - <attribute> <id>ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Equalization for Data and Data Strobe Lines. + Memory Controller side Drive Equalization for Data and Data Strobe Lines. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> <enum>DISABLE = 0, FFE = 1</enum> <mssAccessorName>si_mc_drv_eq_dq_dqs</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CLK</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Clock in Ohms. + Memory Controller side Drive Impedance for Clock in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -281,15 +197,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_clk</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. + Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -297,15 +211,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_cmd_addr</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CNTL</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. + Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -313,15 +225,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_cntl</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CSCID</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. + Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -329,15 +239,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_cscid</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -345,15 +253,14 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_dq_dqs_pull_down</mssAccessorName> - <array>2 4</array> + <array>1</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -361,15 +268,14 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_dq_dqs_pull_up</mssAccessorName> - <array>2 4</array> + <array>1</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Clock in Ohms. + Memory Controller side Drive Slew Rate for Clock in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -377,15 +283,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_clk</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and Activate Lines in Ohms. + Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and Activate Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -393,15 +297,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_cmd_addr</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset Lines in Ohms. + Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -409,15 +311,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_cntl</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. + Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -425,15 +325,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_cscid</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -441,7 +339,20 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_dq_dqs</mssAccessorName> - <array>2 4</array> + <array>1</array> + </attribute> + + <attribute> + <id>ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Memory Controller side Receiver Equalization for Data and Data Strobe Lines. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <enum>DISABLE = 0, DFE = 1</enum> + <mssAccessorName>si_mc_rcv_eq_dq_dqs</mssAccessorName> </attribute> <attribute> @@ -456,15 +367,13 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_rcv_imp_alert_n</mssAccessorName> - <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - Memory Controller side Receiver Impedance. Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Receiver Impedance. Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -472,16 +381,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_rcv_imp_dq_dqs</mssAccessorName> - <array>2 4</array> + <array>1</array> </attribute> <attribute> <id>ATTR_MEM_SI_ODT_RD</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. - The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Array[DIMM][RANK] READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -494,9 +402,8 @@ <id>ATTR_MEM_SI_ODT_WR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] - WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. - The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Array[DIMM][RANK] WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] </description> <initToZero></initToZero> <valueType>uint8</valueType> |