diff options
Diffstat (limited to 'src/import/generic/memory/lib/utils')
-rw-r--r-- | src/import/generic/memory/lib/utils/mc/gen_mss_port.H | 29 | ||||
-rw-r--r-- | src/import/generic/memory/lib/utils/mcbist/gen_mss_memdiags.H | 84 |
2 files changed, 83 insertions, 30 deletions
diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H index 435d93a50..6c4b4d4b1 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H @@ -464,6 +464,19 @@ fapi_try_exit: } /// +/// @brief Set up memory controller specific settings for ECC registers (at the end of draminit_mc) +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in,out] io_data contents of RECR register +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode ecc_reg_settings_draminit_mc( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data ); + +/// /// @brief Enable Read ECC checking /// @tparam MC the memory controller type /// @tparam T the fapi2 target type of the target @@ -471,9 +484,11 @@ fapi_try_exit: /// @param[in] i_target the target /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits<MC> > +template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC> > fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target ) { + constexpr uint8_t RECR_MBSECCQ_DATA_INVERSION_NO_INVERSION = 0b00; + constexpr uint8_t RECR_MBSECCQ_DATA_INVERSION_INVERT_DATA_TOGGLE_CHECKS = 0b11; fapi2::buffer<uint64_t> l_data; uint8_t l_sim = 0; @@ -487,13 +502,17 @@ fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target ) // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything) // so we can't run with address checking. Disable address checking in sim. - l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? 0 : 1); + l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? mss::states::LOW : mss::states::HIGH); - // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented - // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but + // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented + // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC - l_data.insertFromRight<TT::RECR_MBSECCQ_DATA_INVERSION, TT::RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? 0b00 : 0b11); + l_data.insertFromRight<TT::RECR_MBSECCQ_DATA_INVERSION, TT::RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? + RECR_MBSECCQ_DATA_INVERSION_NO_INVERSION : + RECR_MBSECCQ_DATA_INVERSION_INVERT_DATA_TOGGLE_CHECKS); + + FAPI_TRY( ecc_reg_settings_draminit_mc<MC>(i_target, l_data) ); // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. diff --git a/src/import/generic/memory/lib/utils/mcbist/gen_mss_memdiags.H b/src/import/generic/memory/lib/utils/mcbist/gen_mss_memdiags.H index efd2e9bd9..c67b51595 100644 --- a/src/import/generic/memory/lib/utils/mcbist/gen_mss_memdiags.H +++ b/src/import/generic/memory/lib/utils/mcbist/gen_mss_memdiags.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -237,6 +237,28 @@ using mss::mcbist::LAST_PATTERN; using mss::mcbist::NO_PATTERN; /// +/// @brief Set up memory controller specific settings for pre-maint mode read +/// @tparam MC the mc type of the T +/// @tparam T the fapi2::TargetType - derived +/// @tparam TT the portTraits associated with the port +/// @param[in] i_target the memory controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// +template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode pre_maint_read_settings( const fapi2::Target<T>& i_target ); + +/// +/// @brief Set up memory controller specific settings for pre-scrub +/// @tparam MC the mc type of the T +/// @tparam T the fapi2::TargetType - derived +/// @tparam TT the portTraits associated with the port +/// @param[in] i_target the memory controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// +template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode pre_scrub_settings( const fapi2::Target<T>& i_target ); + +/// /// @brief Stop the current command /// @tparam MC the mc type of the T /// @tparam T the fapi2::TargetType of the target @@ -919,7 +941,7 @@ fapi_try_exit: /// @note The function is asynchronous, and the caller should be looking for a done attention /// @note The address is often the port, dimm, rank but this is not enforced in the API. /// -template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T = mss::mcbistMCTraits<MC>::MC_TARGET_TYPE , typename TT = mcbistTraits<MC, T> > +template< mss::mc_type MC, fapi2::TargetType T = mss::mcbistMCTraits<MC>::MC_TARGET_TYPE , typename TT = mcbistTraits<MC, T> > fapi2::ReturnCode sf_read( const fapi2::Target<T>& i_target, const stop_conditions<MC>& i_stop, const mss::mcbist::address& i_address = mss::mcbist::address(), @@ -929,15 +951,19 @@ fapi2::ReturnCode sf_read( const fapi2::Target<T>& i_target, using ET = mss::mcbistMCTraits<MC>; FAPI_INF("superfast read - start for %s", mss::c_str(i_target)); - fapi2::ReturnCode l_rc; - constraints<MC> l_const(i_stop, speed::LUDICROUS, i_end, i_address, i_end_address); - sf_read_operation<MC> l_read_op(i_target, l_const, l_rc); + FAPI_TRY( pre_maint_read_settings<MC>(i_target) ); - FAPI_ASSERT( l_rc == fapi2::FAPI2_RC_SUCCESS, - ET::memdiags_sf_init_failed_init().set_MC_TARGET(i_target), - "Unable to initialize the MCBIST engine for a sf read %s", mss::c_str(i_target) ); + { + fapi2::ReturnCode l_rc; + constraints<MC> l_const(i_stop, speed::LUDICROUS, i_end, i_address, i_end_address); + sf_read_operation<MC> l_read_op(i_target, l_const, l_rc); - return l_read_op.execute(); + FAPI_ASSERT( l_rc == fapi2::FAPI2_RC_SUCCESS, + ET::memdiags_sf_init_failed_init().set_MC_TARGET(i_target), + "Unable to initialize the MCBIST engine for a sf read %s", mss::c_str(i_target) ); + + return l_read_op.execute(); + } fapi_try_exit: return fapi2::current_err; @@ -956,7 +982,7 @@ fapi_try_exit: /// @note The function is asynchronous, and the caller should be looking for a done attention /// @note The address is often the port, dimm, rank but this is not enforced in the API. /// -template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T > +template< mss::mc_type MC, fapi2::TargetType T > fapi2::ReturnCode background_scrub( const fapi2::Target<T>& i_target, const stop_conditions<MC>& i_stop, const speed i_speed, @@ -965,15 +991,19 @@ fapi2::ReturnCode background_scrub( const fapi2::Target<T>& i_target, using ET = mss::mcbistMCTraits<MC>; FAPI_INF("continuous (background) scrub for %s", mss::c_str(i_target)); - fapi2::ReturnCode l_rc; - constraints<MC> l_const(i_stop, i_speed, end_boundary::STOP_AFTER_ADDRESS, i_address); - continuous_scrub_operation<MC> l_op(i_target, l_const, l_rc); + FAPI_TRY( pre_scrub_settings<MC>(i_target) ); + + { + fapi2::ReturnCode l_rc; + constraints<MC> l_const(i_stop, i_speed, end_boundary::STOP_AFTER_ADDRESS, i_address); + continuous_scrub_operation<MC> l_op(i_target, l_const, l_rc); - FAPI_ASSERT( l_rc == fapi2::FAPI2_RC_SUCCESS, - ET::memdiags_continuous_scrub_failed_init().set_MC_TARGET(i_target), - "Unable to initialize the MCBIST engine for a continuous scrub %s", mss::c_str(i_target) ); + FAPI_ASSERT( l_rc == fapi2::FAPI2_RC_SUCCESS, + ET::memdiags_continuous_scrub_failed_init().set_MC_TARGET(i_target), + "Unable to initialize the MCBIST engine for a continuous scrub %s", mss::c_str(i_target) ); - return l_op.execute(); + return l_op.execute(); + } fapi_try_exit: return fapi2::current_err; @@ -994,7 +1024,7 @@ fapi_try_exit: /// @note The function is asynchronous, and the caller should be looking for a done attention /// @note The address is often the port, dimm, rank but this is not enforced in the API. /// -template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T > +template< mss::mc_type MC, fapi2::TargetType T > fapi2::ReturnCode targeted_scrub( const fapi2::Target<T>& i_target, const stop_conditions<MC>& i_stop, const mss::mcbist::address& i_start_address, @@ -1004,15 +1034,19 @@ fapi2::ReturnCode targeted_scrub( const fapi2::Target<T>& i_target, using ET = mss::mcbistMCTraits<MC>; FAPI_INF("targeted scrub for %s", mss::c_str(i_target)); - fapi2::ReturnCode l_rc; - constraints<MC> l_const(i_stop, speed::LUDICROUS, i_end, i_start_address, i_end_address); - targeted_scrub_operation<MC> l_op(i_target, l_const, l_rc); + FAPI_TRY( pre_scrub_settings<MC>(i_target) ); + + { + fapi2::ReturnCode l_rc; + constraints<MC> l_const(i_stop, speed::LUDICROUS, i_end, i_start_address, i_end_address); + targeted_scrub_operation<MC> l_op(i_target, l_const, l_rc); - FAPI_ASSERT( l_rc == fapi2::FAPI2_RC_SUCCESS, - ET::memdiags_targeted_scrub_failed_init().set_MC_TARGET(i_target), - "Unable to initialize the MCBIST engine for a targeted scrub %s", mss::c_str(i_target) ); + FAPI_ASSERT( l_rc == fapi2::FAPI2_RC_SUCCESS, + ET::memdiags_targeted_scrub_failed_init().set_MC_TARGET(i_target), + "Unable to initialize the MCBIST engine for a targeted scrub %s", mss::c_str(i_target) ); - return l_op.execute(); + return l_op.execute(); + } fapi_try_exit: return fapi2::current_err; |