diff options
Diffstat (limited to 'src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H')
| -rw-r--r-- | src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H | 96 |
1 files changed, 48 insertions, 48 deletions
diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H index 47f0e5105..d59aac75f 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H @@ -385,59 +385,59 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> // Byte 70: PMIC0 SWA Volt PMIC0_SWA_BYTE = 70, - PMIC0_SWA_SETTING_START = 0, - PMIC0_SWA_SETTING_LEN = 7, - PMIC0_SWA_RANGE_START = 7, - PMIC0_SWA_RANGE_LEN = 1, + PMIC0_SWA_OFFSET_START = 0, + PMIC0_SWA_OFFSET_LEN = 7, + PMIC0_SWA_OFFSET_DIRECTION_START = 7, + PMIC0_SWA_OFFSET_DIRECTION_LEN = 1, // Byte 71: PMIC0 SWB Volt PMIC0_SWB_BYTE = 71, - PMIC0_SWB_SETTING_START = 0, - PMIC0_SWB_SETTING_LEN = 7, - PMIC0_SWB_RANGE_START = 7, - PMIC0_SWB_RANGE_LEN = 1, + PMIC0_SWB_OFFSET_START = 0, + PMIC0_SWB_OFFSET_LEN = 7, + PMIC0_SWB_OFFSET_DIRECTION_START = 7, + PMIC0_SWB_OFFSET_DIRECTION_LEN = 1, // Byte 72: PMIC0 SWC Volt PMIC0_SWC_BYTE = 72, - PMIC0_SWC_SETTING_START = 0, - PMIC0_SWC_SETTING_LEN = 7, - PMIC0_SWC_RANGE_START = 7, - PMIC0_SWC_RANGE_LEN = 1, + PMIC0_SWC_OFFSET_START = 0, + PMIC0_SWC_OFFSET_LEN = 7, + PMIC0_SWC_OFFSET_DIRECTION_START = 7, + PMIC0_SWC_OFFSET_DIRECTION_LEN = 1, // Byte 73: PMIC0 SWD Volt PMIC0_SWD_BYTE = 73, - PMIC0_SWD_SETTING_START = 0, - PMIC0_SWD_SETTING_LEN = 7, - PMIC0_SWD_RANGE_START = 7, - PMIC0_SWD_RANGE_LEN = 1, + PMIC0_SWD_OFFSET_START = 0, + PMIC0_SWD_OFFSET_LEN = 7, + PMIC0_SWD_OFFSET_DIRECTION_START = 7, + PMIC0_SWD_OFFSET_DIRECTION_LEN = 1, // Byte 74: PMIC1 SWA Volt PMIC1_SWA_BYTE = 74, - PMIC1_SWA_SETTING_START = 0, - PMIC1_SWA_SETTING_LEN = 7, - PMIC1_SWA_RANGE_START = 7, - PMIC1_SWA_RANGE_LEN = 1, + PMIC1_SWA_OFFSET_START = 0, + PMIC1_SWA_OFFSET_LEN = 7, + PMIC1_SWA_OFFSET_DIRECTION_START = 7, + PMIC1_SWA_OFFSET_DIRECTION_LEN = 1, // Byte 75: PMIC1 SWB Volt PMIC1_SWB_BYTE = 75, - PMIC1_SWB_SETTING_START = 0, - PMIC1_SWB_SETTING_LEN = 7, - PMIC1_SWB_RANGE_START = 7, - PMIC1_SWB_RANGE_LEN = 1, + PMIC1_SWB_OFFSET_START = 0, + PMIC1_SWB_OFFSET_LEN = 7, + PMIC1_SWB_OFFSET_DIRECTION_START = 7, + PMIC1_SWB_OFFSET_DIRECTION_LEN = 1, // Byte 76: PMIC1 SWC Volt PMIC1_SWC_BYTE = 76, - PMIC1_SWC_SETTING_START = 0, - PMIC1_SWC_SETTING_LEN = 7, - PMIC1_SWC_RANGE_START = 7, - PMIC1_SWC_RANGE_LEN = 1, + PMIC1_SWC_OFFSET_START = 0, + PMIC1_SWC_OFFSET_LEN = 7, + PMIC1_SWC_OFFSET_DIRECTION_START = 7, + PMIC1_SWC_OFFSET_DIRECTION_LEN = 1, // Byte 77: PMIC1 SWD Volt PMIC1_SWD_BYTE = 77, - PMIC1_SWD_SETTING_START = 0, - PMIC1_SWD_SETTING_LEN = 7, - PMIC1_SWD_RANGE_START = 7, - PMIC1_SWD_RANGE_LEN = 1, + PMIC1_SWD_OFFSET_START = 0, + PMIC1_SWD_OFFSET_LEN = 7, + PMIC1_SWD_OFFSET_DIRECTION_START = 7, + PMIC1_SWD_OFFSET_DIRECTION_LEN = 1, }; public: @@ -638,36 +638,36 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> static constexpr field_t CAC_DLY_B_7{CAC_DELAY_B_SIDE_GROUP_7_BYTE, CAC_DLY_B_7_START, CAC_DLY_B_7_LEN}; // Byte 70: PMIC0 SWA Volt - static constexpr field_t PMIC0_SWA_SETTING{PMIC0_SWA_BYTE, PMIC0_SWA_SETTING_START, PMIC0_SWA_SETTING_LEN}; - static constexpr field_t PMIC0_SWA_RANGE{PMIC0_SWA_BYTE, PMIC0_SWA_RANGE_START, PMIC0_SWA_RANGE_LEN}; + static constexpr field_t PMIC0_SWA_OFFSET{PMIC0_SWA_BYTE, PMIC0_SWA_OFFSET_START, PMIC0_SWA_OFFSET_LEN}; + static constexpr field_t PMIC0_SWA_OFFSET_DIRECTION{PMIC0_SWA_BYTE, PMIC0_SWA_OFFSET_DIRECTION_START, PMIC0_SWA_OFFSET_DIRECTION_LEN}; // Byte 71: PMIC0 SWB Volt - static constexpr field_t PMIC0_SWB_SETTING{PMIC0_SWB_BYTE, PMIC0_SWB_SETTING_START, PMIC0_SWB_SETTING_LEN}; - static constexpr field_t PMIC0_SWB_RANGE{PMIC0_SWB_BYTE, PMIC0_SWB_RANGE_START, PMIC0_SWB_RANGE_LEN}; + static constexpr field_t PMIC0_SWB_OFFSET{PMIC0_SWB_BYTE, PMIC0_SWB_OFFSET_START, PMIC0_SWB_OFFSET_LEN}; + static constexpr field_t PMIC0_SWB_OFFSET_DIRECTION{PMIC0_SWB_BYTE, PMIC0_SWB_OFFSET_DIRECTION_START, PMIC0_SWB_OFFSET_DIRECTION_LEN}; // Byte 72: PMIC0 SWC Volt - static constexpr field_t PMIC0_SWC_SETTING{PMIC0_SWC_BYTE, PMIC0_SWC_SETTING_START, PMIC0_SWC_SETTING_LEN}; - static constexpr field_t PMIC0_SWC_RANGE{PMIC0_SWC_BYTE, PMIC0_SWC_RANGE_START, PMIC0_SWC_RANGE_LEN}; + static constexpr field_t PMIC0_SWC_OFFSET{PMIC0_SWC_BYTE, PMIC0_SWC_OFFSET_START, PMIC0_SWC_OFFSET_LEN}; + static constexpr field_t PMIC0_SWC_OFFSET_DIRECTION{PMIC0_SWC_BYTE, PMIC0_SWC_OFFSET_DIRECTION_START, PMIC0_SWC_OFFSET_DIRECTION_LEN}; // Byte 73: PMIC0 SWD Volt - static constexpr field_t PMIC0_SWD_SETTING{PMIC0_SWD_BYTE, PMIC0_SWD_SETTING_START, PMIC0_SWD_SETTING_LEN}; - static constexpr field_t PMIC0_SWD_RANGE{PMIC0_SWD_BYTE, PMIC0_SWD_RANGE_START, PMIC0_SWD_RANGE_LEN}; + static constexpr field_t PMIC0_SWD_OFFSET{PMIC0_SWD_BYTE, PMIC0_SWD_OFFSET_START, PMIC0_SWD_OFFSET_LEN}; + static constexpr field_t PMIC0_SWD_OFFSET_DIRECTION{PMIC0_SWD_BYTE, PMIC0_SWD_OFFSET_DIRECTION_START, PMIC0_SWD_OFFSET_DIRECTION_LEN}; // Byte 74: PMIC1 SWA Volt - static constexpr field_t PMIC1_SWA_SETTING{PMIC1_SWA_BYTE, PMIC1_SWA_SETTING_START, PMIC1_SWA_SETTING_LEN}; - static constexpr field_t PMIC1_SWA_RANGE{PMIC1_SWA_BYTE, PMIC1_SWA_RANGE_START, PMIC1_SWA_RANGE_LEN}; + static constexpr field_t PMIC1_SWA_OFFSET{PMIC1_SWA_BYTE, PMIC1_SWA_OFFSET_START, PMIC1_SWA_OFFSET_LEN}; + static constexpr field_t PMIC1_SWA_OFFSET_DIRECTION{PMIC1_SWA_BYTE, PMIC1_SWA_OFFSET_DIRECTION_START, PMIC1_SWA_OFFSET_DIRECTION_LEN}; // Byte 75: PMIC1 SWB Volt - static constexpr field_t PMIC1_SWB_SETTING{PMIC1_SWB_BYTE, PMIC1_SWB_SETTING_START, PMIC1_SWB_SETTING_LEN}; - static constexpr field_t PMIC1_SWB_RANGE{PMIC1_SWB_BYTE, PMIC1_SWB_RANGE_START, PMIC1_SWB_RANGE_LEN}; + static constexpr field_t PMIC1_SWB_OFFSET{PMIC1_SWB_BYTE, PMIC1_SWB_OFFSET_START, PMIC1_SWB_OFFSET_LEN}; + static constexpr field_t PMIC1_SWB_OFFSET_DIRECTION{PMIC1_SWB_BYTE, PMIC1_SWB_OFFSET_DIRECTION_START, PMIC1_SWB_OFFSET_DIRECTION_LEN}; // Byte 76: PMIC1 SWC Volt - static constexpr field_t PMIC1_SWC_SETTING{PMIC1_SWC_BYTE, PMIC1_SWC_SETTING_START, PMIC1_SWC_SETTING_LEN}; - static constexpr field_t PMIC1_SWC_RANGE{PMIC1_SWC_BYTE, PMIC1_SWC_RANGE_START, PMIC1_SWC_RANGE_LEN}; + static constexpr field_t PMIC1_SWC_OFFSET{PMIC1_SWC_BYTE, PMIC1_SWC_OFFSET_START, PMIC1_SWC_OFFSET_LEN}; + static constexpr field_t PMIC1_SWC_OFFSET_DIRECTION{PMIC1_SWC_BYTE, PMIC1_SWC_OFFSET_DIRECTION_START, PMIC1_SWC_OFFSET_DIRECTION_LEN}; // Byte 77: PMIC1 SWD Volt - static constexpr field_t PMIC1_SWD_SETTING{PMIC1_SWD_BYTE, PMIC1_SWD_SETTING_START, PMIC1_SWD_SETTING_LEN}; - static constexpr field_t PMIC1_SWD_RANGE{PMIC1_SWD_BYTE, PMIC1_SWD_RANGE_START, PMIC1_SWD_RANGE_LEN}; + static constexpr field_t PMIC1_SWD_OFFSET{PMIC1_SWD_BYTE, PMIC1_SWD_OFFSET_START, PMIC1_SWD_OFFSET_LEN}; + static constexpr field_t PMIC1_SWD_OFFSET_DIRECTION{PMIC1_SWD_BYTE, PMIC1_SWD_OFFSET_DIRECTION_START, PMIC1_SWD_OFFSET_DIRECTION_LEN}; }; } // ns efd |
