diff options
Diffstat (limited to 'src/import/chips')
5 files changed, 122 insertions, 77 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index f0d5da547..cc13bb9d5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -79,43 +79,45 @@ fapi_try_exit: } /// -/// @brief perform the zctl toggle process +/// @brief Perform the zctl enable process /// @param[in] i_target the mcbist for the reset recover /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode toggle_zctl( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +fapi2::ReturnCode enable_zctl( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { -// With model 31 (Drop X) this became unecessary. Not removing it as it's unclear what -// the final algorithm(s) will be. BRS -#if 0 fapi2::buffer<uint64_t> l_data; - const auto l_ports = mss::find_targets<TARGET_TYPE_MCA>(i_target); + constexpr uint64_t l_zcal_reset_reg = pcTraits<TARGET_TYPE_MCA>::PC_RESETS_REG; - // - // 4. Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset and enable the internal impedance controller. - // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) - FAPI_DBG("Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset"); - l_data.setBit<59>(); - FAPI_TRY( mss::scom_blastah(l_ports, MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0, l_data) ); + uint8_t is_sim = 0; - // - // 5. Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset while impedance controller is still enabled. - // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) - FAPI_DBG("Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset."); - l_data.setBit<59>().setBit<60>(); - FAPI_TRY( mss::scom_blastah(l_ports, MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0, l_data) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<TARGET_TYPE_SYSTEM>(), is_sim) ); - // - // 6. Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller. - // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) + if (is_sim) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + // 11. Assert the ZCNTL enable to the internal impedance controller in DDRPHY_PC_RESETS register + mss::pc::set_enable_zcal(l_data, mss::HIGH); + FAPI_TRY( mss::scom_blastah(l_ports, l_zcal_reset_reg, l_data) ); + + // 12. Wait at least 1024 dphy_gckn cycles + fapi2::delay(mss::cycles_to_ns(i_target, 1024), mss::cycles_to_simcycles(1024)); + + // 13. Deassert the ZCNTL impedance controller enable, Check for DONE in DDRPHY_PC_DLL_ZCAL + mss::pc::set_enable_zcal(l_data, mss::LOW); + FAPI_TRY( mss::scom_blastah(l_ports, l_zcal_reset_reg, l_data) ); - FAPI_DBG("Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller"); - l_data.clearBit<59>().setBit<60>(); - FAPI_TRY( mss::scom_blastah(l_ports, MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0, l_data) ); + for (const auto& p : l_ports) + { + FAPI_TRY( mss::pc::read_dll_zcal_status(p, l_data) ); + FAPI_ASSERT(mss::pc::get_zcal_status(l_data) == mss::YES, + fapi2::MSS_ZCNTL_FAILED_TO_COMPLETE().set_MCA_IN_ERROR(p), + "zctl enable failed: %s", mss::c_str(p)); + } fapi_try_exit: -#endif return fapi2::current_err; } @@ -169,30 +171,6 @@ fapi_try_exit: return fapi2::current_err; } - -/// -/// @brief Unset the PLL and check to see that the PLL's have started -/// @param[in] i_target the mcbist target -/// @return FAPI2_RC_SUCCES iff ok -/// -fapi2::ReturnCode deassert_pll_reset( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) -{ - fapi2::buffer<uint64_t> l_data; - - // - // Write 0x4000 into the PC Resets Registers. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active - // - // TODO RTC:156693 Do we need to do this on Nimbus? BRS - FAPI_DBG("Write 0x4000 into the PC Resets Regs. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active"); - - l_data.setBit<MCA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET>(); - FAPI_TRY( mss::scom_blastah(mss::find_targets<TARGET_TYPE_MCA>(i_target), MCA_DDRPHY_PC_RESETS_P0, l_data) ); - -fapi_try_exit: - return fapi2::current_err; - -} - /// /// @brief Change the continuous update mode of the PR CNTL registers /// @note Will take the SYSCLK control out of reset, too diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H index 6b9010976..1d7cff95b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H @@ -33,25 +33,6 @@ #include <fapi2.H> #include <lib/mss_attribute_accessors.H> -// Helper macro to condense the checking for PLL lock -#define CHECK_PLL( __target, __register, __buffer, __mask ) \ - FAPI_TRY(mss::getScom( __target, __register, __buffer)); \ - if ((__buffer & __mask) != __mask) \ - { \ - FAPI_INF("PLL 0x%lx failed to lock 0x%lx", __register, __buffer); \ - done_polling = false; \ - continue; \ - } - -// Helper macro to condense the checking for PLL lock -#define FFDC_PLL( __target, __register, __buffer, __mask, __ffdc_object ) \ - FAPI_ASSERT( ((__buffer & __mask) == __mask), \ - __ffdc_object.set_EXPECTED_STATUS(__mask) \ - .set_ACTUAL_STATUS(__buffer) \ - .set_REGISTER(__register) \ - .set_MCBIST_IN_ERROR(__target), \ - "PLL 0x%llx failed to lock 0x%llx", __register, __buffer); - namespace mss { @@ -71,11 +52,11 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i fapi2::ReturnCode change_resetn( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, states i_state ); /// -/// @brief perform the zctl toggle process +/// @brief perform the zctl enable process /// @param[in] i_target the mcbist for the reset recover /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode toggle_zctl( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +fapi2::ReturnCode enable_zctl( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); /// @brief Change mclk low /// @param[in] i_target mcbist target diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H index 978eee23a..6000b7a39 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H @@ -68,6 +68,7 @@ class pcTraits<fapi2::TARGET_TYPE_MCA> static const uint64_t PC_ERROR_STATUS0_REG = MCA_DDRPHY_PC_ERROR_STATUS0_P0; static const uint64_t PC_INIT_CAL_ERROR_REG = MCA_DDRPHY_PC_INIT_CAL_ERROR_P0; static const uint64_t PC_DLL_ZCAL_CAL_STATUS_REG = MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0; + static const uint64_t PC_RESETS_REG = MCA_DDRPHY_PC_RESETS_P0; enum { @@ -98,6 +99,9 @@ class pcTraits<fapi2::TARGET_TYPE_MCA> DLL_CAL_STATUS_ADR_ERROR_FINE = MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_ERROR_FINE, ZCAL_CAL_STATUS_DONE = MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DONE, + SYSCLK_RESET = MCA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET, + PVT_OVERRIDE = MCA_DDRPHY_PC_RESETS_P0_PVT_OVERRIDE, + ENABLE_ZCAL = MCA_DDRPHY_PC_RESETS_P0_ENABLE_ZCAL, }; }; @@ -166,6 +170,18 @@ inline mss::states get_dll_cal_status( fapi2::buffer<uint64_t>& i_data ) // MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS is read-only /// +/// @brief Get ZCAL Cal Status +/// @param[in] fapi2::buffer representing the status register to interrogate +/// @return mss::states; YES == success, NO == fail +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = pcTraits<T> > +inline mss::states get_zcal_status( fapi2::buffer<uint64_t>& i_data ) +{ + FAPI_INF("zcal_status: 0x%016lx", i_data); + return (i_data.getBit<TT::ZCAL_CAL_STATUS_DONE>() == true) ? mss::YES : mss::NO; +} + +/// /// @brief read PC_ERROR_STATUS0 /// @param[in] i_target the fapi2 target of the port /// @param[out] o_data the value of the register @@ -270,6 +286,48 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief read PC_RESETS +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits<T> > +inline fapi2::ReturnCode read_resets( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::PC_RESETS_REG, o_data) ); + FAPI_INF("pc_resets: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write PC_RESETS +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits<T> > +inline fapi2::ReturnCode write_resets( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + FAPI_INF("pc_resets: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::PC_RESETS_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Set ENABLE_ZCAL in PC_RESETS +/// @param[out] o_data the value of the register +/// @param[in] i_state mss::HIGH or mss::LOW +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = pcTraits<T> > +inline void set_enable_zcal( fapi2::buffer<uint64_t>& o_data, const states i_state ) +{ + FAPI_INF("set_enable_zcal %s", (i_state == mss::LOW ? "low" : "high")); + o_data.writeBit<TT::ENABLE_ZCAL>(i_state); +} + } // close namespace pc } // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index 57607a8ea..57822a0ca 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -69,12 +69,14 @@ extern "C" // 3. Deassert reset_n FAPI_TRY( mss::change_resetn(i_target, mss::LOW), "change_resetn for %s failed", mss::c_str(i_target) ); - // 4, 5, 6. - FAPI_TRY( mss::toggle_zctl(i_target), "toggle_zctl for %s failed", mss::c_str(i_target) ); + // + // ZCTL Enable + // - // 7, 8. - FAPI_INF("deassert_pll_reset for %s", mss::c_str(i_target)); - FAPI_TRY( mss::deassert_pll_reset(i_target) ); + // 11. Assert the ZCNTL enable to the internal impedance controller in DDRPHY_PC_RESETS register + // 12. Wait at least 1024 dphy_gckn cycles + // 13. Deassert the ZCNTL impedance controller enable, Check for DONE in DDRPHY_PC_DLL_ZCAL + FAPI_TRY( mss::enable_zctl(i_target), "enable_zctl for %s failed", mss::c_str(i_target) ); // // DLL calibration @@ -95,8 +97,8 @@ extern "C" FAPI_INF("set up of phase rotator controls %s", mss::c_str(i_target) ); FAPI_TRY( mss::setup_phase_rotator_control_registers(i_target, mss::ON) ); - // 17. Wait at least 5932 dphy_nclk clock cycles to allow the dphy_nclk/SysClk alignment circuit to perform initial - // alignment. + // 17. Wait at least 5932 dphy_nclk clock cycles to allow the dphy_nclk/SysClk alignment circuit to + // perform initial alignment. FAPI_INF("Wait at least 5932 memory clock cycles for clock alignment circuit to perform initial alignment %s", mss::c_str(i_target)); FAPI_TRY( fapi2::delay(mss::cycles_to_ns(i_target, 5932), 2000) ); diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml index 930b80f0c..3d661f67f 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml @@ -42,6 +42,11 @@ </registerFfdc> <registerFfdc> + <id>REG_FFDC_ZCNTL_REGS</id> + <scomRegister>MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0</scomRegister> +</registerFfdc> + +<registerFfdc> <id>REG_FFDC_DLL_REGS</id> <scomRegister>MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0</scomRegister> @@ -324,4 +329,25 @@ </gard> </hwpError> +<hwpError> + <rc>RC_MSS_ZCNTL_FAILED_TO_COMPLETE</rc> + <description> + ZCAL failed to complete + </description> + <collectRegisterFfdc> + <id>REG_FFDC_ZCNTL_REGS</id> + <target>MCA_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>MCA_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MCA_IN_ERROR</target> + </deconfigure> + <gard> + <target>MCA_IN_ERROR</target> + </gard> +</hwpError> + </hwpErrors> |