diff options
Diffstat (limited to 'src/import/chips/p9a/procedures/hwp/memory')
8 files changed, 328 insertions, 55 deletions
diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H index 5cf787640..48f5cb222 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H @@ -252,13 +252,13 @@ fapi2::ReturnCode setup_mc_config0( l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT, TT::MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN>( - mss::omi::phy_ctr_mode::PHY_CTR_MODE_50US); + mss::omi::phy_ctr_mode::PHY_CTR_MODE_60MS); // CFG_DL0_RUNLANE_OVRD_ENABLE: When enabled, the dl0 will drive run lane to the PHY for all training states. l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_TX_EP_MODE>(0); // CFG_DL0_PWRMGT_ENABLE: dl0 power management enabled - l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_PWRMGT_ENABLE>(1); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_PWRMGT_ENABLE>(0); // CFG_DL0_QUARTER_WIDTH_BACKOFF_ENABLE: dl0 x1 backoff enabled l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE>(0); @@ -283,6 +283,9 @@ fapi2::ReturnCode setup_mc_config0( // CFG_DL0_RESET: dl0 reset - Reset dl0 back to traning state 0 l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_RESET>(0); + FAPI_DBG("Writing 0x%16llx to MC_REG2_DL0_CONFIG0 (0x%16llx) of %s", + l_val, TT::MC_REG2_DL0_CONFIG0, mss::c_str(i_target)); + FAPI_TRY( mss::putScom(i_target, TT::MC_REG2_DL0_CONFIG0, l_val) ); fapi_try_exit: diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C index e4ac4af7c..783091c62 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C @@ -59,7 +59,7 @@ namespace mc /// @param[in] i_proc_type PROC type/name /// @return true/false perform workaround /// -bool is_prbs_omi_required_helper(const uint8_t i_ocmb_type, const uint8_t i_proc_type) +bool is_prbs_omi_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type) { // OMI Workaround Logic: // Explorer+Axone: OMI/PROC-side workaround off @@ -70,66 +70,91 @@ bool is_prbs_omi_required_helper(const uint8_t i_ocmb_type, const uint8_t i_proc } /// -/// @brief Determine whether to perform PRBS OMI workaround +/// @brief Helper function to determine whether PRBS axone OMI workarounds will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_axone_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type) +{ + // OMI Workaround Logic: + // Explorer+Axone: Workaround on. + // Else: None + return ((i_proc_type == fapi2::ENUM_ATTR_NAME_AXONE) + && (i_ocmb_type == fapi2::ENUM_ATTR_NAME_EXPLORER)); // Explorer && axone +} + +/// +/// @brief Perform PRBS delay from prbs time and sim attributes +/// +/// @param[in] i_omi OMI target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_omi) +{ + uint8_t l_sim = 0; + uint32_t l_prbs_time = 0; + uint64_t l_prbs_time_scaled = 0; + + FAPI_TRY( mss::attr::get_is_simulation( l_sim) ); + + FAPI_TRY(mss::attr::get_omi_dl_preipl_prbs_time(i_omi, l_prbs_time), + "Error from FAPI_ATTR_GET (ATTR_OMI_DL_PREIPL_PRBS_TIME)"); + l_prbs_time_scaled = l_prbs_time * mss::common_timings::DELAY_1MS; + + FAPI_TRY(fapi2::delay(l_prbs_time_scaled, mss::common_timings::DELAY_1US)); + FAPI_DBG("OMI Training Pre-ipl PRBS Time = %dns", + (l_sim ? mss::common_timings::DELAY_1US : l_prbs_time_scaled)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Get PROC and OCMB types /// /// @param[in] i_ocmb_chip OCMB chip /// @param[in] i_proc_chip PROC chip /// @param[out] o_required workaround required /// @return FAPI2_RC_SUCCESS iff success /// -fapi2::ReturnCode is_prbs_omi_required( +fapi2::ReturnCode get_ocmb_proc_types( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> i_proc_chip, - bool& o_required) + uint8_t& o_ocmb_type, + uint8_t& o_proc_type) { - uint8_t l_ocmb_type = 0; - uint8_t l_proc_type = 0; - - FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_ocmb_chip, l_ocmb_type), + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_ocmb_chip, o_ocmb_type), "Error getting ATTR_NAME of %s", mss::c_str(i_ocmb_chip)); - FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_proc_chip, l_proc_type), + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_proc_chip, o_proc_type), "Error getting ATTR_NAME of %s", mss::c_str(i_proc_chip)); - o_required = is_prbs_omi_required_helper(l_ocmb_type, l_proc_type); - fapi_try_exit: return fapi2::current_err; } /// -/// @brief Perform the PRBS OMI workaround +/// @brief Perform the PRBS OMI workaround for gemini configurations /// /// @param[in] i_omi OMI /// @param[in] i_dl_x4_backoff_en backoff enable bit /// @return fapi2::FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode prbs_omi( +fapi2::ReturnCode omi_training_prbs_gem( const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, const uint8_t i_dl_x4_backoff_en) { FAPI_DBG("Performing PRBS OMI workaround on %s", mss::c_str(i_omi)); - uint32_t l_prbs_time = 0; - uint64_t l_prbs_time_scaled = 0; - uint8_t l_sim = 0; - FAPI_TRY(mss::attr::get_is_simulation(l_sim)); - - // Get PRBS time - FAPI_TRY(mss::attr::get_omi_dl_preipl_prbs_time(i_omi, l_prbs_time), - "Error from FAPI_ATTR_GET (ATTR_OMI_DL_PREIPL_PRBS_TIME)"); - l_prbs_time_scaled = l_prbs_time * mss::common_timings::DELAY_1MS; - // *_CONFIG0 should be the last one written, since it starts the training. // We are not using the pre-ipl PRBS auto training mode because it doesn't function properly in Axone // Enable training state 6 to send TS3 FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_TRAINING_STATE3, i_dl_x4_backoff_en)); - // Set configurable delay based on the PRBS ATTR and SIM mode - FAPI_TRY(fapi2::delay(l_prbs_time_scaled, mss::common_timings::DELAY_1US)); - FAPI_DBG("OMI Training Pre-ipl PRBS Time = %dns", - (l_sim ? mss::common_timings::DELAY_1US : l_prbs_time_scaled)); + FAPI_TRY(prbs_delay(i_omi)); // Enable training state 1 to send Pattern A FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_PATTERN_A, i_dl_x4_backoff_en)); @@ -138,6 +163,50 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Perform p9a_omi_train workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode omi_training_prbs( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en) +{ + FAPI_DBG("Performing OMI Train axone workaround on %s", mss::c_str(i_omi)); + + // Training mode 1: send Pattern A + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_PATTERN_A, i_dl_x4_backoff_en)); + + FAPI_TRY(fapi2::delay(100 * mss::common_timings::DELAY_1MS, mss::common_timings::DELAY_1MS)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform p9a_omi_setup (pre-training) workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_omi_training_prbs( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en) +{ + FAPI_DBG("Performing OMI Setup axone workaround on %s", mss::c_str(i_omi)); + + // Training mode 4: send State 1 + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_TRAINING_STATE1, i_dl_x4_backoff_en)); + + FAPI_TRY(prbs_delay(i_omi)); + +fapi_try_exit: + return fapi2::current_err; +} + } // mc } // workarounds } // mss diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H index 45828a2af..4491a91e3 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H @@ -51,29 +51,69 @@ namespace mc /// @param[in] i_proc_type PROC type/name /// @return true/false perform workaround /// -bool is_prbs_omi_required_helper(const uint8_t i_ocmb_type, const uint8_t i_proc_type); +bool is_prbs_omi_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type); /// -/// @brief Determine whether to perform PRBS OMI workaround +/// @brief Helper function to determine whether PRBS axone OMI workarounds will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_axone_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type); + +/// +/// @brief Perform PRBS delay from prbs time and sim attributes +/// +/// @param[in] i_omi OMI target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_omi); + +/// +/// @brief Get PROC and OCMB types /// /// @param[in] i_ocmb_chip OCMB chip /// @param[in] i_proc_chip PROC chip /// @param[out] o_required workaround required /// @return FAPI2_RC_SUCCESS iff success /// -fapi2::ReturnCode is_prbs_omi_required( +fapi2::ReturnCode get_ocmb_proc_types( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> i_proc_chip, - bool& o_required); + uint8_t& o_ocmb_type, + uint8_t& o_proc_type); /// -/// @brief Perform the PRBS OMI workaround +/// @brief Perform the PRBS OMI workaround for gemini configurations /// /// @param[in] i_omi OMI /// @param[in] i_dl_x4_backoff_en backoff enable bit /// @return fapi2::FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode prbs_omi( +fapi2::ReturnCode omi_training_prbs_gem( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en); + +/// +/// @brief Perform p9a_omi_train workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode omi_training_prbs( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en); + +/// +/// @brief Perform p9a_omi_setup (pre-training) workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_omi_training_prbs( const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, const uint8_t i_dl_x4_backoff_en); diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C index 06edf3375..eaccc18c9 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C @@ -22,3 +22,77 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file p9a_omi_setup.C +/// @brief Setup the OMI +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/shared/axone_defaults.H> +#include <p9a_omi_setup.H> +#include <lib/mc/omi.H> +#include <generic/memory/mss_git_data_helper.H> +#include <lib/workarounds/p9a_omi_workarounds.H> + +/// +/// @brief Setup OMI for axone +/// @param[in] i_target the axone OMI target to operate on +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode p9a_omi_setup( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_target ) +{ + mss::display_git_commit_info("p9a_omi_setup"); + + FAPI_INF("%s Start p9a_omi_setup", mss::c_str(i_target)); + + const auto& l_mc = mss::find_target<fapi2::TARGET_TYPE_MC>(i_target); + const auto& l_ocmbs = mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); + + FAPI_TRY(mss::mc::setup_mc_mcn_config(l_mc)); + FAPI_TRY(mss::mc::setup_mc_config1(i_target)); + FAPI_TRY(mss::mc::setup_mc_cya_bits(i_target)); + FAPI_TRY(mss::mc::setup_mc_error_action(i_target)); + FAPI_TRY(mss::mc::setup_mc_rmt_config(i_target)); + + if(l_ocmbs.empty()) + { + // No ocmbs, no training needed + // Ensuring we don't try to access an empty vector + return fapi2::FAPI2_RC_SUCCESS; + } + + { + // Only one OCMB per OMI for axone + const auto& l_ocmb = l_ocmbs[0]; + const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); + uint8_t l_dl_x4_backoff_en = 0; + bool l_axone_workarounds_required = false; + uint8_t l_proc_type = 0; + uint8_t l_ocmb_type = 0; + + // Get BACKOFF_ENABLE CHIP_EC attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE, l_ocmb, l_dl_x4_backoff_en), + "Error getting ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE"); + + // Determine if workaround will be performed, if so, perform it + FAPI_TRY(mss::workarounds::mc::get_ocmb_proc_types(l_ocmb, l_proc, l_ocmb_type, l_proc_type)); + l_axone_workarounds_required = mss::workarounds::mc::is_prbs_omi_axone_required(l_ocmb_type, l_proc_type); + + if (l_axone_workarounds_required) + { + // TX_TRAINING_STATE1 + FAPI_TRY(mss::workarounds::mc::pre_omi_training_prbs(i_target, l_dl_x4_backoff_en)); + } + + return fapi2::FAPI2_RC_SUCCESS; + } + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H index a5e089214..cf364294b 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H @@ -22,3 +22,32 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file p9a_omi_setup.H +/// @brief Setup the OMI +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef P9A_OMI_SETUP_H_ +#define P9A_OMI_SETUP_H_ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9a_omi_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OMI>&); + +extern "C" +{ + /// + /// @brief Setup OMI for axone + /// @param[in] i_target the axone OMI target to operate on + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode p9a_omi_setup( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_target ); +} + +#endif diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.mk index c4264c879..1edeebce8 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.mk @@ -22,3 +22,8 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG +-include 00p9a_common.mk + +PROCEDURE=p9a_omi_setup +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C index 5913df90d..2075dfc5a 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C @@ -62,15 +62,8 @@ fapi2::ReturnCode p9a_omi_train( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_ FAPI_INF("%s Start p9a_omi_train", mss::c_str(i_target)); - const auto& l_mc = mss::find_target<fapi2::TARGET_TYPE_MC>(i_target); const auto& l_ocmbs = mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); - FAPI_TRY(mss::mc::setup_mc_mcn_config(l_mc)); - FAPI_TRY(mss::mc::setup_mc_config1(i_target)); - FAPI_TRY(mss::mc::setup_mc_cya_bits(i_target)); - FAPI_TRY(mss::mc::setup_mc_error_action(i_target)); - FAPI_TRY(mss::mc::setup_mc_rmt_config(i_target)); - if(l_ocmbs.empty()) { // No ocmbs, no training needed @@ -82,18 +75,32 @@ fapi2::ReturnCode p9a_omi_train( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_ const auto& l_ocmb = l_ocmbs[0]; const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(l_ocmb); uint8_t l_dl_x4_backoff_en = 0; - bool l_workaround_required = false; + bool l_gem_or_non_axone_workaround = false; + bool l_axone_workarounds_required = false; + uint8_t l_proc_type = 0; + uint8_t l_ocmb_type = 0; // Get BACKOFF_ENABLE CHIP_EC attribute FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE, l_ocmb, l_dl_x4_backoff_en), "Error getting ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE"); - // Determine if workaround will be performed, if so, perform it - FAPI_TRY(mss::workarounds::mc::is_prbs_omi_required(l_ocmb, l_proc, l_workaround_required)); + // Determine if workarounds will be performed, if so, perform them + FAPI_TRY(mss::workarounds::mc::get_ocmb_proc_types(l_ocmb, l_proc, l_ocmb_type, l_proc_type)); + l_gem_or_non_axone_workaround = mss::workarounds::mc::is_prbs_omi_required(l_ocmb_type, l_proc_type); + l_axone_workarounds_required = mss::workarounds::mc::is_prbs_omi_axone_required(l_ocmb_type, l_proc_type); - if (l_workaround_required) + if (l_axone_workarounds_required) + { + // TX_PATTERN_A + FAPI_TRY(mss::workarounds::mc::omi_training_prbs(i_target, l_dl_x4_backoff_en)); + } + else if (l_gem_or_non_axone_workaround) { - FAPI_TRY(mss::workarounds::mc::prbs_omi(i_target, l_dl_x4_backoff_en)); + // TX_TRAINING_STATE_3, TX_PATTERN_A + FAPI_TRY(mss::workarounds::mc::omi_training_prbs_gem(i_target, l_dl_x4_backoff_en)); + + // 2 second delay for gemini + FAPI_TRY(fapi2::delay(2 * mss::common_timings::DELAY_1S, mss::common_timings::DELAY_1MS)); } // Enable auto training diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C index 8a010bded..9aae6b90f 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C @@ -59,48 +59,94 @@ fapi2::ReturnCode p9a_omi_train_check( const fapi2::Target<fapi2::TARGET_TYPE_OM // Const constexpr uint8_t STATE_MACHINE_SUCCESS = 0b111; // This value is from Lonny Lambrecht - constexpr uint8_t MAX_LOOP_COUNT = 20; // Retry times + constexpr uint8_t MAX_LOOP_COUNT = 10; // Retry times // Declares variables fapi2::buffer<uint64_t> l_omi_status; fapi2::buffer<uint64_t> l_omi_training_status; + fapi2::buffer<uint64_t> l_dl0_error_hold; + fapi2::buffer<uint64_t> l_expected_dl0_error_hold; + fapi2::buffer<uint64_t> l_dl0_config1; uint8_t l_state_machine_state = 0; uint8_t l_tries = 0; + uint32_t l_omi_freq = 0; + + const auto& l_ocmbs = mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); + + // Sanity check for no empty vector + if (l_ocmbs.empty()) + { + // No training could have occurred + return fapi2::FAPI2_RC_SUCCESS; + } + + const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(l_ocmbs[0]); FAPI_TRY(mss::mc::omi_train_status(i_target, l_state_machine_state, l_omi_status)); - while (l_tries < MAX_LOOP_COUNT && l_state_machine_state != STATE_MACHINE_SUCCESS) + do { // Delay - fapi2::delay(mss::DELAY_100US, 10 * mss::DELAY_1MS); + fapi2::delay(500 * mss::DELAY_1MS, 10 * mss::DELAY_1MS); // Check OMI training status FAPI_TRY(mss::mc::omi_train_status(i_target, l_state_machine_state, l_omi_status)); - // Note: this is very useful debug information while trying to debug training during polling - FAPI_TRY(mss::getScom(i_target, P9A_MC_REG2_DL0_TRAINING_STATUS, l_omi_training_status)); l_tries++; + } + while (l_tries < MAX_LOOP_COUNT && l_state_machine_state != STATE_MACHINE_SUCCESS); + // Note: this is very useful debug information while trying to debug training during polling FAPI_TRY(mss::getScom(i_target, P9A_MC_REG2_DL0_TRAINING_STATUS, l_omi_training_status)); + FAPI_TRY(fapi2::getScom(i_target, P9A_MC_REG2_DL0_CONFIG1, l_dl0_config1)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_OMI_MHZ, l_proc, l_omi_freq)); + FAPI_ASSERT(l_state_machine_state == STATE_MACHINE_SUCCESS, fapi2::P9A_OMI_TRAIN_ERR() - .set_TARGET(i_target) + .set_OMI_TARGET(i_target) + .set_OCMB_TARGET(l_ocmbs[0]) .set_EXPECTED_SM_STATE(STATE_MACHINE_SUCCESS) .set_ACTUAL_SM_STATE(l_state_machine_state) .set_DL0_STATUS(l_omi_status) - .set_DL0_TRAINING_STATUS(l_omi_training_status), - "%s OMI Training Failure, expected state:%d/actual state:%d", + .set_DL0_TRAINING_STATUS(l_omi_training_status) + .set_DL0_CONFIG1(l_dl0_config1) + .set_OMI_FREQ(l_omi_freq), + "%s P9A OMI Training Failure, expected state:%d/actual state:%d", mss::c_str(i_target), STATE_MACHINE_SUCCESS, l_state_machine_state ); + // Check errors in ERROR_HOLD until we get a proper FIR API setup + FAPI_TRY(mss::getScom(i_target, P9A_MC_REG2_DL0_ERROR_HOLD, l_dl0_error_hold)); + + // Training completion bit set + l_expected_dl0_error_hold.setBit<P9A_OMI_REG0_DL0_ERROR_HOLD_CERR_39>(); + + // Lost block bit set: this results in p9a only, from the + // necessary pre-training workarounds, and is expected to be set + // TK - We will need to the proper FIR unmasking later + l_expected_dl0_error_hold.setBit<P9A_OMI_REG0_DL0_ERROR_HOLD_CERR_33>(); + + if (l_dl0_error_hold != l_expected_dl0_error_hold) + { + // To get to this point, we had to have completed training, so these errors are not catastrophic + // We don't need to assert out, but let's make sure we print them out + FAPI_INF("%s P9A_MC_REG2_DL0_ERROR_HOLD REG 0x%016llx " + "did not match expected value. REG contents: 0x%016llx Expected: 0x%016llx", + mss::c_str(i_target), + P9A_MC_REG2_DL0_ERROR_HOLD, + l_dl0_error_hold, + l_expected_dl0_error_hold); + } + FAPI_INF("%s End p9a_omi_train_check, expected state:%d/actual state:%d, DL0_STATUS:0x%016llx, DL0_TRAINING_STATUS:0x%016llx", mss::c_str(i_target), STATE_MACHINE_SUCCESS, l_state_machine_state, l_omi_status, l_omi_training_status); + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: |
