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Diffstat (limited to 'src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H')
-rw-r--r-- | src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H index ae17d925d..1b4f96d0c 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H @@ -22,3 +22,73 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file axone_freq_traits.H +/// @brief Contains frequency traits information for Axone +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP FW Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: CI + +#ifndef _AXONE_FREQ_TRAITS_H_ +#define _AXONE_FREQ_TRAITS_H_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/freq/gen_mss_freq_traits.H> +#include <vpd_access.H> + +namespace mss +{ + +/// +/// @class Traits and policy class for frequency and synchronous code - specialization for the AXONE processor type +/// +template<> +class frequency_traits<mss::proc_type::AXONE> +{ + public: + ////////////////////////////////////////////////////////////// + // Target types + ////////////////////////////////////////////////////////////// + static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + static constexpr fapi2::TargetType FREQ_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + static constexpr fapi2::TargetType VPD_TARGET_TYPE = fapi2::TARGET_TYPE_OCMB_CHIP; + + ////////////////////////////////////////////////////////////// + // Traits values + ////////////////////////////////////////////////////////////// + static const std::vector<uint64_t> SUPPORTED_FREQS; + // MEM_PORT is our frequency domain. So 1 port per domain + static constexpr uint64_t PORTS_PER_FREQ_DOMAIN = 1; + // Max DIMM's per port + static constexpr uint64_t MAX_DIMM_PER_PORT = 2; + // Maxium number of primary ranks on a DIMM + static constexpr uint64_t MAX_PRIMARY_RANK_PER_DIMM = 4; + // MC type for Axone is constant - EXPLORER + static constexpr mss::mc_type MC = mss::mc_type::EXPLORER; + static constexpr const char* PROC_STR = "AXONE"; + + // VPD traits values + // TK Resolve these when we know what they are for Axone + static constexpr uint64_t VPD_KEYWORD_MAX = 255; + static constexpr const char* VPD_BLOB_NAME = "EFD"; + static constexpr auto VPD_BLOB = fapi2::MemVpdData::EFD; + static constexpr auto LRDIMM_TYPE = fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM; + + // Coding minion, why have these explicitly defined frequency values? + // Isn't the supported frequency vector used for this purpose? + // Well, we need to callout the specific frequency values that are allowed on a given system + // As we can't callout a vector in error callouts and each traits might have a different number of allowable traits, + // the below values are hardcoded specifically for the error callouts + static constexpr uint64_t SUPPORTED_FREQ0 = DIMM_SPEED_2666; + static constexpr uint64_t SUPPORTED_FREQ1 = DIMM_SPEED_2933; + static constexpr uint64_t SUPPORTED_FREQ2 = DIMM_SPEED_3200; +}; + + +} // ns mss +#endif |