diff options
Diffstat (limited to 'src/import/chips/p9')
12 files changed, 580 insertions, 154 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C index 2f86d7d21..84ddaa1c6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C @@ -25,7 +25,7 @@ // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <math.h> @@ -64,7 +64,7 @@ using fapi2::TARGET_TYPE_MCBIST; /// DA[2] QxPAR disabled /// DA [1:0] QxC[2:0] (Chip ID) /// -enum rc08_encode : uint64_t +enum rc08_encode { CID_START = 6, CID_LENGTH = 2, @@ -115,7 +115,7 @@ enum rc0d_encode : uint8_t /// @brief bit encodings for RC0E /// From DDR4 Register v1.0 /// -enum rc0e_encode : uint64_t +enum rc0e_encode { RC0E_PARITY_ENABLE_BIT = 7, RC0E_PARITY_ENABLE = 1, @@ -175,6 +175,16 @@ enum lrdimm_databuffers LRDIMM_DB02 = 0b0001 }; +/// +/// @brief encoding for MSS_INVALID_FREQ so we can look up functions based on encoding +/// +enum invalid_freq_function_encoding +{ + RC0A = 0x0a, + RC3X = 0x30, + BC0A = 0x0a, +}; + ///////////////////////// // Non-member function implementations ///////////////////////// @@ -365,6 +375,16 @@ fapi2::ReturnCode eff_dimm::dram_width() FAPI_TRY( iv_pDecoder->device_width(l_decoder_val), "Failed accessing device width from SPD %s", mss::c_str(iv_dimm) ); FAPI_TRY( eff_dram_width(iv_mcs, &l_mcs_attrs[0][0]), "Failed getting EFF_DRAM_WIDTH" ); + // Enforcing NIMBUS restrictions + FAPI_ASSERT( (l_decoder_val == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) || + (l_decoder_val == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4), + fapi2::MSS_INVALID_DRAM_WIDTH() + .set_DRAM_WIDTH(l_decoder_val) + .set_TARGET(iv_dimm), + "Unsupported DRAM width with %d for target %s", + l_decoder_val, + mss::c_str(iv_dimm)); + l_mcs_attrs[iv_port_index][iv_dimm_index] = l_decoder_val; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_WIDTH, iv_mcs, l_mcs_attrs), "Failed setting ATTR_EFF_DRAM_WIDTH" ); @@ -379,7 +399,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dram_density() { - uint8_t l_decoder_val = 0; FAPI_TRY( iv_pDecoder->sdram_density(l_decoder_val), "Failed to get dram_density from SPD %s", mss::c_str(iv_dimm) ); @@ -480,6 +499,7 @@ fapi2::ReturnCode eff_dimm::primary_stack_type() break; default: + // SPD decoder should limit this two just two types, if we get here, there was a coding error FAPI_ERR("Error decoding prim_sdram_package_type"); fapi2::Assert(false); }; @@ -503,6 +523,16 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dimm_size() { + std::vector<uint32_t> l_dimm_sizes = { fapi2::ENUM_ATTR_EFF_DIMM_SIZE_4GB, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_8GB, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_256GB, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_512GB, + }; + // Retrieve values needed to calculate dimm size uint8_t l_bus_width = 0; uint8_t l_sdram_width = 0; @@ -515,12 +545,40 @@ fapi2::ReturnCode eff_dimm::dimm_size() FAPI_TRY( iv_pDecoder->logical_ranks_per_dimm(l_logical_rank_per_dimm), "Failed to get logical ranks from SPD %s", mss::c_str(iv_dimm) ); + // Let's sort the dimm size vector just to be super duper safe + std::sort( l_dimm_sizes.begin(), l_dimm_sizes.end() ); { + + // Double checking to avoid divide by zero errors + // If this fails, there was a problem with the check in SPD function + FAPI_ASSERT( l_sdram_density != 0, + fapi2::MSS_BAD_SDRAM_DENSITY_DECODER() + .set_DRAM_DENSITY(l_sdram_density) + .set_TARGET(iv_dimm), + "SPD decoder messed up and returned a 0. Should have been caught already %s", + mss::c_str(iv_dimm)); + // Calculate dimm size - // Formula from SPD Spec + // Formula from SPD Spec (seriously, they don't have parenthesis in the spec) // Total = SDRAM Capacity / 8 * Primary Bus Width / SDRAM Width * Logical Ranks per DIMM const uint32_t l_dimm_size = (l_sdram_density * l_bus_width * l_logical_rank_per_dimm) / (8 * l_sdram_width); + FAPI_ASSERT( (std::binary_search(l_dimm_sizes.begin(), l_dimm_sizes.end(), l_dimm_size) == true), + fapi2::MSS_INVALID_CALCULATED_DIMM_SIZE() + .set_SDRAM_WIDTH(l_sdram_width) + .set_BUS_WIDTH(l_bus_width) + .set_DRAM_DENSITY(l_sdram_density) + .set_LOGICAL_RANKS(l_logical_rank_per_dimm) + .set_TARGET(iv_dimm), + "Recieved an invalid dimm size (%d) for calculated DIMM_SIZE for target %s" + "(l_sdram_density %d * l_bus_width %d * l_logical_rank_per_dimm %d) / (8 * l_sdram_width %d", + l_dimm_size, + mss::c_str(iv_dimm), + l_sdram_width, + l_bus_width, + l_sdram_density, + l_logical_rank_per_dimm); + // Get & update MCS attribute uint32_t l_attrs_dimm_size[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; FAPI_TRY( eff_dimm_size(iv_mcs, &l_attrs_dimm_size[0][0]), "Failed to get ATTR_MSS_EFF_DIMM_SIZE" ); @@ -606,7 +664,6 @@ fapi2::ReturnCode eff_dimm::dram_trefi() { // Calculate refresh cycle time in nCK & set attribute - std::vector<uint16_t> l_mcs_attrs_trefi(PORTS_PER_MCS, 0); uint64_t l_trefi_in_nck = 0; @@ -742,7 +799,7 @@ fapi2::ReturnCode eff_dimm::dram_trfc_dlr() l_density, iv_refresh_mode); // Calculate refresh cycle time in ps - FAPI_TRY( calc_trfc_dlr(iv_refresh_mode, l_density, l_trfc_dlr_in_ps), "Failed calc_trfc_dlr()" ); + FAPI_TRY( calc_trfc_dlr(iv_dimm, iv_refresh_mode, l_density, l_trfc_dlr_in_ps), "Failed calc_trfc_dlr()" ); // Calculate clock period (tCK) from selected freq from mss_freq FAPI_TRY( clock_period(iv_dimm, l_tCK_in_ps), "Failed to calculate clock period (tCK)"); @@ -845,6 +902,16 @@ fapi2::ReturnCode eff_dimm::dram_dqs_time() FAPI_TRY( eff_dram_tdqs(iv_mcs, &l_attrs_dqs_time[0]) ); FAPI_INF("SDRAM width: %d for target %s", l_dram_width, mss::c_str(iv_dimm)); + // Enforcing current NIMBUS standards. + FAPI_ASSERT( (l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) || + (l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4), + fapi2::MSS_INVALID_DRAM_WIDTH() + .set_DRAM_WIDTH(l_dram_width) + .set_TARGET(iv_dimm), + "Invalid DRAM width with %d for target %s", + l_dram_width, + mss::c_str(iv_dimm)); + // Only possible dram width are x4, x8. If x8, tdqs is available, else not available l_attrs_dqs_time[iv_port_index] = (l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) ? fapi2::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE : fapi2::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE; @@ -1173,7 +1240,8 @@ fapi2::ReturnCode eff_dimm::dimm_rc08() fapi2::MSS_INVALID_CALCULATED_NUM_SLAVE_RANKS() .set_NUM_SLAVE_RANKS(l_num_slave_ranks) .set_NUM_TOTAL_RANKS(l_total_ranks) - .set_NUM_MASTER_RANKS(l_master_ranks), + .set_NUM_MASTER_RANKS(l_master_ranks) + .set_TARGET(iv_dimm), "For target %s: Invalid total_ranks %d seen with %d master ranks", mss::c_str(iv_dimm), l_total_ranks, @@ -1191,7 +1259,8 @@ fapi2::ReturnCode eff_dimm::dimm_rc08() fapi2::MSS_INVALID_CALCULATED_NUM_SLAVE_RANKS() .set_NUM_SLAVE_RANKS(l_num_slave_ranks) .set_NUM_TOTAL_RANKS(l_total_ranks) - .set_NUM_MASTER_RANKS(l_master_ranks), + .set_NUM_MASTER_RANKS(l_master_ranks) + .set_TARGET(iv_dimm), "For target %s: Invalid number of slave ranks calculated (%d) from (total_ranks %d / master %d)", mss::c_str(iv_dimm), l_num_slave_ranks, @@ -1292,8 +1361,12 @@ fapi2::ReturnCode eff_dimm::dimm_rc0a() break; default: - FAPI_ERR("Invalid frequency for RC0a encoding received: %d", iv_freq); - return fapi2::FAPI2_RC_FALSE; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_RC() + .set_FREQ(iv_freq) + .set_RC_NUM(RC0A) + .set_TARGET(iv_dimm), + "Invalid frequency for rc0a encoding received: %d", iv_freq); break; } @@ -1521,8 +1594,14 @@ fapi2::ReturnCode eff_dimm::dimm_rc3x() break; default: - FAPI_ERR("Invalid frequency for rc_3x encoding received: %d", iv_freq); - return fapi2::FAPI2_RC_FALSE; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_RC() + .set_FREQ(iv_freq) + .set_RC_NUM(RC3X) + .set_TARGET(iv_dimm), + "%s: Invalid frequency for RC_3X encoding received: %d", + mss::c_str(iv_dimm), + iv_freq); break; } @@ -1854,7 +1933,7 @@ fapi2::ReturnCode eff_dimm::dram_cwl() FAPI_ASSERT( ((l_preamble == 0) || (l_preamble == 1)), fapi2::MSS_INVALID_VPD_MT_PREAMBLE() .set_VALUE(l_preamble) - .set_DIMM_TARGET(iv_dimm), + .set_MCA_TARGET(iv_mca), "Target %s VPD_MT_PREAMBLE is invalid (not 1 or 0), value is %d", mss::c_str(iv_dimm), l_preamble ); @@ -1863,7 +1942,8 @@ fapi2::ReturnCode eff_dimm::dram_cwl() if (l_preamble == 0) { FAPI_TRY( mss::find_value_from_key( CWL_TABLE_1, - iv_freq, l_cwl), + iv_freq, + l_cwl), "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d", iv_freq, l_preamble); @@ -1871,7 +1951,8 @@ fapi2::ReturnCode eff_dimm::dram_cwl() else { FAPI_TRY( mss::find_value_from_key( CWL_TABLE_2, - iv_freq, l_cwl), + iv_freq, + l_cwl), "Failed finding CAS Write Latency (cwl), freq: %d, preamble %d", iv_freq, l_preamble); @@ -2038,8 +2119,7 @@ fapi2::ReturnCode eff_dimm::vref_dq_train_value() FAPI_ASSERT(l_train_value <= JEDEC_MAX_TRAIN_VALUE, fapi2::MSS_INVALID_VPD_VREF_DRAM_WR_RANGE() .set_MAX(JEDEC_MAX_TRAIN_VALUE) - .set_VALUE(l_train_value) - .set_DIMM_TARGET(iv_dimm), + .set_VALUE(l_train_value), "%s VPD DRAM VREF value out of range max 0x%02x value 0x%02x", mss::c_str(iv_dimm), JEDEC_MAX_TRAIN_VALUE, l_train_value ); @@ -2066,7 +2146,7 @@ fapi_try_exit: fapi2::ReturnCode eff_dimm::vref_dq_train_enable() { // Default mode for train enable should be normal operation mode - 0x00 - + static constexpr uint8_t NORMAL_MODE = 0x00; uint8_t l_attrs_vref_dq_train_enable[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; std::vector< uint64_t > l_ranks; @@ -2076,7 +2156,7 @@ fapi2::ReturnCode eff_dimm::vref_dq_train_enable() for(const auto& l_rank : l_ranks) { - l_attrs_vref_dq_train_enable[iv_port_index][iv_dimm_index][index(l_rank)] = 0x00; + l_attrs_vref_dq_train_enable[iv_port_index][iv_dimm_index][index(l_rank)] = NORMAL_MODE; } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_VREF_DQ_TRAIN_ENABLE, iv_mcs, l_attrs_vref_dq_train_enable), @@ -2214,7 +2294,6 @@ fapi2::ReturnCode eff_dimm::odt_input_buffer() uint8_t l_sim = 0; FAPI_TRY( mss::is_simulation(l_sim) ); - FAPI_TRY( eff_odt_input_buff(iv_mcs, l_attrs_odt_input_buffer.data()) ); // sim vs actual hardware value @@ -2253,7 +2332,7 @@ fapi_try_exit: /// /// @brief Determines & sets effective config for write_dbi /// @return fapi2::FAPI2_RC_SUCCESS if okay -/// @note DBI is not supported +/// @note write_dbi is not supported, so set to DISABLED (0) /// fapi2::ReturnCode eff_dimm::write_dbi() { @@ -2353,7 +2432,7 @@ fapi2::ReturnCode eff_dimm::read_preamble() FAPI_ASSERT( ((l_preamble == 0) || (l_preamble == 1)), fapi2::MSS_INVALID_VPD_MT_PREAMBLE() .set_VALUE(l_preamble) - .set_DIMM_TARGET(iv_dimm), + .set_MCA_TARGET(iv_mca), "Target %s VPD_MT_PREAMBLE is invalid (not 1 or 0), value is %d", mss::c_str(iv_dimm), l_preamble ); @@ -2387,7 +2466,7 @@ fapi2::ReturnCode eff_dimm::write_preamble() FAPI_ASSERT( ((l_preamble == 0) || (l_preamble == 1)), fapi2::MSS_INVALID_VPD_MT_PREAMBLE() .set_VALUE(l_preamble) - .set_DIMM_TARGET(iv_dimm), + .set_MCA_TARGET(iv_mca), "Target %s VPD_MT_PREAMBLE is invalid (not 1 or 0), value is %d", mss::c_str(iv_dimm), l_preamble ); @@ -3003,7 +3082,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dram_trrd_s() { - std::vector<uint8_t> l_attrs_dram_trrd_s(PORTS_PER_MCS, 0); uint64_t l_trrd_s_in_nck = 0; uint8_t l_stack_type = 0; @@ -3052,7 +3130,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dram_trrd_l() { - std::vector<uint8_t> l_attrs_dram_trrd_l(PORTS_PER_MCS, 0); uint64_t l_trrd_l_in_nck = 0; uint8_t l_stack_type = 0; @@ -3126,7 +3203,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dram_tfaw() { - std::vector<uint8_t> l_attrs_dram_tfaw(PORTS_PER_MCS, 0); uint64_t l_tfaw_in_nck = 0; uint8_t l_stack_type = 0; @@ -3305,7 +3381,16 @@ fapi2::ReturnCode eff_rdimm::dram_rtt_nom() 0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_NOM_OHM240 / l_rtt_nom[mss::index(l_rank)]; // Make sure it's a valid mss::index - fapi2::Assert( l_rtt_nom_index < RTT_NOM_MAP_SIZE); + FAPI_ASSERT( l_rtt_nom_index < RTT_NOM_MAP_SIZE, + fapi2::MSS_INVALID_RTT_NOM_CALCULATIONS() + .set_RANK(l_rank) + .set_RTT_NOM_INDEX(l_rtt_nom_index) + .set_RTT_NOM_FROM_VPD(l_rtt_nom[mss::index(l_rank)]), + "Error calculating RTT_NOM for target %s rank %d, rtt_nom from vpd is %d, index is %d", + mss::c_str(iv_dimm), + l_rank, + l_rtt_nom[mss::index(l_rank)], + l_rtt_nom_index); // Map from RTT_NOM array to the value in the map l_decoder_val = rtt_nom_map[l_rtt_nom_index]; @@ -3384,8 +3469,7 @@ fapi2::ReturnCode eff_rdimm::dram_rtt_wr() FAPI_ASSERT( mss::find_value_from_key(l_rtt_wr_map, l_dram_rtt_wr[mss::index(l_rank)], l_encoding), fapi2::MSS_INVALID_RTT_WR() .set_RTT_WR(l_dram_rtt_wr[l_rank]) - .set_RANK(mss::index(l_rank)) - .set_DIMM_TARGET(iv_dimm), + .set_RANK(mss::index(l_rank)), "unknown RTT_WR 0x%x (%s rank %d), dynamic odt off", l_dram_rtt_wr[mss::index(l_rank)], mss::c_str(iv_dimm), @@ -3531,7 +3615,7 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc00() // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking // for mss::index 1. So this doesn't correspond directly with the table in the JEDEC spec, // as that's not in "denominator order." - // 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7 + // 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7 constexpr uint8_t rtt_nom_map[RTT_NOM_MAP_SIZE] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 }; // Temp holders to grab attributes to then parse into value for this dimm and rank @@ -3545,9 +3629,17 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc00() l_rtt_nom_index = (l_rtt_nom[l_rank] == 0) ? 0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_NOM_OHM240 / l_rtt_nom[l_rank]; - // Make sure it's a valid mss::index - // - fapi2::Assert( l_rtt_nom_index < RTT_NOM_MAP_SIZE); + // Make sure it's a valid index + FAPI_ASSERT( l_rtt_nom_index < RTT_NOM_MAP_SIZE, + fapi2::MSS_INVALID_RTT_NOM_CALCULATIONS() + .set_RANK(l_rank) + .set_RTT_NOM_INDEX(l_rtt_nom_index) + .set_RTT_NOM_FROM_VPD(l_rtt_nom[mss::index(l_rank)]), + "Error calculating RTT_NOM for target %s rank %d, rtt_nom from vpd is %d, index is %d", + mss::c_str(iv_dimm), + l_rank, + l_rtt_nom[mss::index(l_rank)], + l_rtt_nom_index); // Map from RTT_NOM array to the value in the map l_decoder_val = rtt_nom_map[l_rtt_nom_index]; @@ -3594,8 +3686,7 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc01() FAPI_ASSERT( mss::find_value_from_key(l_rtt_wr_map, l_dram_rtt_wr[l_rank], l_encoding), fapi2::MSS_INVALID_RTT_WR() .set_RTT_WR(l_dram_rtt_wr[l_rank]) - .set_RANK(mss::index(l_rank)) - .set_DIMM_TARGET(iv_dimm), + .set_RANK(mss::index(l_rank)), "unknown RTT_WR 0x%x (%s rank %d), dynamic odt off", l_dram_rtt_wr[mss::index(l_rank)], mss::c_str(iv_dimm), @@ -3968,13 +4059,14 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc0a() }; uint8_t l_attrs_dimm_bc0a[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; - FAPI_INF(" FREQ is %d enum is %d", iv_freq, fapi2::ENUM_ATTR_MSS_FREQ_MT2400); - FAPI_INF("%d", (iv_freq == fapi2::ENUM_ATTR_MSS_FREQ_MT2400)); + // Find the correct mapping from freq to encoding FAPI_ASSERT( mss::find_value_from_key(l_freq_map, uint64_t(iv_freq), l_encoding), - fapi2::MSS_INVALID_FREQ() - .set_FREQ(iv_freq), - "unknown FREQ %d for %s", + fapi2::MSS_INVALID_FREQ_BC() + .set_FREQ(iv_freq) + .set_BC_NUM(BC0A) + .set_TARGET(iv_dimm), + "unknown FREQ %d for %s in bc0a", iv_freq, mss::c_str(iv_dimm)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C index 57eaec10d..a6a396766 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,7 +29,7 @@ // *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com> // *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H index 2fc0d92fc..ea410dd5c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,7 +31,7 @@ // *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com> // *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C index 0120de737..aea2bfd64 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,7 +30,7 @@ // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H index d6fd5f408..9a6cbc4ab 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,7 +30,7 @@ // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_EFF_MEMORY_SIZE_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C index 6f3e2f6fe..ae50e8fdc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H index 7d0ad15d0..31726e8fc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_PLUG_RULES_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C index 82ef939d1..2e5cf9deb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,6 +22,13 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + + #include <fapi2.H> #include <mss.H> #include <lib/utils/find.H> @@ -90,6 +97,8 @@ fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, uint64_t& o_timing ) { uint64_t l_multiplier = 0; + uint64_t l_quotient = 0; + uint64_t l_remainder = 0; switch(i_temp_refresh_range) { @@ -105,19 +114,25 @@ fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, // Temperature Refresh Range will be a platform attribute set by the MRW, // which they "shouldn't" mess up as long as use "attribute" enums. // if someone messes this up we can at least catch it - FAPI_ERR( "Incorrect Temperature Ref. Range received: %d ", i_temp_refresh_range); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_TEMP_REFRESH() + .set_TEMP_REFRESH_RANGE(i_temp_refresh_range), + "Incorrect Temperature Ref. Range received: %d ", + i_temp_refresh_range); break; } - const uint64_t l_quotient = TREFI_BASE / ( int64_t(i_mode) * l_multiplier ); - const uint64_t l_remainder = TREFI_BASE % ( int64_t(i_mode) * l_multiplier ); + l_quotient = TREFI_BASE / ( int64_t(i_mode) * l_multiplier ); + l_remainder = TREFI_BASE % ( int64_t(i_mode) * l_multiplier ); o_timing = l_quotient + (l_remainder == 0 ? 0 : 1); FAPI_INF( "tREFI: %d, quotient: %d, remainder: %d, tREFI_base: %d", o_timing, l_quotient, l_remainder, TREFI_BASE ); + // FAPI_ASSERT doesn't set current error to good return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank) @@ -126,7 +141,8 @@ fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, /// @param[out] o_trfc_in_ps timing val in ps /// @return fapi2::FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode calc_trfc_dlr(const uint8_t i_refresh_mode, +fapi2::ReturnCode calc_trfc_dlr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_refresh_mode, const uint8_t i_density, uint64_t& o_trfc_in_ps) { @@ -153,18 +169,28 @@ fapi2::ReturnCode calc_trfc_dlr(const uint8_t i_refresh_mode, // Fine Refresh Mode will be a platform attribute set by the MRW, // which they "shouldn't" mess up as long as use "attribute" enums. // if openpower messes this up we can at least catch it - FAPI_ERR( "Incorrect Fine Refresh Mode received: %d ", i_refresh_mode); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FINE_REFRESH() + .set_REFRESH_MODE(i_refresh_mode), + "Incorrect Fine Refresh Mode received: %d ", + i_refresh_mode); break; }// switch - if(l_is_val_found) - { - return fapi2::FAPI2_RC_SUCCESS; - } - - FAPI_ERR("Unable to find tRFC (ps) from map with SDRAM density key %d", i_density); - return fapi2::FAPI2_RC_FALSE; + FAPI_ASSERT( l_is_val_found, + fapi2::MSS_FAILED_TO_FIND_TRFC() + .set_SDRAM_DENSITY(i_density) + .set_REFRESH_MODE(i_refresh_mode) + .set_TARGET(i_target), + "%s: Unable to find tRFC (ps) from map with SDRAM density key %d with %d refresh mode", + mss::c_str(i_target), + i_density, + i_refresh_mode); + + // Again, FAPI_ASSERT doesn't set current_err to good, only to bad + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } }// mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H index aa5320e3b..ce6415a32 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,7 +29,7 @@ // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_TIMING_H_ @@ -43,6 +43,24 @@ namespace mss { +/// +/// @brief Enums for ffdc error callout so we know which function had the error +/// +enum functions +{ + TRAS = 0, + TFAW_HALF_KB_PAGE_HELPER = 1, + TFAW_ONE_KB_PAGE_HELPER = 2, + TFAW_TW_KB_PAGE_HELPER = 3, + TFAW_SLR_X4_HELPER = 4, + TFAW_SLR_X8_HELPER = 5, + TRRD_S_SLR = 6, + TRRD_L_SLR = 7, + TRRD_L_HALF_AND_1KB_PAGE_HELPER = 8, + TRRD_S_HALF_AND_1KB_PAGE_HELPER = 9, + TRRD_S_2KB_PAGE_HELPER = 10, +}; + enum guard_band : uint16_t { // Used for caclulating spd timing values - from JEDEC rounding algorithm @@ -251,12 +269,14 @@ fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, /// /// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank) +/// @param[in] i_target a target for attributes /// @param[in] i_mode fine refresh rate mode /// @param[in] i_density SDRAM density /// @param[out] o_trfc_in_ps timing val in ps /// @return fapi2::FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode calc_trfc_dlr( const uint8_t i_refresh_mode, +fapi2::ReturnCode calc_trfc_dlr( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_refresh_mode, const uint8_t i_density, uint64_t& o_trfc_in_ps ); @@ -440,8 +460,6 @@ inline fapi2::ReturnCode dodt_on( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& o_dodt = l_cwl + l_al + l_ca_parity_latency - 2; FAPI_INF( "dodt_on %s %d", mss::c_str(i_target), o_dodt ); - return fapi2::FAPI2_RC_SUCCESS; - fapi_try_exit: return fapi2::current_err; } @@ -474,8 +492,6 @@ inline fapi2::ReturnCode max_dodt_on( const fapi2::Target<fapi2::TARGET_TYPE_MCA o_dodt = std::max(o_dodt, l_odt); } - return fapi2::FAPI2_RC_SUCCESS; - fapi_try_exit: return fapi2::current_err; } @@ -533,6 +549,7 @@ inline fapi2::ReturnCode fw_rd_wr( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: + FAPI_ERR("Error calculating the delay between a read and write command in memory clock cycles (fw_rd_wr"); return fapi2::current_err; } @@ -549,12 +566,10 @@ constexpr uint64_t trtp() /// /// @brief Return the minimum allowable tRAS in picoseconds -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s /// @param[in] i_target the fapi2 target /// @return value in picoseconds /// -template< fapi2::TargetType T > -inline uint64_t tras(const fapi2::Target<T>& i_target) +inline uint64_t tras(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) { uint64_t l_freq = 0; uint64_t l_tras = 0; @@ -578,7 +593,14 @@ inline uint64_t tras(const fapi2::Target<T>& i_target) break; default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TRAS) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); } return l_tras; @@ -642,7 +664,14 @@ static fapi2::ReturnCode tfaw_half_kb_page_helper(const fapi2::Target<T>& i_targ break; default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TFAW_HALF_KB_PAGE_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); } fapi_try_exit: @@ -689,7 +718,14 @@ static fapi2::ReturnCode tfaw_1kb_page_helper(const fapi2::Target<T>& i_target, break; default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TFAW_ONE_KB_PAGE_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); break; } @@ -735,7 +771,14 @@ static fapi2::ReturnCode tfaw_2kb_page_helper(const fapi2::Target<T>& i_target, break; default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TFAW_TW_KB_PAGE_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); break; } @@ -771,8 +814,13 @@ fapi2::ReturnCode tfaw( const fapi2::Target<T>& i_target, break; default: - FAPI_ERR("%s Recieved an invalid page size: %lu", mss::c_str(i_target), i_dram_width); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_DRAM_WIDTH() + .set_DRAM_WIDTH(i_dram_width) + .set_TARGET(i_target), + "Invalid DRAM width with %d for target %s", + i_dram_width, + mss::c_str(i_target)); break; } @@ -822,13 +870,24 @@ static fapi2::ReturnCode tfaw_slr_x4_helper(const fapi2::Target<T>& i_target, break; case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - FAPI_ERR("2666 MT/s is TBD from the DDR3 3DS spec"); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_SPEED_FOR_TSV() + .set_FREQ(l_freq) + .set_TARGET(i_target), + "%s 2666 MT/s is TBD from the DDR4 3DS (TSV) spec", + mss::c_str(i_target)); + break; default: - FAPI_ERR( "%s: Invalid frequency received (%d)", c_str(i_target), l_freq ); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TFAW_SLR_X4_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); break; } @@ -876,16 +935,27 @@ static fapi2::ReturnCode tfaw_slr_x8_helper(const fapi2::Target<T>& i_target, break; case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - FAPI_ERR("2666 MT/s is TBD from the DDR3 3DS spec"); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_SPEED_FOR_TSV() + .set_FREQ(l_freq) + .set_TARGET(i_target), + "%s 2666 MT/s is TBD from the DDR4 3DS (TSV) spec", + mss::c_str(i_target)); break; default: - FAPI_ERR( "%s: Invalid frequency received (%d)", c_str(i_target), l_freq ); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TFAW_SLR_X8_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); break; } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } @@ -981,16 +1051,29 @@ fapi2::ReturnCode trrd_s_slr(const fapi2::Target<T>& i_target, break; case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - FAPI_ERR("2666 MT/s is TBD from the DDR3 3DS spec"); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_SPEED_FOR_TSV() + .set_FREQ(l_freq) + .set_TARGET(i_target), + "%s 2666 MT/s is TBD from the DDR4 3DS (TSV) spec", + mss::c_str(i_target)); break; default: - FAPI_ERR( "%s: Invalid frequency received (%d)", c_str(i_target), l_freq ); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TRRD_S_SLR) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); + + break; } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } @@ -1035,16 +1118,27 @@ fapi2::ReturnCode trrd_l_slr(const fapi2::Target<T>& i_target, break; case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - FAPI_ERR("2666 MT/s is TBD from the DDR4 SPD spec"); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_SPEED_FOR_TSV() + .set_FREQ(l_freq) + .set_TARGET(i_target), + "%s 2666 MT/s is TBD from the DDR4 3DS (TSV) spec", + mss::c_str(i_target)); break; default: - FAPI_ERR( "%s: Invalid frequency received (%d)", c_str(i_target), l_freq ); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TRRD_L_SLR) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); break; } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } @@ -1091,9 +1185,17 @@ static fapi2::ReturnCode trrd_l_half_and_1kb_page_helper(const fapi2::Target<T>& break; default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TRRD_L_HALF_AND_1KB_PAGE_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } @@ -1162,7 +1264,7 @@ fapi2::ReturnCode trrd_l( const fapi2::Target<T>& i_target, { case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4: case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8: - FAPI_TRY( trrd_l_half_and_1kb_page_helper(i_target, o_tRRD_L) ); + FAPI_TRY( trrd_l_half_and_1kb_page_helper(i_target, o_tRRD_L), "Error calculating trrd l for half and 1kb page" ); break; case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X16: @@ -1170,11 +1272,17 @@ fapi2::ReturnCode trrd_l( const fapi2::Target<T>& i_target, break; default: - FAPI_ERR("%s Recieved an invalid page size: %lu", mss::c_str(i_target), i_dram_width); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_PAGE_SIZE() + .set_DRAM_WIDTH(i_dram_width) + .set_TARGET(i_target), + "%s Recieved an invalid page size: %lu", + mss::c_str(i_target), + i_dram_width); break; } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } @@ -1225,9 +1333,17 @@ static fapi2::ReturnCode trrd_s_half_and_1kb_page_helper(const fapi2::Target<T>& break; default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TRRD_S_HALF_AND_1KB_PAGE_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } @@ -1269,10 +1385,18 @@ static fapi2::ReturnCode trrd_s_2kb_page_helper(const fapi2::Target<T>& i_target break; default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); + FAPI_ASSERT( false, + fapi2::MSS_INVALID_FREQ_PASSED_IN() + .set_FREQ(l_freq) + .set_FUNCTION(TRRD_S_2KB_PAGE_HELPER) + .set_TARGET(i_target), + "%s Invalid frequency %lu", + mss::c_str(i_target), + l_freq); break; } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } @@ -1295,7 +1419,7 @@ fapi2::ReturnCode trrd_s( const fapi2::Target<T>& i_target, { case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4: case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8: - FAPI_TRY( trrd_s_half_and_1kb_page_helper(i_target, o_tRRD_S) ); + FAPI_TRY( trrd_s_half_and_1kb_page_helper(i_target, o_tRRD_S), "Error calculating trrd_s for half and 1kb page" ); break; case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X16: @@ -1303,11 +1427,17 @@ fapi2::ReturnCode trrd_s( const fapi2::Target<T>& i_target, break; default: - FAPI_ERR("%s Recieved an invalid page size: %lu", mss::c_str(i_target), i_dram_width); - return fapi2::FAPI2_RC_INVALID_PARAMETER; + FAPI_ASSERT( false, + fapi2::MSS_INVALID_PAGE_SIZE() + .set_DRAM_WIDTH(i_dram_width) + .set_TARGET(i_target), + "%s Recieved an invalid page size: %lu", + mss::c_str(i_target), + i_dram_width); break; } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H index 9e68f2f9a..b8a59c91b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/checker.H @@ -152,7 +152,7 @@ inline fapi2::ReturnCode fail_for_invalid_map(const fapi2::Target<fapi2::TARGET_ fapi2::MSS_INVALID_KEY(). set_KEY(i_key). set_DATA(i_data). - set_DIMM_TARGET(i_target), + set_TARGET(i_target), "%s. %s Could not find value from key %d. Returned data: %d.", c_str(i_target), i_err_str, diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml index 1506a618d..4d042fa81 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml @@ -44,12 +44,9 @@ </description> <ffdc>TEMP_REF_RANGE</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> </hwpError> <hwpError> @@ -69,6 +66,10 @@ </description> <ffdc>FINE_REF_MODE</ffdc> <ffdc>TEMP_REF_MODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> @@ -79,11 +80,15 @@ <ffdc>KEY</ffdc> <ffdc>DATA</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>DIMM_TARGET</target> + <target>TARGET</target> </deconfigure> </hwpError> @@ -125,12 +130,9 @@ <ffdc>MAX</ffdc> <ffdc>VALUE</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> </hwpError> <hwpError> @@ -140,13 +142,14 @@ </description> <ffdc>VALUE</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - </hwpError> + <callout> + <target>MCA_TARGET</target> + <priority>HIGH</priority> + </callout> +</hwpError> <hwpError> <rc>RC_MSS_INVALID_CAST_CALC_NCK</rc> @@ -155,11 +158,27 @@ <ffdc>NCK_NS</ffdc> <ffdc>CORRECTION_FACTOR</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_BAD_SDRAM_DENSITY_DECODER</rc> + <description> + SPD decoder messed up and returned a 0. Should have been caught already + </description> + <ffdc>DRAM_DENSITY</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>DIMM_TARGET</target> + <target>TARGET</target> </deconfigure> </hwpError> @@ -203,6 +222,18 @@ <ffdc>RTT_WR</ffdc> <ffdc>RANK</ffdc> <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_FREQ</rc> + <description> + An invalid Freq value has been set + </description> + <ffdc>FREQ</ffdc> + <callout> <target>DIMM_TARGET</target> <priority>HIGH</priority> </callout> @@ -212,17 +243,84 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_FREQ</rc> + <rc>RC_MSS_INVALID_FREQ_BC</rc> + <description> + An invalid Freq value has been set in Buffer Control functions + </description> + <ffdc>FREQ</ffdc> + <ffdc>BC_NUM</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_FREQ_RC</rc> + <description> + An invalid Freq value has been set in raw card functions + </description> + <ffdc>FREQ</ffdc> + <ffdc>RC_NUM</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_FREQ_PASSED_IN</rc> <description> An invalid Freq value has been set </description> <ffdc>FREQ</ffdc> + <ffdc>FUNCTION</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>DIMM_TARGET</target> + <childTargets> + <parent>TARGET</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_SPEED_FOR_TSV</rc> + <description> + As of 2/2017 no JEDEC timing values for 2666 3DS dram stack type + </description> + <ffdc>FREQ</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> </deconfigure> </hwpError> @@ -267,29 +365,125 @@ <ffdc>NUM_TOTAL_RANKS</ffdc> <ffdc>NUM_MASTER_RANKS</ffdc> <callout> - <target>DIMM_TARGET</target> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>DIMM_TARGET</target> + <target>TARGET</target> </deconfigure> </hwpError> <hwpError> - <rc>RC_MSS_INVALID_TOTAL_RANKS_FOR_3DS_DIMM</rc> + <rc>RC_MSS_INVALID_CALCULATED_DIMM_SIZE</rc> <description> - Somehow calculated the total (logical) ranks is greater than or equal to the number of master ranks - Even though the DIMM has slave ranks + Error calculating DIMM size </description> - <ffdc>NUM_SLAVE_RANKS</ffdc> - <ffdc>NUM_TOTAL_RANKS</ffdc> - <ffdc>NUM_MASTER_RANKS</ffdc> + <ffdc>SDRAM_WIDTH</ffdc> + <ffdc>BUS_WIDTH</ffdc> + <ffdc>DRAM_DENSITY</ffdc> + <ffdc>LOGICAL_RANKS</ffdc> <callout> - <target>DIMM_TARGET</target> + <target>TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>DIMM_TARGET</target> + <target>TARGET</target> </deconfigure> </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_TEMP_REFRESH</rc> + <description> + Incorrect Temperature Ref. Range received + </description> + <ffdc>TEMP_REFRESH_RANGE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_FINE_REFRESH</rc> + <description> + Incorrect FINE Refresh Mode received + </description> + <ffdc>REFRESH_MODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_FAILED_TO_FIND_TRFC</rc> + <description> + Unable to find tRFC (ps) from map with SDRAM density key + </description> + <ffdc>SDRAM_DENSITY</ffdc> + <ffdc>REFRESH_MODE</ffdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_PAGE_SIZE</rc> + <description> + Invalid page size + </description> + <ffdc>DRAM_WIDTH</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_DRAM_WIDTH</rc> + <description> + Code only supports x4 and x8 drams at this time + </description> + <ffdc>DRAM_WIDTH</ffdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_INVALID_RTT_NOM_CALCULATIONS</rc> + <description> + Calculated the rtt_nom_index into the VPD attribute incorrectly + </description> + <ffdc>RANK</ffdc> + <ffdc>RTT_NOM_INDEX</ffdc> + <ffdc>RTT_NOM_FROM_VPD</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml index 28883d6ef..3b7e47049 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml @@ -69,22 +69,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_DRAM_WIDTH</rc> - <description> - An invalid/unsupported DRAM width was received. This is possibly due - to SPD decoding errors or incorrect setting of ATTR_EFF_DRAM_WIDTH attribute. - </description> - <ffdc>DRAM_WIDTH</ffdc> - <callout> - <target>TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_RTT_WR_ENCODING</rc> <description> An invalid/unsupported RTT_WR encoding was received, possibly due to VPD error or bad |
