diff options
Diffstat (limited to 'src/import/chips/p9')
3 files changed, 49 insertions, 10 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C index 77eb285d8..da5111357 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C @@ -1979,7 +1979,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::vref_dq_train_value(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); uint8_t l_attrs_vref_dq_train_val[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; @@ -1988,13 +1987,32 @@ fapi2::ReturnCode eff_config::vref_dq_train_value(const fapi2::Target<TARGET_TYP const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); const auto l_dimm_num = index(i_target); + //value to set. + fapi2::buffer<uint8_t> l_vpd_value; + fapi2::buffer<uint8_t> l_train_value; + constexpr uint64_t VPD_TRAIN_VALUE_START = 2; + constexpr uint64_t VPD_TRAIN_VALUE_LEN = 6; + //Taken from DDR4 (this attribute is DDR4 only) spec MRS6 section VrefDQ training: values table + constexpr uint8_t JEDEC_MAX_TRAIN_VALUE = 0b00110010; + + FAPI_TRY(mss::vpd_mt_vref_dram_wr(i_target, l_vpd_value)); + l_vpd_value.extractToRight<VPD_TRAIN_VALUE_START, VPD_TRAIN_VALUE_LEN>(l_train_value); + + FAPI_ASSERT(l_train_value <= JEDEC_MAX_TRAIN_VALUE, + fapi2::MSS_INVALID_VPD_VREF_DRAM_WR_RANGE() + .set_MAX(JEDEC_MAX_TRAIN_VALUE) + .set_VALUE(l_train_value) + .set_DIMM_TARGET(i_target), + "%s VPD DRAM VREF value out of range max 0x%02x value 0x%02x", mss::c_str(i_target), + JEDEC_MAX_TRAIN_VALUE, l_train_value ); + // Attribute to set num dimm ranks is a pre-requisite FAPI_TRY( eff_vref_dq_train_value(l_mcs, &l_attrs_vref_dq_train_val[0][0][0]) ); FAPI_TRY( mss::ranks(i_target, l_ranks) ); for(const auto& l_rank : l_ranks) { - l_attrs_vref_dq_train_val[l_port_num][l_dimm_num][index(l_rank)] = 0x10; + l_attrs_vref_dq_train_val[l_port_num][l_dimm_num][index(l_rank)] = l_train_value; } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_VREF_DQ_TRAIN_VALUE, l_mcs, l_attrs_vref_dq_train_val), @@ -2004,7 +2022,6 @@ fapi_try_exit: return fapi2::current_err; } - /// /// @brief Determines & sets effective config for Vref DQ Train Enable /// @param[in] i_target FAPI2 target @@ -2012,7 +2029,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::vref_dq_train_enable(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + //Default mode for train enable should be normal operation mode - 0x00 const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); uint8_t l_attrs_vref_dq_train_enable[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; @@ -2037,7 +2054,6 @@ fapi_try_exit: return fapi2::current_err; } - /// /// @brief Determines & sets effective config for Vref DQ Train Range /// @param[in] i_target FAPI2 target @@ -2045,7 +2061,6 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::vref_dq_train_range(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); // Attribute to set num dimm ranks is a pre-requisite @@ -2055,12 +2070,20 @@ fapi2::ReturnCode eff_config::vref_dq_train_range(const fapi2::Target<TARGET_TYP const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); const auto l_dimm_num = index(i_target); + //value to set. + fapi2::buffer<uint8_t> l_vpd_value; + fapi2::buffer<uint8_t> l_train_range; + constexpr uint64_t VPD_TRAIN_RANGE_START = 1; + FAPI_TRY(mss::vpd_mt_vref_dram_wr(i_target, l_vpd_value)); + l_train_range = l_vpd_value.getBit<VPD_TRAIN_RANGE_START>(); + + //gets the current value of train_range FAPI_TRY( eff_vref_dq_train_range(l_mcs, &l_attrs_vref_dq_train_range[0][0][0]) ); FAPI_TRY( mss::ranks(i_target, l_ranks) ); for(const auto& l_rank : l_ranks) { - l_attrs_vref_dq_train_range[l_port_num][l_dimm_num][index(l_rank)] = 0x00; + l_attrs_vref_dq_train_range[l_port_num][l_dimm_num][index(l_rank)] = l_train_range; } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_VREF_DQ_TRAIN_RANGE, l_mcs, l_attrs_vref_dq_train_range), diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index f0e22fa98..181995b20 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -56,6 +56,9 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> std::map<uint32_t, std::shared_ptr<mss::spd::decoder> > l_factory_caches; FAPI_TRY( mss::spd::populate_decoder_caches(i_target, l_factory_caches) ); + // Decode the VPD for this MCS and stick it in the attributes. + FAPI_TRY( l_eff_config.decode_vpd(i_target) ); + for( const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) ) { const auto l_dimm_pos = mss::pos(l_dimm); @@ -220,9 +223,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> }// dimm - // Decode the VPD for this MCS and stick it in the attributes. - FAPI_TRY( l_eff_config.decode_vpd(i_target) ); - fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml index edcb02520..4bb33c98c 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml @@ -84,4 +84,20 @@ </deconfigure> </hwpError> + <hwpError> + <rc>RC_MSS_INVALID_VPD_VREF_DRAM_WR_RANGE</rc> + <description> + Value in the VPD for VREF dram WR range is outside of the JEDEC spec's range. + </description> + <ffdc>MAX</ffdc> + <ffdc>VALUE</ffdc> + <callout> + <target>DIMM_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>DIMM_TARGET</target> + </deconfigure> + </hwpError> + </hwpErrors> |
