diff options
Diffstat (limited to 'src/import/chips/p9')
7 files changed, 178 insertions, 1408 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H index b135f16b0..ef2dfd9ce 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H @@ -82,7 +82,8 @@ class mcbistTraits<fapi2::TARGET_TYPE_MCBIST> static constexpr uint64_t MCBSTATQ_REG = MCBIST_MCBSTATQ; static constexpr uint64_t MCBPARMQ_REG = MCBIST_MCBPARMQ; static constexpr uint64_t MCBAGRAQ_REG = MCBIST_MCBAGRAQ; - static constexpr uint64_t SRERR_REG = MCBIST_MBSEC1Q; + static constexpr uint64_t SRERR0_REG = MCBIST_MBSEC0Q; + static constexpr uint64_t SRERR1_REG = MCBIST_MBSEC1Q; static constexpr uint64_t THRESHOLD_REG = MCBIST_MBSTRQ; static constexpr uint64_t FIRQ_REG = MCBIST_MCBISTFIRQ; static constexpr uint64_t LAST_ADDR_REG = MCBIST_MCBMCATQ; @@ -198,6 +199,8 @@ class mcbistTraits<fapi2::TARGET_TYPE_MCBIST> LOGGED_ERROR_ON_PORT_INDICATOR = MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR, LOGGED_ERROR_ON_PORT_INDICATOR_LEN = MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN, + SUBTEST_NUM_INDICATOR = MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR, + SUBTEST_NUM_INDICATOR_LEN = MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN, UE_COUNT = MCBIST_MBSEC1Q_UE_COUNT, UE_COUNT_LEN = MCBIST_MBSEC1Q_UE_COUNT_LEN, @@ -1030,41 +1033,38 @@ class program /// inline fapi2::ReturnCode process_errors( const fapi2::Target<T> i_target ) const { - // TK: Check for more detailed errors - // Until reading the error array is documented, comparison errors 'just' result in // a flag indicating there was a problem on port. { fapi2::buffer<uint64_t> l_data; - uint64_t l_read = 0; + uint64_t l_port = 0; + uint64_t l_subtest = 0; FAPI_TRY( mss::getScom(i_target, TT::MCBSTATQ_REG, l_data) ); - l_data.extractToRight<TT::LOGGED_ERROR_ON_PORT_INDICATOR, TT::LOGGED_ERROR_ON_PORT_INDICATOR_LEN>(l_read); + l_data.extractToRight<TT::LOGGED_ERROR_ON_PORT_INDICATOR, TT::LOGGED_ERROR_ON_PORT_INDICATOR_LEN>(l_port); + l_data.extractToRight<TT::SUBTEST_NUM_INDICATOR, TT::SUBTEST_NUM_INDICATOR_LEN>(l_subtest); - FAPI_ASSERT( l_read == 0, + FAPI_ASSERT( l_port == 0, fapi2::MSS_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN() .set_TARGET(i_target) - .set_PORT(mss::first_bit_set(l_read)), - "MCBIST error on port %d", mss::first_bit_set(l_read) ); + .set_PORT(mss::first_bit_set(l_port)) + .set_SUBTEST(l_subtest), + "MCBIST error on port %d subtest %d", mss::first_bit_set(l_port), l_subtest ); } // Check for UE errors { - fapi2::buffer<uint64_t> l_data; - uint64_t l_read = 0; - FAPI_TRY( mss::getScom(i_target, TT::SRERR_REG, l_data) ); - - // For now, lets catch anything in the scrub/read error reg - not just UE -#ifdef CATCH_UE_ONLY - l_data.extractToRight<TT::UE_COUNT, TT::UE_COUNT_LEN>(l_read); -#else - l_read = l_data; -#endif + fapi2::buffer<uint64_t> l_read0; + fapi2::buffer<uint64_t> l_read1; + + FAPI_TRY( mss::getScom(i_target, TT::SRERR0_REG, l_read0) ); + FAPI_TRY( mss::getScom(i_target, TT::SRERR1_REG, l_read1) ); - FAPI_ASSERT( l_read == 0, + FAPI_ASSERT( ((l_read0 == 0) && (l_read1 == 0)), fapi2::MSS_MEMDIAGS_UE_OR_SUE_IN_LAST_PATTERN() .set_TARGET(i_target) - .set_STATUS(l_read), - "MCBIST scrub/read error 0x%016lx", l_read ); + .set_STATUS0(l_read0) + .set_STATUS1(l_read1), + "MCBIST scrub/read error reg0: 0x%016lx reg1: 0x%016lx", l_read0, l_read1 ); } FAPI_INF("Execution success - no errors seen from MCBIST program"); @@ -1427,7 +1427,8 @@ inline fapi2::ReturnCode clear_errors( const fapi2::Target<T> i_target ) // TK: Clear the more detailed errors checked above FAPI_INF("Clear MCBIST error state"); FAPI_TRY( mss::putScom(i_target, TT::MCBSTATQ_REG, 0) ); - FAPI_TRY( mss::putScom(i_target, TT::SRERR_REG, 0) ); + FAPI_TRY( mss::putScom(i_target, TT::SRERR0_REG, 0) ); + FAPI_TRY( mss::putScom(i_target, TT::SRERR1_REG, 0) ); FAPI_TRY( mss::putScom(i_target, TT::FIRQ_REG, 0) ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 9ccedfb2e..9c9b04eaa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -501,11 +501,11 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC l_err_data.extractToRight<TT::INIT_CAL_ERROR_WR_LEVEL, TT::CAL_ERROR_FIELD_LEN>(l_errors); l_err_data.extractToRight<TT::INIT_CAL_ERROR_RANK_PAIR, TT::INIT_CAL_ERROR_RANK_PAIR_LEN>(l_rank_pairs); - FAPI_DBG("initial cal err: 0x%016llx, rp: 0x%016llx (0x%016llx)", l_errors, l_rank_pairs, uint64_t(l_err_data)); + FAPI_INF("initial cal err: 0x%016llx, rp: 0x%016llx (0x%016llx)", l_errors, l_rank_pairs, uint64_t(l_err_data)); if ((l_rank_pairs == 0) || (l_errors == 0)) { - FAPI_DBG("Initial cal - no errors reported"); + FAPI_INF("Initial cal - no errors reported"); return fapi2::current_err; } @@ -1083,1338 +1083,5 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Dump the registers of the PHY (MCA) -/// @param[in] i_target the MCA target -/// @return fapi2::FAPI2_RC_SUCCESS if ok -/// -template<> -fapi2::ReturnCode dump_regs( const fapi2::Target<TARGET_TYPE_MCA>& i_target ) -{ - // To generate this vector: - // grep MCA_DDRPHY chips/p9/common/include/p9_mc_scom_addresses.H | awk '{ print "{\42" $2 "\42,", $2, "}," }' - static const std::vector< std::pair<char const*, uint64_t> > l_registers = - { - {"MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0", MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0 }, - {"MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1", MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1 }, - {"MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2", MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2 }, - {"MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3", MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0", MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1", MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DELAY0_P0_ADR0", MCA_DDRPHY_ADR_DELAY0_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY0_P0_ADR1", MCA_DDRPHY_ADR_DELAY0_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY0_P0_ADR2", MCA_DDRPHY_ADR_DELAY0_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY0_P0_ADR3", MCA_DDRPHY_ADR_DELAY0_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DELAY1_P0_ADR0", MCA_DDRPHY_ADR_DELAY1_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY1_P0_ADR1", MCA_DDRPHY_ADR_DELAY1_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY1_P0_ADR2", MCA_DDRPHY_ADR_DELAY1_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY1_P0_ADR3", MCA_DDRPHY_ADR_DELAY1_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DELAY2_P0_ADR0", MCA_DDRPHY_ADR_DELAY2_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY2_P0_ADR1", MCA_DDRPHY_ADR_DELAY2_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY2_P0_ADR2", MCA_DDRPHY_ADR_DELAY2_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY2_P0_ADR3", MCA_DDRPHY_ADR_DELAY2_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DELAY3_P0_ADR0", MCA_DDRPHY_ADR_DELAY3_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY3_P0_ADR1", MCA_DDRPHY_ADR_DELAY3_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY3_P0_ADR2", MCA_DDRPHY_ADR_DELAY3_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY3_P0_ADR3", MCA_DDRPHY_ADR_DELAY3_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DELAY4_P0_ADR0", MCA_DDRPHY_ADR_DELAY4_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY4_P0_ADR1", MCA_DDRPHY_ADR_DELAY4_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY4_P0_ADR2", MCA_DDRPHY_ADR_DELAY4_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY4_P0_ADR3", MCA_DDRPHY_ADR_DELAY4_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DELAY5_P0_ADR0", MCA_DDRPHY_ADR_DELAY5_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY5_P0_ADR1", MCA_DDRPHY_ADR_DELAY5_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY5_P0_ADR2", MCA_DDRPHY_ADR_DELAY5_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY5_P0_ADR3", MCA_DDRPHY_ADR_DELAY5_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DELAY6_P0_ADR0", MCA_DDRPHY_ADR_DELAY6_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY6_P0_ADR1", MCA_DDRPHY_ADR_DELAY6_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY6_P0_ADR2", MCA_DDRPHY_ADR_DELAY6_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY6_P0_ADR3", MCA_DDRPHY_ADR_DELAY6_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DELAY7_P0_ADR0", MCA_DDRPHY_ADR_DELAY7_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DELAY7_P0_ADR1", MCA_DDRPHY_ADR_DELAY7_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DELAY7_P0_ADR2", MCA_DDRPHY_ADR_DELAY7_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DELAY7_P0_ADR3", MCA_DDRPHY_ADR_DELAY7_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0", MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1", MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2", MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3", MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0", MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0 }, - {"MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1", MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1 }, - {"MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2", MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 }, - {"MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3", MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3 }, - {"MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0", MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1", MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2 }, - {"MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3", MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2 }, - {"MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3", MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3 }, - {"MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0", MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1", MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0", MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1", MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0", MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1", MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0", MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1", MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0", MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0 }, - {"MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1", MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1 }, - {"MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2", MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2 }, - {"MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3", MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3 }, - {"MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0", MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1", MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0", MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1", MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 }, - {"MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0", MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0 }, - {"MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1", MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1 }, - {"MCA_DDRPHY_APB_ATEST_MUX_SEL_P0", MCA_DDRPHY_APB_ATEST_MUX_SEL_P0 }, - {"MCA_DDRPHY_APB_CONFIG0_P0", MCA_DDRPHY_APB_CONFIG0_P0 }, - {"MCA_DDRPHY_APB_ERROR_MASK0_P0", MCA_DDRPHY_APB_ERROR_MASK0_P0 }, - {"MCA_DDRPHY_APB_ERROR_STATUS0_P0", MCA_DDRPHY_APB_ERROR_STATUS0_P0 }, - {"MCA_DDRPHY_APB_FIR_ERR0_P0", MCA_DDRPHY_APB_FIR_ERR0_P0 }, - {"MCA_DDRPHY_APB_FIR_ERR1_P0", MCA_DDRPHY_APB_FIR_ERR1_P0 }, - {"MCA_DDRPHY_APB_FIR_ERR2_P0", MCA_DDRPHY_APB_FIR_ERR2_P0 }, - {"MCA_DDRPHY_APB_FIR_ERR3_P0", MCA_DDRPHY_APB_FIR_ERR3_P0 }, - {"MCA_DDRPHY_APB_LO_PROBE_SEL_P0", MCA_DDRPHY_APB_LO_PROBE_SEL_P0 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3 }, - {"MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4", MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0", MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1", MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2", MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3", MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4", MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0", MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1", MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2", MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3", MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3 }, - {"MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4", MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4", MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0", MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1", MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2", MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3", MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4", MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0", MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1", MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2", MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3", MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3 }, - {"MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4", MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0", MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1", MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2", MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3", MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4", MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0", MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1", MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2", MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3", MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3 }, - {"MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4", MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4 }, - {"MCA_DDRPHY_DP16_DEBUG_SEL_P0_0", MCA_DDRPHY_DP16_DEBUG_SEL_P0_0 }, - {"MCA_DDRPHY_DP16_DEBUG_SEL_P0_1", MCA_DDRPHY_DP16_DEBUG_SEL_P0_1 }, - {"MCA_DDRPHY_DP16_DEBUG_SEL_P0_2", MCA_DDRPHY_DP16_DEBUG_SEL_P0_2 }, - {"MCA_DDRPHY_DP16_DEBUG_SEL_P0_3", MCA_DDRPHY_DP16_DEBUG_SEL_P0_3 }, - {"MCA_DDRPHY_DP16_DEBUG_SEL_P0_4", MCA_DDRPHY_DP16_DEBUG_SEL_P0_4 }, - {"MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0", MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0 }, - {"MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1", MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1 }, - {"MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2", MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2 }, - {"MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3", MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3 }, - {"MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4", MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4 }, - {"MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0", MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0 }, - {"MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1", MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1 }, - {"MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2", MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2 }, - {"MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3", MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3 }, - {"MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4", MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4 }, - {"MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0", MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0 }, - {"MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1", MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1 }, - {"MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2", MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2 }, - {"MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3", MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3 }, - {"MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4", MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_CNTL0_P0_0", MCA_DDRPHY_DP16_DLL_CNTL0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_CNTL0_P0_1", MCA_DDRPHY_DP16_DLL_CNTL0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_CNTL0_P0_2", MCA_DDRPHY_DP16_DLL_CNTL0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_CNTL0_P0_3", MCA_DDRPHY_DP16_DLL_CNTL0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_CNTL0_P0_4", MCA_DDRPHY_DP16_DLL_CNTL0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_CNTL1_P0_0", MCA_DDRPHY_DP16_DLL_CNTL1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_CNTL1_P0_1", MCA_DDRPHY_DP16_DLL_CNTL1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_CNTL1_P0_2", MCA_DDRPHY_DP16_DLL_CNTL1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_CNTL1_P0_3", MCA_DDRPHY_DP16_DLL_CNTL1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_CNTL1_P0_4", MCA_DDRPHY_DP16_DLL_CNTL1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0", MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1", MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2", MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3", MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4", MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0", MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1", MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2", MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3", MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4", MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0", MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1", MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2", MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3", MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4", MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0", MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1", MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2", MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3", MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4", MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0", MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1", MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2", MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3", MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4", MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4", MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0", MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1", MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2", MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3", MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4", MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0", MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1", MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2", MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3", MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4", MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0", MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1", MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2", MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3", MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4", MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0", MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1", MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2", MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3", MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4", MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0", MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1", MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2", MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3", MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4", MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0", MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1", MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2", MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3", MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3 }, - {"MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4", MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0", MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1", MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2", MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3", MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4", MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4", MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3 }, - {"MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4", MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4 }, - {"MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0", MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0 }, - {"MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1", MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1 }, - {"MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2", MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2 }, - {"MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3", MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3 }, - {"MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4", MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0", MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0 }, - {"MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1", MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1 }, - {"MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2", MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2 }, - {"MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3", MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3 }, - {"MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4", MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4 }, - {"MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0", MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0 }, - {"MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1", MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1 }, - {"MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2", MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2 }, - {"MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3", MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3 }, - {"MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4", MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4 }, - {"MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0", MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0 }, - {"MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1", MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1 }, - {"MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2", MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2 }, - {"MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3", MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3 }, - {"MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4", MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4 }, - {"MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0", MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0 }, - {"MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1", MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1 }, - {"MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2", MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2 }, - {"MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3", MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3 }, - {"MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4", MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0", MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1", MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2", MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3", MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4", MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0", MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1", MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2", MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3", MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4", MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0", MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1", MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2", MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3", MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3 }, - {"MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4", MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0", MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1", MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2", MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3", MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4", MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0", MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1", MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2", MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3", MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4", MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0", MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1", MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2", MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3", MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4", MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0", MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1", MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2", MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3", MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4", MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0", MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1", MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2", MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3", MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4", MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0", MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1", MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2", MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3", MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3 }, - {"MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4", MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4 }, - {"MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0", MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0 }, - {"MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1", MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1 }, - {"MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2", MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2 }, - {"MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3", MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3 }, - {"MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4", MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0", MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1", MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2", MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3", MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4", MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_0", MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_0 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_1", MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_1 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_2", MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_2 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_3", MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_3 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_4", MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_4 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0", MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1", MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2", MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3", MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4", MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_0", MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_0 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_1", MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_1 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_2", MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_2 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_3", MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_3 }, - {"MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_4", MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_4 }, - {"MCA_DDRPHY_DP16_RD_STATUS0_P0_0", MCA_DDRPHY_DP16_RD_STATUS0_P0_0 }, - {"MCA_DDRPHY_DP16_RD_STATUS0_P0_1", MCA_DDRPHY_DP16_RD_STATUS0_P0_1 }, - {"MCA_DDRPHY_DP16_RD_STATUS0_P0_2", MCA_DDRPHY_DP16_RD_STATUS0_P0_2 }, - {"MCA_DDRPHY_DP16_RD_STATUS0_P0_3", MCA_DDRPHY_DP16_RD_STATUS0_P0_3 }, - {"MCA_DDRPHY_DP16_RD_STATUS0_P0_4", MCA_DDRPHY_DP16_RD_STATUS0_P0_4 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0", MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1", MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2", MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3", MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4", MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0", MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1", MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2", MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3", MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3 }, - {"MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4", MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0", MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1", MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2", MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3", MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4", MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0", MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1", MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2", MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3", MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3 }, - {"MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4", MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4 }, - {"MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0", MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0 }, - {"MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1", MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1 }, - {"MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2", MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2 }, - {"MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3", MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3 }, - {"MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4", MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0", MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0 }, - {"MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1", MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1 }, - {"MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2", MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2 }, - {"MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3", MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3 }, - {"MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4", MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0 }, - 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{"MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0 }, - 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{"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3 }, - {"MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4", MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4 }, - {"MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0", MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0 }, - {"MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1", MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1 }, - {"MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2", MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2 }, - {"MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3", MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3 }, - {"MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4", MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0", MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1", MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2", MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3", MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4", MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0", MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1", MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2", MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3", MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4", MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0", MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1", MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2", MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3", MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3 }, - {"MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4", MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0", MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1", MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2", MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3", MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4", MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0", MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1", MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2", MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3", MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4", MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0", MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1", MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2", MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3", MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4", MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0", MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1", MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2", MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3", MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3 }, - {"MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4", MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4 }, - {"MCA_DDRPHY_DP16_WRCLK_PR_P0_0", MCA_DDRPHY_DP16_WRCLK_PR_P0_0 }, - {"MCA_DDRPHY_DP16_WRCLK_PR_P0_1", MCA_DDRPHY_DP16_WRCLK_PR_P0_1 }, - {"MCA_DDRPHY_DP16_WRCLK_PR_P0_2", MCA_DDRPHY_DP16_WRCLK_PR_P0_2 }, - {"MCA_DDRPHY_DP16_WRCLK_PR_P0_3", MCA_DDRPHY_DP16_WRCLK_PR_P0_3 }, - {"MCA_DDRPHY_DP16_WRCLK_PR_P0_4", MCA_DDRPHY_DP16_WRCLK_PR_P0_4 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3 }, - {"MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4 }, - {"MCA_DDRPHY_DP16_WR_ERROR0_P0_0", MCA_DDRPHY_DP16_WR_ERROR0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_ERROR0_P0_1", MCA_DDRPHY_DP16_WR_ERROR0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_ERROR0_P0_2", MCA_DDRPHY_DP16_WR_ERROR0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_ERROR0_P0_3", MCA_DDRPHY_DP16_WR_ERROR0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_ERROR0_P0_4", MCA_DDRPHY_DP16_WR_ERROR0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0", MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1", MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2", MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3", MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4", MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0", MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1", MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2", MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3", MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4", MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0", MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1", MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2", MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3", MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4", MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0", MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1", MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2", MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3", MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4", MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0", MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1", MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2", MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3", MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4", MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4", MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0", MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1", MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2", MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3", MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4", MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0", MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1", MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2", MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3", MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4", MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3 }, - {"MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4", MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 }, - {"MCA_DDRPHY_PC_BASE_CNTR0_P0", MCA_DDRPHY_PC_BASE_CNTR0_P0 }, - {"MCA_DDRPHY_PC_BASE_CNTR1_P0", MCA_DDRPHY_PC_BASE_CNTR1_P0 }, - {"MCA_DDRPHY_PC_CAL_TIMER_P0", MCA_DDRPHY_PC_CAL_TIMER_P0 }, - {"MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0", MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0 }, - {"MCA_DDRPHY_PC_CONFIG0_P0", MCA_DDRPHY_PC_CONFIG0_P0 }, - {"MCA_DDRPHY_PC_CONFIG1_P0", MCA_DDRPHY_PC_CONFIG1_P0 }, - {"MCA_DDRPHY_PC_CSID_CFG_P0", MCA_DDRPHY_PC_CSID_CFG_P0 }, - {"MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0", MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0 }, - {"MCA_DDRPHY_PC_ERROR_MASK0_P0", MCA_DDRPHY_PC_ERROR_MASK0_P0 }, - {"MCA_DDRPHY_PC_ERROR_STATUS0_P0", MCA_DDRPHY_PC_ERROR_STATUS0_P0 }, - {"MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0", MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0 }, - {"MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0", MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0 }, - {"MCA_DDRPHY_PC_INIT_CAL_ERROR_P0", MCA_DDRPHY_PC_INIT_CAL_ERROR_P0 }, - {"MCA_DDRPHY_PC_INIT_CAL_MASK_P0", MCA_DDRPHY_PC_INIT_CAL_MASK_P0 }, - {"MCA_DDRPHY_PC_INIT_CAL_STATUS_P0", MCA_DDRPHY_PC_INIT_CAL_STATUS_P0 }, - {"MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0", MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 }, - {"MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0", MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0 }, - {"MCA_DDRPHY_PC_MR0_PRI_RP0_P0", MCA_DDRPHY_PC_MR0_PRI_RP0_P0 }, - {"MCA_DDRPHY_PC_MR0_PRI_RP1_P0", MCA_DDRPHY_PC_MR0_PRI_RP1_P0 }, - {"MCA_DDRPHY_PC_MR0_PRI_RP2_P0", MCA_DDRPHY_PC_MR0_PRI_RP2_P0 }, - {"MCA_DDRPHY_PC_MR0_PRI_RP3_P0", MCA_DDRPHY_PC_MR0_PRI_RP3_P0 }, - {"MCA_DDRPHY_PC_MR0_SEC_RP0_P0", MCA_DDRPHY_PC_MR0_SEC_RP0_P0 }, - {"MCA_DDRPHY_PC_MR0_SEC_RP1_P0", MCA_DDRPHY_PC_MR0_SEC_RP1_P0 }, - {"MCA_DDRPHY_PC_MR0_SEC_RP2_P0", MCA_DDRPHY_PC_MR0_SEC_RP2_P0 }, - {"MCA_DDRPHY_PC_MR0_SEC_RP3_P0", MCA_DDRPHY_PC_MR0_SEC_RP3_P0 }, - {"MCA_DDRPHY_PC_MR1_PRI_RP0_P0", MCA_DDRPHY_PC_MR1_PRI_RP0_P0 }, - {"MCA_DDRPHY_PC_MR1_PRI_RP1_P0", MCA_DDRPHY_PC_MR1_PRI_RP1_P0 }, - {"MCA_DDRPHY_PC_MR1_PRI_RP2_P0", MCA_DDRPHY_PC_MR1_PRI_RP2_P0 }, - {"MCA_DDRPHY_PC_MR1_PRI_RP3_P0", MCA_DDRPHY_PC_MR1_PRI_RP3_P0 }, - {"MCA_DDRPHY_PC_MR1_SEC_RP0_P0", MCA_DDRPHY_PC_MR1_SEC_RP0_P0 }, - {"MCA_DDRPHY_PC_MR1_SEC_RP1_P0", MCA_DDRPHY_PC_MR1_SEC_RP1_P0 }, - {"MCA_DDRPHY_PC_MR1_SEC_RP2_P0", MCA_DDRPHY_PC_MR1_SEC_RP2_P0 }, - {"MCA_DDRPHY_PC_MR1_SEC_RP3_P0", MCA_DDRPHY_PC_MR1_SEC_RP3_P0 }, - {"MCA_DDRPHY_PC_MR2_PRI_RP0_P0", MCA_DDRPHY_PC_MR2_PRI_RP0_P0 }, - {"MCA_DDRPHY_PC_MR2_PRI_RP1_P0", MCA_DDRPHY_PC_MR2_PRI_RP1_P0 }, - {"MCA_DDRPHY_PC_MR2_PRI_RP2_P0", MCA_DDRPHY_PC_MR2_PRI_RP2_P0 }, - {"MCA_DDRPHY_PC_MR2_PRI_RP3_P0", MCA_DDRPHY_PC_MR2_PRI_RP3_P0 }, - {"MCA_DDRPHY_PC_MR2_SEC_RP0_P0", MCA_DDRPHY_PC_MR2_SEC_RP0_P0 }, - {"MCA_DDRPHY_PC_MR2_SEC_RP1_P0", MCA_DDRPHY_PC_MR2_SEC_RP1_P0 }, - {"MCA_DDRPHY_PC_MR2_SEC_RP2_P0", MCA_DDRPHY_PC_MR2_SEC_RP2_P0 }, - {"MCA_DDRPHY_PC_MR2_SEC_RP3_P0", MCA_DDRPHY_PC_MR2_SEC_RP3_P0 }, - {"MCA_DDRPHY_PC_MR3_PRI_RP0_P0", MCA_DDRPHY_PC_MR3_PRI_RP0_P0 }, - {"MCA_DDRPHY_PC_MR3_PRI_RP1_P0", MCA_DDRPHY_PC_MR3_PRI_RP1_P0 }, - {"MCA_DDRPHY_PC_MR3_PRI_RP2_P0", MCA_DDRPHY_PC_MR3_PRI_RP2_P0 }, - {"MCA_DDRPHY_PC_MR3_PRI_RP3_P0", MCA_DDRPHY_PC_MR3_PRI_RP3_P0 }, - {"MCA_DDRPHY_PC_MR3_SEC_RP0_P0", MCA_DDRPHY_PC_MR3_SEC_RP0_P0 }, - {"MCA_DDRPHY_PC_MR3_SEC_RP1_P0", MCA_DDRPHY_PC_MR3_SEC_RP1_P0 }, - {"MCA_DDRPHY_PC_MR3_SEC_RP2_P0", MCA_DDRPHY_PC_MR3_SEC_RP2_P0 }, - {"MCA_DDRPHY_PC_MR3_SEC_RP3_P0", MCA_DDRPHY_PC_MR3_SEC_RP3_P0 }, - {"MCA_DDRPHY_PC_PER_CAL_CONFIG_P0", MCA_DDRPHY_PC_PER_CAL_CONFIG_P0 }, - {"MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0", MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 }, - {"MCA_DDRPHY_PC_POWERDOWN_1_P0", MCA_DDRPHY_PC_POWERDOWN_1_P0 }, - {"MCA_DDRPHY_PC_RANK_GROUP_EXT_P0", MCA_DDRPHY_PC_RANK_GROUP_EXT_P0 }, - {"MCA_DDRPHY_PC_RANK_GROUP_P0", MCA_DDRPHY_PC_RANK_GROUP_P0 }, - {"MCA_DDRPHY_PC_RANK_PAIR0_P0", MCA_DDRPHY_PC_RANK_PAIR0_P0 }, - {"MCA_DDRPHY_PC_RANK_PAIR1_P0", MCA_DDRPHY_PC_RANK_PAIR1_P0 }, - {"MCA_DDRPHY_PC_RANK_PAIR2_P0", MCA_DDRPHY_PC_RANK_PAIR2_P0 }, - {"MCA_DDRPHY_PC_RANK_PAIR3_P0", MCA_DDRPHY_PC_RANK_PAIR3_P0 }, - {"MCA_DDRPHY_PC_RELOAD_VALUE0_P0", MCA_DDRPHY_PC_RELOAD_VALUE0_P0 }, - {"MCA_DDRPHY_PC_RESETS_P0", MCA_DDRPHY_PC_RESETS_P0 }, - {"MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0", MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0 }, - {"MCA_DDRPHY_PC_ZCAL_TIMER_P0", MCA_DDRPHY_PC_ZCAL_TIMER_P0 }, - {"MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0", MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 }, - {"MCA_DDRPHY_RC_CONFIG0_P0", MCA_DDRPHY_RC_CONFIG0_P0 }, - {"MCA_DDRPHY_RC_CONFIG1_P0", MCA_DDRPHY_RC_CONFIG1_P0 }, - {"MCA_DDRPHY_RC_CONFIG2_P0", MCA_DDRPHY_RC_CONFIG2_P0 }, - {"MCA_DDRPHY_RC_CONFIG3_P0", MCA_DDRPHY_RC_CONFIG3_P0 }, - {"MCA_DDRPHY_RC_ERROR_MASK0_P0", MCA_DDRPHY_RC_ERROR_MASK0_P0 }, - {"MCA_DDRPHY_RC_ERROR_STATUS0_P0", MCA_DDRPHY_RC_ERROR_STATUS0_P0 }, - {"MCA_DDRPHY_RC_RDVREF_CONFIG0_P0", MCA_DDRPHY_RC_RDVREF_CONFIG0_P0 }, - {"MCA_DDRPHY_RC_RDVREF_CONFIG1_P0", MCA_DDRPHY_RC_RDVREF_CONFIG1_P0 }, - {"MCA_DDRPHY_SEQ_CONFIG0_P0", MCA_DDRPHY_SEQ_CONFIG0_P0 }, - {"MCA_DDRPHY_SEQ_ERROR_MASK0_P0", MCA_DDRPHY_SEQ_ERROR_MASK0_P0 }, - {"MCA_DDRPHY_SEQ_ERROR_STATUS0_P0", MCA_DDRPHY_SEQ_ERROR_STATUS0_P0 }, - {"MCA_DDRPHY_SEQ_LPT_ADDR2_P0", MCA_DDRPHY_SEQ_LPT_ADDR2_P0 }, - {"MCA_DDRPHY_SEQ_LPT_ADDR3_P0", MCA_DDRPHY_SEQ_LPT_ADDR3_P0 }, - {"MCA_DDRPHY_SEQ_LPT_ADDR4_P0", MCA_DDRPHY_SEQ_LPT_ADDR4_P0 }, - {"MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0", MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 }, - {"MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0", MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 }, - {"MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0", MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 }, - {"MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0", MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0 }, - {"MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0", MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0 }, - {"MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0", MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0 }, - {"MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0", MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0 }, - {"MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0", MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0 }, - {"MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0", MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0 }, - {"MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0", MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0 }, - {"MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0", MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0 }, - {"MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0", MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0 }, - {"MCA_DDRPHY_SEQ_RD_WR_DATA0_P0", MCA_DDRPHY_SEQ_RD_WR_DATA0_P0 }, - {"MCA_DDRPHY_SEQ_RD_WR_DATA1_P0", MCA_DDRPHY_SEQ_RD_WR_DATA1_P0 }, - {"MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0", MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0 }, - {"MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0", MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0 }, - {"MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0", MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0 }, - {"MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0", MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0 }, - {"MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0", MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0 }, - {"MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0", MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0 }, - {"MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0", MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0 }, - {"MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0", MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0 }, - {"MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0", MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0 }, - {"MCA_DDRPHY_WC_CONFIG0_P0", MCA_DDRPHY_WC_CONFIG0_P0 }, - {"MCA_DDRPHY_WC_CONFIG1_P0", MCA_DDRPHY_WC_CONFIG1_P0 }, - {"MCA_DDRPHY_WC_CONFIG2_P0", MCA_DDRPHY_WC_CONFIG2_P0 }, - {"MCA_DDRPHY_WC_CONFIG3_P0", MCA_DDRPHY_WC_CONFIG3_P0 }, - {"MCA_DDRPHY_WC_ERROR_MASK0_P0", MCA_DDRPHY_WC_ERROR_MASK0_P0 }, - {"MCA_DDRPHY_WC_ERROR_STATUS0_P0", MCA_DDRPHY_WC_ERROR_STATUS0_P0 }, - {"MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0", MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0 }, - }; - - for (const auto& r : l_registers) - { - fapi2::buffer<uint64_t> l_data; - FAPI_TRY( mss::getScom(i_target, r.second, l_data) ); - FAPI_DBG("dump %s: 0x%016lx 0x%04lx", r.first, r.second, l_data); - } - -fapi_try_exit: - return fapi2::current_err; -} } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C index cf96bbf10..86cd3bf0e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C @@ -75,9 +75,9 @@ extern "C" return fapi2::FAPI2_RC_SUCCESS; } - // Configure the CCS engine. Since this is a chunk of McBIST logic, we don't want + // Configure the CCS engine. Since this is a chunk of MCBIST logic, we don't want // to do it for every port. If we ever break this code out so f/w can call draminit - // per-port (separate threads) we'll need to proved them a way to set this up before + // per-port (separate threads) we'll need to provide them a way to set this up before // sapwning per-port threads. { fapi2::buffer<uint64_t> l_ccs_config; diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index 142e8e212..0cbb14324 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -84,36 +84,7 @@ extern "C" // Setup a series of register probes which we'll see during the polling loop // Leaving these probes in here as we need them from time to time, but they // take up a lot of sim time, so we like to remove them simply -#ifdef TRAINING_POLLING_PROBES - l_program.iv_probes = - { - // One block for each DP16 - {p, "wr_cntr_status0 (dp16 0)", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0}, - {p, "wr_cntr_status1 (dp16 0)", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0}, - {p, "wr_cntr_status2 (dp16 0)", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0}, - {p, "wr_lvl_status (dp16 0)", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0}, - - {p, "wr_cntr_status0 (dp16 1)", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1}, - {p, "wr_cntr_status1 (dp16 1)", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1}, - {p, "wr_cntr_status2 (dp16 1)", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1}, - {p, "wr_lvl_status (dp16 1)", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1}, - - {p, "wr_cntr_status0 (dp16 2)", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2}, - {p, "wr_cntr_status1 (dp16 2)", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2}, - {p, "wr_cntr_status2 (dp16 2)", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2}, - {p, "wr_lvl_status (dp16 2)", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2}, - - {p, "wr_cntr_status0 (dp16 3)", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3}, - {p, "wr_cntr_status1 (dp16 3)", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3}, - {p, "wr_cntr_status2 (dp16 3)", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3}, - {p, "wr_lvl_status (dp16 3)", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3}, - - {p, "wr_cntr_status0 (dp16 4)", MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4}, - {p, "wr_cntr_status1 (dp16 4)", MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4}, - {p, "wr_cntr_status2 (dp16 4)", MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4}, - {p, "wr_lvl_status (dp16 4)", MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4}, - }; -#endif + // Delays in the CCS instruction ARR1 for training are supposed to be 0xFFFF, // and we're supposed to poll for the done or timeout bit. But we don't want // to wait 0xFFFF cycles before we start polling - that's too long. So we put @@ -129,11 +100,6 @@ extern "C" // we configured on this port. std::vector<uint64_t> l_pairs; -#ifdef CAL_STATUS_DOESNT_REPORT_COMPLETE - // This isn't correct - shouldn't be setting - static const uint64_t CLEAR_CAL_COMPLETE = 0x000000000000F000; - FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_STATUS_P0, CLEAR_CAL_COMPLETE) ); -#endif FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_ERROR_P0, 0) ); FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, 0) ); diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml index 03fa442d7..b0095c9e4 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml @@ -76,7 +76,9 @@ </registerFfdc> <registerFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> + <scomRegister>MCA_DDRPHY_PC_INIT_CAL_ERROR_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_ERROR_STATUS0_P0</scomRegister> <scomRegister>MCA_DDRPHY_DP16_RD_STATUS0_P0_0</scomRegister> <scomRegister>MCA_DDRPHY_DP16_RD_STATUS0_P0_1</scomRegister> <scomRegister>MCA_DDRPHY_DP16_RD_STATUS0_P0_2</scomRegister> @@ -110,7 +112,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -133,7 +135,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -156,7 +158,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -179,7 +181,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -202,7 +204,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -225,7 +227,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -248,7 +250,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -271,7 +273,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -294,7 +296,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -317,7 +319,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -340,7 +342,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> @@ -363,7 +365,7 @@ <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_DRAMINIT_TRAINING_DP16_ERROR_STATUS</id> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> <callout> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml index 1ffe1702a..5b9193318 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml @@ -33,11 +33,127 @@ <hwpErrors> <registerFfdc> + <id>REG_FFDC_PHY_MR_SHADOW_REGS</id> + <scomRegister>MCA_DDRPHY_PC_MR0_PRI_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR0_PRI_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR0_PRI_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR0_PRI_RP3_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR0_SEC_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR0_SEC_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR0_SEC_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR0_SEC_RP3_P0</scomRegister> + + <scomRegister>MCA_DDRPHY_PC_MR1_PRI_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR1_PRI_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR1_PRI_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR1_PRI_RP3_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR1_SEC_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR1_SEC_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR1_SEC_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR1_SEC_RP3_P0</scomRegister> + + <scomRegister>MCA_DDRPHY_PC_MR2_PRI_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR2_PRI_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR2_PRI_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR2_PRI_RP3_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR2_SEC_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR2_SEC_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR2_SEC_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR2_SEC_RP3_P0</scomRegister> + + <scomRegister>MCA_DDRPHY_PC_MR3_PRI_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR3_PRI_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR3_PRI_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR3_PRI_RP3_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR3_SEC_RP0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR3_SEC_RP1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR3_SEC_RP2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_PC_MR3_SEC_RP3_P0</scomRegister> + </registerFfdc> + + <registerFfdc> <id>REG_FFDC_MSS_CCS_FAILURE</id> <scomRegister>MCBIST_CCS_MODEQ</scomRegister> <scomRegister>MCBIST_CCS_STATQ</scomRegister> <scomRegister>MCBIST_CCS_CNTLQ</scomRegister> <scomRegister>MCBIST_MCBMCATQ</scomRegister> + + <!-- Instructions --> + <scomRegister>MCBIST_CCS_INST_ARR0_00</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_01</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_02</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_03</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_04</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_05</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_06</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_07</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_08</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_09</scomRegister> + + <scomRegister>MCBIST_CCS_INST_ARR0_10</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_11</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_12</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_13</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_14</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_15</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_16</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_17</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_18</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_19</scomRegister> + + <scomRegister>MCBIST_CCS_INST_ARR0_20</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_21</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_22</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_23</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_24</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_25</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_26</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_27</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_28</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_29</scomRegister> + + <scomRegister>MCBIST_CCS_INST_ARR0_30</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR0_31</scomRegister> + + <!-- Control array --> + <scomRegister>MCBIST_CCS_INST_ARR1_00</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_01</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_02</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_03</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_04</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_05</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_06</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_07</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_08</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_09</scomRegister> + + <scomRegister>MCBIST_CCS_INST_ARR1_10</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_11</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_12</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_13</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_14</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_15</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_16</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_17</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_18</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_19</scomRegister> + + <scomRegister>MCBIST_CCS_INST_ARR1_20</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_21</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_22</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_23</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_24</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_25</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_26</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_27</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_28</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_29</scomRegister> + + <scomRegister>MCBIST_CCS_INST_ARR1_30</scomRegister> + <scomRegister>MCBIST_CCS_INST_ARR1_31</scomRegister> + + <!-- to get the CCS state machine hung state --> + <scomRegister>MCBIST_MCBERRPTQ</scomRegister> </registerFfdc> <hwpError> @@ -48,6 +164,10 @@ <id>REG_FFDC_MSS_CCS_FAILURE</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PHY_MR_SHADOW_REGS</id> + <target>TARGET_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>TARGET_IN_ERROR</target> <priority>HIGH</priority> @@ -65,6 +185,10 @@ <id>REG_FFDC_MSS_CCS_FAILURE</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PHY_MR_SHADOW_REGS</id> + <target>TARGET_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>TARGET_IN_ERROR</target> <priority>HIGH</priority> @@ -82,6 +206,10 @@ <id>REG_FFDC_MSS_CCS_FAILURE</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PHY_MR_SHADOW_REGS</id> + <target>TARGET_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>TARGET_IN_ERROR</target> <priority>HIGH</priority> @@ -98,6 +226,10 @@ <id>REG_FFDC_MSS_CCS_FAILURE</id> <target>TARGET_IN_ERROR</target> </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PHY_MR_SHADOW_REGS</id> + <target>TARGET_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>TARGET_IN_ERROR</target> <priority>HIGH</priority> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml index cb31c4284..f80a8ae75 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml @@ -58,7 +58,8 @@ <hwpError> <rc>RC_MSS_MEMDIAGS_UE_OR_SUE_IN_LAST_PATTERN</rc> <description>A UE or SUE was caused by the last MCBIST pattern</description> - <ffdc>STATUS</ffdc> + <ffdc>STATUS0</ffdc> + <ffdc>STATUS1</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> <target>TARGET</target> @@ -73,6 +74,7 @@ <rc>RC_MSS_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN</rc> <description>A miscompare error was caused by the last MCBIST pattern</description> <ffdc>PORT</ffdc> + <ffdc>SUBTEST</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> <target>TARGET</target> |