diff options
Diffstat (limited to 'src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml | 76 |
1 files changed, 71 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml index 52d47ded0..4dee999b7 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -30,11 +30,43 @@ Procedure: p9_sbe_check_master_stop15 Indicates the targeted core is either running (hasn't started to enter a STOP state) or is in transition. This return code would be used by the - caller (SBE control loop) to determine whether to continue polling for a - completed transition. - - Note: STOP 11 and STOP 15 are equivalent for POWER9. + caller (FSP/SBE control loop) to determine whether to continue polling + for a completed transition. </description> + + <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc> + + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_PU</id> + <target>PU</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EQ</id> + <target>EQ</target> + <targetType>TARGET_TYPE_EQ</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EX</id> + <target>EX</target> + <targetType>TARGET_TYPE_EX</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id> + <target>EC</target> + <targetType>TARGET_TYPE_CORE</targetType> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>LVL_SUPPORT</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>EC</target> + </deconfigure> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -44,6 +76,40 @@ Indicates the targeted core is no longer pending entering a STOP state but the achieved level is not appropriate. </description> + + <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc> + + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_PU</id> + <target>PU</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EQ</id> + <target>EQ</target> + <targetType>TARGET_TYPE_EQ</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EX</id> + <target>EX</target> + <targetType>TARGET_TYPE_EX</targetType> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id> + <target>EC</target> + <targetType>TARGET_TYPE_CORE</targetType> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>LVL_SUPPORT</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>EC</target> + </deconfigure> </hwpError> <!-- ******************************************************************** --> <hwpError> |
