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-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index ff1a0b3fd..b12add32b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2389,6 +2389,23 @@
</attribute>
<attribute>
+ <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DISABLE_HW_VREF_CAL</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ In below DD2 Nimbus, the HW VREF calibration needs to be checked against the chip subversion to see if it can be run.
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+
+ <attribute>
<id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
@@ -2426,6 +2443,23 @@
</attribute>
<attribute>
+ <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ In below DD2 Nimbus, the RD VREF cal VREF sense needs to be checked against the chip subversion to see if it should be run.
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+
+ <attribute>
<id>ATTR_CHIP_EC_FEATURE_RNG_ADAPTEST_SETTINGS</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
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