diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C | 4 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C index 4fa0017d3..7d320eee8 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C @@ -103,6 +103,10 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0 l_scom_buffer.insert<8, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE_ON ); constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF = 0x0; l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF ); + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_SYNC_ON = 0x1; + l_scom_buffer.insert<27, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_SYNC_ON ); + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_PAIR_SYNC_ON = 0x1; + l_scom_buffer.insert<28, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_PAIR_SYNC_ON ); FAPI_TRY(fapi2::putScom(TGT0, 0x5010811ull, l_scom_buffer)); } } diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C index af80d2fb8..e86021ea4 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C @@ -181,12 +181,22 @@ fapi2::ReturnCode progMCMODE0( l_scomData.setBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); } + else + { + l_scomData.clearBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); + l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); + } if (!l_same_side_functional) { l_scomData.setBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); } + else + { + l_scomData.clearBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + } FAPI_INF("Writing MCS_MCMODE0 reg 0x%.16llX: Mask 0x%.16llX , Data 0x%.16llX", MCS_MCMODE0, l_scomMask, l_scomData); |
