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-rw-r--r--src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H
index f32c74796..82d00e879 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H
@@ -22,9 +22,8 @@
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
-// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 1
+// *HWP Level: 2
// *HWP Consumed by: FSP:HB
#ifndef __P9_MSS_DRAMINIT_MC__
@@ -38,7 +37,7 @@ extern "C"
{
///
/// @brief Initialize the MC now that DRAM is up
-/// @param[in] i_target, the McBIST of the ports of the dram you're training
+/// @param[in] i_target, the McBIST of the ports
/// @return FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode p9_mss_draminit_mc( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target );
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