diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 4aa8db4cf..1958501e3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -251,11 +251,12 @@ enum cal_steps : uint64_t WRITE_CTR = 17, ///< Write Centering COARSE_WR = 18, ///< Initial Coarse Pattern Write COARSE_RD = 19, ///< Coarse Read Centering - TRAINING_ADV = 20, ///< Flag for draminit training advance in the attribute/ CUSTOM_READ_CTR in code + TRAINING_ADV_RD = 20, ///< Flag for draminit training advance in the attribute/ CUSTOM_READ_CTR in code + TRAINING_ADV_WR = 21, ///< Flag for draminit training advance in the attribute/ CUSTOM_WRITE_CTR in code // Not *exactly* a cal step but go w/it - RUN_ALL_CAL_STEPS = 0xFFFFF800, - RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7800, + RUN_ALL_CAL_STEPS = 0xFFFFFC00, + RUN_CAL_SKIP_WR_RD_2D_VREF = 0xFFFD7C00, INITIAL_PAT_WR_TO_RD_CTR_LEN = inclusive_range(INITIAL_PAT_WR, READ_CTR), WR_VREF_TO_COARSE_RD_LEN = inclusive_range(WRITE_CTR_2D_VREF, COARSE_RD), |
