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-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
index 6e6771f73..329bfa4d2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
@@ -167,6 +167,8 @@ class rosettaTraits<fapi2::TARGET_TYPE_MCA, DQ>
public:
// Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
static const rosetta_map::PhyMap C4_TO_PHY;
+ // Map from MC index to PHY pin. Not a PhyMap because it's the same for every port
+ static const std::vector<std::pair<uint64_t, uint64_t>> MC_TO_PHY;
};
///
@@ -179,6 +181,8 @@ class rosettaTraits<fapi2::TARGET_TYPE_MCA, DQS>
public:
// Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
static const rosetta_map::PhyMap C4_TO_PHY;
+ // Map from MC index to PHY pin. Not a PhyMap because it's the same for every port
+ static const std::vector<std::pair<uint64_t, uint64_t>> MC_TO_PHY;
};
///
@@ -191,6 +195,8 @@ class rosettaTraits<fapi2::TARGET_TYPE_MCA, ADDRESS>
public:
// Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
static const rosetta_map::PhyMap C4_TO_PHY;
+ // Constexpr defines how many pins there are on an ADR instance
+ static constexpr uint64_t PINS_PER_ADR = 12;
};
///
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