diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy')
3 files changed, 97 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 8c2a338e8..9b468e1ce 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -650,6 +650,9 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target // Resets all WR VREF related registers FAPI_TRY( mss::dp16::reset_wr_vref_registers(p)); + // Reset the windage registers + FAPI_TRY( mss::dp16::reset_read_delay_offset_registers(p) ); + // // Workarounds // diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 02c90dd7f..ddf1e0a03 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -339,6 +339,7 @@ const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>:: { MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 }, { MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 }, }; + // Definition of the VREF value registers for RP3 element is DP16 number, first is value 0 second is value 1 const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP3_REG = { @@ -349,6 +350,51 @@ const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>:: { MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 }, }; +// Definition of the windage value registers per MCA. These are per rank pair, per DP16 and there are 2. +const std::vector<uint64_t> dp16Traits<TARGET_TYPE_MCA>::READ_DELAY_OFFSET_REG = +{ + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3, + MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4, +}; + /// /// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage. /// @tparam T fapi2 Target Type - derived @@ -1645,5 +1691,35 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Resets all read delay offset registers +/// @param[in] i_target the fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template<> +fapi2::ReturnCode reset_read_delay_offset_registers( const fapi2::Target<TARGET_TYPE_MCA>& i_target ) +{ + typedef dp16Traits<TARGET_TYPE_MCA> TT; + + // We grab the information from the VPD and blast it in to all the registers. Note the + // VPD is picoseconds but the register wants clocks - so we convert. Likewise, the VPD + // is per port so we can easily cram the data in to the port using the blastah. + fapi2::buffer<uint64_t> l_data; + int64_t l_clocks = 0; + int16_t l_windage = 0; + + FAPI_TRY( mss::vpd_mt_windage_rd_ctr(i_target, l_windage) ); + l_clocks = mss::ps_to_cycles(i_target, l_windage); + + l_data + .insertFromRight<TT::READ_OFFSET_LOWER, TT::READ_OFFSET_LOWER_LEN>(l_clocks) + .insertFromRight<TT::READ_OFFSET_UPPER, TT::READ_OFFSET_UPPER_LEN>(l_clocks); + + FAPI_TRY( mss::scom_blastah(i_target, TT::READ_DELAY_OFFSET_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + } // close namespace dp16 } // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index 7485232bc..bbd2e1f73 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -156,6 +156,7 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA> static const std::vector< uint64_t > PR_STATIC_OFFSET_REG; static const std::vector< uint64_t > IO_TX_FET_SLICE_REG; static const std::vector< uint64_t > IO_TX_PFET_TERM_REG; + static const std::vector< uint64_t > READ_DELAY_OFFSET_REG; //WR VREF registers static const std::vector< uint64_t > WR_VREF_CONFIG0_REG; @@ -291,6 +292,12 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA> WR_VREF_VALUE_RANGE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM1 , WR_VREF_VALUE_VALUE_DRAM_ODD = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1 , WR_VREF_VALUE_VALUE_DRAM_ODD_LEN = MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1_LEN , + + // Read Delay fields. + READ_OFFSET_LOWER = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01, + READ_OFFSET_LOWER_LEN = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN, + READ_OFFSET_UPPER = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1, + READ_OFFSET_UPPER_LEN = MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN, }; }; @@ -1666,6 +1673,17 @@ fapi2::ReturnCode reset_wr_vref_value_rp3( const fapi2::Target<T>& i_target ); template< fapi2::TargetType T, typename TT = dp16Traits<T> > fapi2::ReturnCode reset_wr_vref_registers( const fapi2::Target<T>& i_target ); +/// +/// @brief Resets all read delay offset registers +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to dp16Traits<T> +/// @param[in] i_target the fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +// TODO RTC:162136 implement read, write, set and get for the read delay offset registers +template< fapi2::TargetType T, typename TT = dp16Traits<T> > +fapi2::ReturnCode reset_read_delay_offset_registers( const fapi2::Target<T>& i_target ); + } // close namespace dp16 } // close namespace mss |