diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C | 518 |
1 files changed, 517 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 5522ec472..975c0ae6b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -1415,6 +1415,442 @@ const std::vector< std::vector<uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_DQ_DE }, }; +const std::vector<std::vector<uint64_t>> dp16Traits<TARGET_TYPE_MCA>::WR_DELAY_REG +{ + // RP0 + { + // DP0 + MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0, + // DP1 + MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1, + // DP2 + MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2, + // DP3 + MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3, + // DP4 + MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4, + }, + // RP1 + { + // DP0 + MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0, + // DP1 + MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1, + // DP2 + MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2, + // DP3 + MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3, + // DP4 + MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4, + }, + // RP2 + { + // DP0 + MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0, + // DP1 + MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1, + // DP2 + MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2, + // DP3 + MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3, + // DP4 + MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4, + }, + // RP3 + { + // DP0 + MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0, + MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0, + // DP1 + MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1, + MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1, + // DP2 + MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2, + MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2, + // DP3 + MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3, + MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3, + // DP4 + MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4, + MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4, + }, +}; + /// /// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage. /// @tparam T fapi2 Target Type - derived @@ -1759,7 +2195,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCES iff ok /// template<> -fapi2::ReturnCode rd_ctr_settings<TARGET_TYPE_MCA>::restore() +fapi2::ReturnCode rd_ctr_settings<TARGET_TYPE_MCA>::restore() const { typedef mss::dp16Traits<TARGET_TYPE_MCA> TT; @@ -1854,6 +2290,86 @@ fapi_try_exit: } /// +/// @brief Save settings for a given rank pair +/// @return FAPI2_RC_SUCCES iff ok +/// +template<> +fapi2::ReturnCode wr_ctr_settings<TARGET_TYPE_MCA>::save() +{ + typedef mss::dp16Traits<TARGET_TYPE_MCA> TT; + + // Read each register and save in private variables + FAPI_TRY( mss::scom_suckah(iv_target, TT::WR_DELAY_REG[iv_rp], iv_write_delay) ); + FAPI_TRY( mss::scom_suckah(iv_target, TT::BIT_DISABLE_REG[iv_rp], iv_dq_disable) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Restore settings for a given rank pair +/// @return FAPI2_RC_SUCCES iff ok +/// +template<> +fapi2::ReturnCode wr_ctr_settings<TARGET_TYPE_MCA>::restore() const +{ + typedef mss::dp16Traits<TARGET_TYPE_MCA> TT; + + std::vector<fapi2::buffer<uint64_t>> l_post_training_settings; + std::vector<std::pair<fapi2::buffer<uint64_t>, fapi2::buffer<uint64_t> > > l_post_training_disables; + + // Log values before restoring them + FAPI_TRY( mss::scom_suckah(iv_target, TT::WR_DELAY_REG[iv_rp], l_post_training_settings) ); + + if( l_post_training_settings.size() != iv_write_delay.size() ) + { + // Asserting out instead of collecting FFDC since this is a + // programming bug that shouldn't occur. + FAPI_ERR("Number of WRITE_DELAY registers != number of stored registers: %d != %d", + l_post_training_settings.size(), iv_write_delay.size()); + fapi2::Assert(false); + } + + // TK Should these messages be written in FFDC so we can see them in FW? + for (uint64_t l_idx = 0; l_idx < l_post_training_settings.size(); ++l_idx) + { + FAPI_INF("%s restoring value of WRITE_DELAY scom 0x%016llx from 0x%016llx to 0x%016llx", + mss::c_str(iv_target), TT::WR_DELAY_REG[iv_rp][l_idx], l_post_training_settings[l_idx], iv_write_delay[l_idx]); + } + + FAPI_TRY( mss::scom_suckah(iv_target, TT::BIT_DISABLE_REG[iv_rp], l_post_training_disables) ); + + if( l_post_training_disables.size() != iv_dq_disable.size() ) + { + // Asserting out instead of collecting FFDC since this is a + // programming bug that shouldn't occur. + FAPI_ERR("Number of BIT_DISABLE registers != number of stored registers: %d != %d", + l_post_training_disables.size(), iv_dq_disable.size()); + fapi2::Assert(false); + } + + for (uint64_t l_idx = 0; l_idx < l_post_training_disables.size(); ++l_idx) + { + FAPI_INF("%s restoring value of DATA_DISABLE scom 0x%016llx from 0x%016llx to 0x%016llx", + mss::c_str(iv_target), TT::BIT_DISABLE_REG[iv_rp][l_idx].first, l_post_training_disables[l_idx].first, + iv_dq_disable[l_idx].first); + FAPI_INF("%s restoring value of DATA_DISABLE scom 0x%016llx from 0x%016llx to 0x%016llx", + mss::c_str(iv_target), TT::BIT_DISABLE_REG[iv_rp][l_idx].second, l_post_training_disables[l_idx].second, + iv_dq_disable[l_idx].second); + } + + // Write each register back from private variables + FAPI_TRY( mss::scom_blastah(iv_target, TT::WR_DELAY_REG[iv_rp], iv_write_delay) ); + FAPI_TRY( mss::scom_blastah(iv_target, TT::BIT_DISABLE_REG[iv_rp], iv_dq_disable) ); + + // Run the record_bad_bits function to restore the BAD_DQ_BITMAP attribute using the pre-training disable bits + FAPI_TRY( mss::dp16::record_bad_bits(iv_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Reset the data bit enable registers /// @param[in] i_target a port target /// @return FAPI2_RC_SUCCES iff ok |
