diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H | 144 |
1 files changed, 120 insertions, 24 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index fa1683bd2..783fd05aa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -9273,12 +9273,13 @@ fapi_try_exit: /// MRD - Fine (LRDIMM) [5] WR_LEVEL [6] INITIAL_PAT_WR [7] WR_VREF_LATCH [8] DWL /// (LRDIMM) [9] MWD - Coarse (LRDIMM) [10] MWD - Fine (LRDIMM) [11] HWL (LRDIMM) /// [12] DQS_ALIGN [13] RDCLK_ALIGN [14] READ_CTR_2D_VREF [15] READ_CTR [16] -/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] TRAINING_ADV -/// Only set for DD2.* machines [21]:[31] Reserved for future use COARSE_WR and -/// COARSE_RD will be consumed together to form COARSE_LVL. WRITE_CTR will be run, -/// even if only WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon -/// WRITE_CTR 1D to function. Note: LRDIMM steps will only be enabled for LRDIMMs -/// and won't run on +/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] +/// TRAINING_ADV_RD Only set for DD2.* machines [21] TRAINING_ADV_WR Only set for +/// DD2.* machines [22]:[31] Reserved for future use COARSE_WR and COARSE_RD will be +/// consumed together to form COARSE_LVL. WRITE_CTR will be run, even if only +/// WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon WRITE_CTR 1D +/// to function. Note: LRDIMM steps will only be enabled for LRDIMMs and won't run +/// on /// RDIMMs. /// inline fapi2::ReturnCode cal_step_enable(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint32_t& o_value) @@ -9306,12 +9307,13 @@ fapi_try_exit: /// MRD - Fine (LRDIMM) [5] WR_LEVEL [6] INITIAL_PAT_WR [7] WR_VREF_LATCH [8] DWL /// (LRDIMM) [9] MWD - Coarse (LRDIMM) [10] MWD - Fine (LRDIMM) [11] HWL (LRDIMM) /// [12] DQS_ALIGN [13] RDCLK_ALIGN [14] READ_CTR_2D_VREF [15] READ_CTR [16] -/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] TRAINING_ADV -/// Only set for DD2.* machines [21]:[31] Reserved for future use COARSE_WR and -/// COARSE_RD will be consumed together to form COARSE_LVL. WRITE_CTR will be run, -/// even if only WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon -/// WRITE_CTR 1D to function. Note: LRDIMM steps will only be enabled for LRDIMMs -/// and won't run on +/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] +/// TRAINING_ADV_RD Only set for DD2.* machines [21] TRAINING_ADV_WR Only set for +/// DD2.* machines [22]:[31] Reserved for future use COARSE_WR and COARSE_RD will be +/// consumed together to form COARSE_LVL. WRITE_CTR will be run, even if only +/// WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon WRITE_CTR 1D +/// to function. Note: LRDIMM steps will only be enabled for LRDIMMs and won't run +/// on /// RDIMMs. /// inline fapi2::ReturnCode cal_step_enable(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint32_t& o_value) @@ -9340,12 +9342,13 @@ fapi_try_exit: /// MRD - Fine (LRDIMM) [5] WR_LEVEL [6] INITIAL_PAT_WR [7] WR_VREF_LATCH [8] DWL /// (LRDIMM) [9] MWD - Coarse (LRDIMM) [10] MWD - Fine (LRDIMM) [11] HWL (LRDIMM) /// [12] DQS_ALIGN [13] RDCLK_ALIGN [14] READ_CTR_2D_VREF [15] READ_CTR [16] -/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] TRAINING_ADV -/// Only set for DD2.* machines [21]:[31] Reserved for future use COARSE_WR and -/// COARSE_RD will be consumed together to form COARSE_LVL. WRITE_CTR will be run, -/// even if only WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon -/// WRITE_CTR 1D to function. Note: LRDIMM steps will only be enabled for LRDIMMs -/// and won't run on +/// WRITE_CTR_2D_VREF [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD [20] +/// TRAINING_ADV_RD Only set for DD2.* machines [21] TRAINING_ADV_WR Only set for +/// DD2.* machines [22]:[31] Reserved for future use COARSE_WR and COARSE_RD will be +/// consumed together to form COARSE_LVL. WRITE_CTR will be run, even if only +/// WRITE_CTR_2D_VREF is enabled, as the WR 2D VREF HW cal depends upon WRITE_CTR 1D +/// to function. Note: LRDIMM steps will only be enabled for LRDIMMs and won't run +/// on /// RDIMMs. /// inline fapi2::ReturnCode cal_step_enable(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint32_t* o_array) @@ -9375,7 +9378,7 @@ fapi_try_exit: /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Special training pattern used in draminit_training_advance. Used for custom -/// pattern write There can be two patterns used here. This attribute is before +/// pattern read There can be two patterns used here. This attribute is before /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute /// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for @@ -9405,7 +9408,7 @@ fapi_try_exit: /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Special training pattern used in draminit_training_advance. Used for custom -/// pattern write There can be two patterns used here. This attribute is before +/// pattern read There can be two patterns used here. This attribute is before /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute /// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for @@ -9436,7 +9439,7 @@ fapi_try_exit: /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Special training pattern used in draminit_training_advance. Used for custom -/// pattern write There can be two patterns used here. This attribute is before +/// pattern read There can be two patterns used here. This attribute is before /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute /// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for @@ -9470,7 +9473,7 @@ fapi_try_exit: /// @param[out] ref to the value uint32_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Special training backup pattern Used for custom_pattern_write in +/// @note Special training backup pattern Used for custom_pattern_read in /// draminit_training_advance. If the main patterns fail, the code will try running /// this pattern Used for read centering There can be two patterns used here. This /// attribute is before swizzling for endianness of the registers. CODE WILL SWIZZLE @@ -9501,7 +9504,7 @@ fapi_try_exit: /// @param[out] ref to the value uint32_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Special training backup pattern Used for custom_pattern_write in +/// @note Special training backup pattern Used for custom_pattern_read in /// draminit_training_advance. If the main patterns fail, the code will try running /// this pattern Used for read centering There can be two patterns used here. This /// attribute is before swizzling for endianness of the registers. CODE WILL SWIZZLE @@ -9533,7 +9536,7 @@ fapi_try_exit: /// @param[out] uint32_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Special training backup pattern Used for custom_pattern_write in +/// @note Special training backup pattern Used for custom_pattern_read in /// draminit_training_advance. If the main patterns fail, the code will try running /// this pattern Used for read centering There can be two patterns used here. This /// attribute is before swizzling for endianness of the registers. CODE WILL SWIZZLE @@ -9564,6 +9567,99 @@ fapi_try_exit: } /// +/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Special training pattern used in draminit_training_advance. Used for custom +/// pattern write Due to hardware limitations, only one 8-bit pattern can be used +/// This attribute is before swizzling for endianness of the registers. CODE WILL +/// SWIZZLE FOR THE SYSTEM If this attribute is set to 0, using the default values +/// of: 0x9A Set to default in +/// eff_config +/// +inline fapi2::ReturnCode custom_training_adv_wr_pattern(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint8_t& o_value) +{ + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Special training pattern used in draminit_training_advance. Used for custom +/// pattern write Due to hardware limitations, only one 8-bit pattern can be used +/// This attribute is before swizzling for endianness of the registers. CODE WILL +/// SWIZZLE FOR THE SYSTEM If this attribute is set to 0, using the default values +/// of: 0x9A Set to default in +/// eff_config +/// +inline fapi2::ReturnCode custom_training_adv_wr_pattern(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) +{ + uint8_t l_value[2]; + auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); + o_value = l_value[mss::index(l_mca)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Special training pattern used in draminit_training_advance. Used for custom +/// pattern write Due to hardware limitations, only one 8-bit pattern can be used +/// This attribute is before swizzling for endianness of the registers. CODE WILL +/// SWIZZLE FOR THE SYSTEM If this attribute is set to 0, using the default values +/// of: 0x9A Set to default in +/// eff_config +/// +inline fapi2::ReturnCode custom_training_adv_wr_pattern(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MSS_VREF_CAL_ENABLE getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint16_t |
