diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | 32 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C | 31 |
2 files changed, 30 insertions, 33 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index b4ce1a6b7..540ae5b8c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -37,6 +37,7 @@ #include <mss.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/eff_config/timing.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -60,31 +61,26 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { FAPI_INF("ddr4::mrs_load %s", mss::c_str(i_target)); - // Per DDR4 Full spec update (79-4A) - timing requirements - constexpr uint64_t tMRD = 8; - constexpr uint64_t tZQinit = 1024; - uint64_t l_freq = 0; - uint64_t tDLLK = 0; fapi2::buffer<uint16_t> l_cal_steps; + uint64_t tDLLK = 0; static std::vector< mrs_data<TARGET_TYPE_MCBIST> > l_mrs_data = { // JEDEC ordering of MRS per DDR4 power on sequence - { 3, mrs03, mrs03_decode, tMRD }, - { 6, mrs06, mrs06_decode, tMRD }, - { 5, mrs05, mrs05_decode, tMRD }, - { 4, mrs04, mrs04_decode, tMRD }, - { 2, mrs02, mrs02_decode, tMRD }, - { 1, mrs01, mrs01_decode, tMRD }, - { 0, mrs00, mrs00_decode, tMRD }, + { 3, mrs03, mrs03_decode, mss::tmrd() }, + { 6, mrs06, mrs06_decode, mss::tmrd() }, + { 5, mrs05, mrs05_decode, mss::tmrd() }, + { 4, mrs04, mrs04_decode, mss::tmrd() }, + { 2, mrs02, mrs02_decode, mss::tmrd() }, + { 1, mrs01, mrs01_decode, mss::tmrd() }, + + // We need to wait either tmod or tmrd before zqcl. + { 0, mrs00, mrs00_decode, std::max(mss::tmrd(), mss::tmod(i_target)) }, }; std::vector< uint64_t > l_ranks; FAPI_TRY( mss::ranks(i_target, l_ranks) ); - - // Calculate tDLLK from our frequency. Magic numbers (in clocks) from the DDR4 spec - FAPI_TRY( mss::freq(mss::find_target<TARGET_TYPE_MCBIST>(i_target), l_freq) ); - tDLLK = (l_freq < fapi2::ENUM_ATTR_MSS_FREQ_MT2133) ? 597 : 768; + FAPI_TRY( mss::tdllk(i_target, tDLLK) ); // Load MRS for (const auto& d : l_mrs_data) @@ -141,9 +137,9 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, l_inst_b_side = mss::address_invert(l_inst_a_side); l_inst_a_side.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, - MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + tZQinit); + MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + mss::tzqinit()); l_inst_b_side.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, - MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + tZQinit); + MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + mss::tzqinit()); // There's nothing to decode here. FAPI_INF("ZQCL 0x%016llx:0x%016llx %s:rank %d a-side", diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C index ef7f77392..a1f57e489 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C @@ -59,28 +59,29 @@ fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target { FAPI_INF("rcd_load_ddr4 %s", mss::c_str(i_target)); - // Per DDR4RCD02 table 104 - timing requirements - static const uint64_t tMRD = 8; - static const uint64_t tMRD_L = 16; - - // Per DDR4RCD02, tSTAB is 5us. We want this in cycles for the CCS. - const uint64_t tSTAB = mss::us_to_cycles(i_target, 5); + // Per DDR4RCD02, tSTAB is us. We want this in cycles for the CCS. + const uint64_t tSTAB = mss::us_to_cycles(i_target, mss::tstab()); static std::vector< rcd_data > l_rcd_4bit_data = { - { 0, eff_dimm_ddr4_rc00, tMRD }, { 1, eff_dimm_ddr4_rc01, tMRD }, { 2, eff_dimm_ddr4_rc02, tSTAB }, - { 3, eff_dimm_ddr4_rc03, tMRD_L}, { 4, eff_dimm_ddr4_rc04, tMRD_L}, { 5, eff_dimm_ddr4_rc05, tMRD_L}, - { 6, eff_dimm_ddr4_rc06_07, tMRD }, { 8, eff_dimm_ddr4_rc08, tMRD }, { 9, eff_dimm_ddr4_rc09, tMRD }, - { 10, eff_dimm_ddr4_rc10, tSTAB }, { 11, eff_dimm_ddr4_rc11, tMRD }, { 12, eff_dimm_ddr4_rc12, tMRD }, - { 13, eff_dimm_ddr4_rc13, tMRD }, { 14, eff_dimm_ddr4_rc14, tMRD }, { 15, eff_dimm_ddr4_rc15, tMRD }, + { 0, eff_dimm_ddr4_rc00, mss::tmrd() }, { 1, eff_dimm_ddr4_rc01, mss::tmrd() }, + { 2, eff_dimm_ddr4_rc02, tSTAB }, { 3, eff_dimm_ddr4_rc03, mss::tmrd_l() }, + { 4, eff_dimm_ddr4_rc04, mss::tmrd_l() }, { 5, eff_dimm_ddr4_rc05, mss::tmrd_l() }, + { 6, eff_dimm_ddr4_rc06_07, mss::tmrd() }, { 8, eff_dimm_ddr4_rc08, mss::tmrd() }, + { 9, eff_dimm_ddr4_rc09, mss::tmrd() }, { 10, eff_dimm_ddr4_rc10, tSTAB }, + { 11, eff_dimm_ddr4_rc11, mss::tmrd() }, { 12, eff_dimm_ddr4_rc12, mss::tmrd() }, + { 13, eff_dimm_ddr4_rc13, mss::tmrd() }, { 14, eff_dimm_ddr4_rc14, mss::tmrd() }, + { 15, eff_dimm_ddr4_rc15, mss::tmrd() }, }; static std::vector< rcd_data > l_rcd_8bit_data = { - { 1, eff_dimm_ddr4_rc_1x, tMRD }, { 2, eff_dimm_ddr4_rc_2x, tMRD }, { 3, eff_dimm_ddr4_rc_3x, tSTAB }, - { 4, eff_dimm_ddr4_rc_4x, tMRD }, { 5, eff_dimm_ddr4_rc_5x, tMRD }, { 6, eff_dimm_ddr4_rc_6x, tMRD }, - { 7, eff_dimm_ddr4_rc_7x, tMRD }, { 8, eff_dimm_ddr4_rc_8x, tMRD }, { 9, eff_dimm_ddr4_rc_9x, tMRD }, - { 10, eff_dimm_ddr4_rc_ax, tMRD }, { 11, eff_dimm_ddr4_rc_bx, tMRD_L} + { 1, eff_dimm_ddr4_rc_1x, mss::tmrd() }, { 2, eff_dimm_ddr4_rc_2x, mss::tmrd() }, + { 3, eff_dimm_ddr4_rc_3x, tSTAB }, { 4, eff_dimm_ddr4_rc_4x, mss::tmrd() }, + { 5, eff_dimm_ddr4_rc_5x, mss::tmrd() }, { 6, eff_dimm_ddr4_rc_6x, mss::tmrd() }, + { 7, eff_dimm_ddr4_rc_7x, mss::tmrd() }, { 8, eff_dimm_ddr4_rc_8x, mss::tmrd() }, + { 9, eff_dimm_ddr4_rc_9x, mss::tmrd() }, { 10, eff_dimm_ddr4_rc_ax, mss::tmrd() }, + { 11, eff_dimm_ddr4_rc_bx, mss::tmrd_l() } }; fapi2::buffer<uint8_t> l_value; |
