diff options
17 files changed, 424 insertions, 379 deletions
diff --git a/src/import/chips/centaur/utils/imageProcs/cen_ringId.C b/src/import/chips/centaur/utils/imageProcs/cen_ringId.C index de68361c0..5df973921 100644 --- a/src/import/chips/centaur/utils/imageProcs/cen_ringId.C +++ b/src/import/chips/centaur/utils/imageProcs/cen_ringId.C @@ -23,6 +23,9 @@ /* */ /* IBM_PROLOG_END_TAG */ +#include <string.h> +#include <common_ringId.H> + namespace CEN_RID { @@ -140,4 +143,75 @@ const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID }; }; // namespace CEN -}; // namespace CENTAUR +}; // namespace CEN_RID + + +using namespace CEN_RID; + +ChipletType_t CEN_RID::ringid_get_chiplet(RingId_t i_ringId) +{ + return RING_PROPERTIES[i_ringId].iv_type; +} + +void CEN_RID::ringid_get_chiplet_properties( + ChipletType_t i_chiplet, + ChipletData_t** o_cpltData, + GenRingIdList** o_ringComm, + GenRingIdList** o_ringInst, + RingVariantOrder** o_varOrder, + uint8_t* o_varNumb) +{ + switch (i_chiplet) + { + case CEN_TYPE : + *o_cpltData = (ChipletData_t*) &CEN::g_chipletData; + *o_ringComm = (GenRingIdList*) CEN::RING_ID_LIST_COMMON; + *o_ringInst = NULL; + *o_varOrder = (RingVariantOrder*) CEN::RING_VARIANT_ORDER; + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; + break; + + default : + *o_cpltData = NULL; + *o_ringComm = NULL; + *o_ringInst = NULL; + *o_varOrder = NULL; + *o_varNumb = 0; + break; + } +} + +GenRingIdList* CEN_RID::ringid_get_ring_properties(RingId_t i_ringId) +{ + ChipletData_t* l_cpltData; + GenRingIdList* l_ringList[2]; // 0: common, 1: instance + RingVariantOrder* l_varOrder; + uint8_t l_varNumb; + int i, j, n; + + CEN_RID::ringid_get_chiplet_properties( + CEN_RID::ringid_get_chiplet(i_ringId), + &l_cpltData, &l_ringList[0], &l_ringList[1], &l_varOrder, &l_varNumb); + + if (!l_ringList[0]) + { + return NULL; + } + + for (j = 0; j < 2; j++) // 0: common, 1: instance + { + n = (j ? l_cpltData->iv_num_instance_rings + : l_cpltData->iv_num_common_rings); + + for (i = 0; i < n; i++) + { + if (!strcmp(l_ringList[j][i].ringName, + RING_PROPERTIES[i_ringId].iv_name)) + { + return &(l_ringList[j][i]); + } + } + } + + return NULL; +} diff --git a/src/import/chips/centaur/utils/imageProcs/cen_ringId.H b/src/import/chips/centaur/utils/imageProcs/cen_ringId.H index d4f1b9ce6..134c3268a 100644 --- a/src/import/chips/centaur/utils/imageProcs/cen_ringId.H +++ b/src/import/chips/centaur/utils/imageProcs/cen_ringId.H @@ -42,12 +42,6 @@ namespace CEN extern const GenRingIdList RING_ID_LIST_COMMON[]; extern const RingVariantOrder RING_VARIANT_ORDER[]; -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -156,19 +150,19 @@ enum RingOffset // ** none ** }; -static const CHIPLET_DATA g_cenData = +static const ChipletData_t g_chipletData = { 0x01, // Centaur chiplet ID NUM_RING_IDS, // Num of common rings for Centaur chiplet 0, // Num of instance rings for Centaur chiplet - 0 + 0, + 2, // Num of ring variants: BASE, RL }; - }; // namespace CEN #ifndef __PPE__ -static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = +static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { { CEN::tcm_perv_cmsk, "tcm_perv_cmsk", CEN_TYPE }, { CEN::tcm_perv_lbst, "tcm_perv_lbst", CEN_TYPE }, @@ -275,7 +269,7 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = #else -static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = +static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { { CEN::tcm_perv_cmsk, CEN_TYPE }, { CEN::tcm_perv_lbst, CEN_TYPE }, @@ -382,4 +376,28 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = #endif // __PPE__ + + +// returns our own chiplet enum value for this ringId +ChipletType_t +ringid_get_chiplet( + RingId_t i_ringId); + +// returns data structures defined for chiplet type +// as determined by ringId +void +ringid_get_chiplet_properties( + ChipletType_t i_chiplet, + ChipletData_t** o_cpltData, + GenRingIdList** o_ringComm, + GenRingIdList** o_ringInst, + RingVariantOrder** o_varOrder, + uint8_t* o_varNumb); + +// returns properties of a ring as determined by ringId +GenRingIdList* +ringid_get_ring_properties( + RingId_t i_ringId); + + #endif // _CEN_RINGID_H_ diff --git a/src/import/chips/centaur/utils/imageProcs/cen_ringId.mk b/src/import/chips/centaur/utils/imageProcs/cen_ringId.mk index 5828fa2b2..92737c83b 100644 --- a/src/import/chips/centaur/utils/imageProcs/cen_ringId.mk +++ b/src/import/chips/centaur/utils/imageProcs/cen_ringId.mk @@ -22,7 +22,7 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG -PROCEDURE = cen_ringId +PROCEDURE=cen_ringId $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/common/utils/imageProcs) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.H b/src/import/chips/common/utils/imageProcs/common_ringId.H index 1efcac4a0..de4aa7137 100644 --- a/src/import/chips/common/utils/imageProcs/common_ringId.H +++ b/src/import/chips/common/utils/imageProcs/common_ringId.H @@ -126,7 +126,7 @@ enum RingType ALLRING = 2 }; -struct CHIPLET_DATA +typedef struct { // This is the chiplet-ID of the first instance of the Chiplet uint8_t iv_base_chiplet_number; @@ -140,7 +140,10 @@ struct CHIPLET_DATA // The no.of instance rings for the Chiplet (w/different ringId values // AND different scanAddress values) uint8_t iv_num_instance_rings_scan_addrs; -}; + + // The no.of ring variants + uint8_t iv_num_ring_variants; +} ChipletData_t; // This is used to Set (Mark) the left-most bit #define INSTANCE_RING_MARK (uint8_t)0x80 @@ -154,14 +157,14 @@ struct CHIPLET_DATA // This structure is needed for mapping a RingID to it's corresponding name. // The names will be used by the build scripts when generating the TOR. #ifndef __PPE__ -struct ringProperties_t +struct RingProperties_t { uint8_t iv_torOffSet; char iv_name[50]; ChipletType_t iv_type; }; #else -struct ringProperties_t +struct RingProperties_t { uint8_t iv_torOffSet; ChipletType_t iv_type; diff --git a/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C b/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C index dc01832e7..fccc0d4e5 100644 --- a/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C +++ b/src/import/chips/p9/procedures/hwp/accessors/p9_mvpd_ring_funcs.C @@ -534,7 +534,7 @@ extern "C" be64toh(l_pScanDataOld->iv_scanSelect) & l_evenOddMask ) ) { // look up ring in p9_ringId and retrieve scanAddr - GenRingIdList* l_ringProp = p9_ringid_get_ring_properties(i_ringId); + GenRingIdList* l_ringProp = ringid_get_ring_properties(i_ringId); FAPI_ASSERT(l_ringProp, fapi2::MVPD_RINGID_DATA_NOT_FOUND(). diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.mk b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.mk index fd41524c1..103376c98 100644 --- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.mk +++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.mk @@ -30,6 +30,7 @@ lib$(PROCEDURE)_DEPLIBS+=p9_get_mvpd_ring lib$(PROCEDURE)_DEPLIBS+=p9_mvpd_ring_funcs lib$(PROCEDURE)_DEPLIBS+=p9_tor lib$(PROCEDURE)_DEPLIBS+=p9_ringId +lib$(PROCEDURE)_DEPLIBS+=cen_ringId lib$(PROCEDURE)_DEPLIBS+=p9_dd_container $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/xip) $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/utils/imageProcs) diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 7a07e7080..c1a7eee54 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -64,8 +64,8 @@ namespace p9_hcodeImageBuild * @brief returns maximum quad common rings that enter HOMER. */ -#define MAX_HOMER_QUAD_CMN_RINGS (uint32_t)(EQ::g_eqData.iv_num_common_rings - 4) -#define MAX_HOMER_CORE_CMN_RINGS (uint32_t)(EC::g_ecData.iv_num_common_rings - 2) +#define MAX_HOMER_QUAD_CMN_RINGS (uint32_t)(EQ::g_chipletData.iv_num_common_rings - 4) +#define MAX_HOMER_CORE_CMN_RINGS (uint32_t)(EC::g_chipletData.iv_num_common_rings - 2) /** * @brief models QPMR header in HOMER diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 144ead47c..717cb5f22 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -3237,7 +3237,7 @@ fapi2::ReturnCode layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, uint32_t tempBufSize = 0; uint32_t tempLength = 0; - for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_instance_rings_scan_addrs; + for( uint32_t ringIndex = 0; ringIndex < EQ::g_chipletData.iv_num_instance_rings_scan_addrs; ringIndex++ ) { tempBufSize = i_ringData.iv_sizeWorkBuf1; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk index 8af339f69..277071bfd 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk @@ -39,6 +39,7 @@ lib$(PROCEDURE)_DEPLIBS += p9_xip_image lib$(PROCEDURE)_DEPLIBS += p9_tor lib$(PROCEDURE)_DEPLIBS += p9_ring_identification lib$(PROCEDURE)_DEPLIBS += p9_ringId +lib$(PROCEDURE)_DEPLIBS += cen_ringId lib$(PROCEDURE)_DEPLIBS += p9_stop_util lib$(PROCEDURE)_DEPLIBS += p9_stop_api lib$(PROCEDURE)_DEPLIBS += p9_fbc_utils diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C index df1f67b2c..4431c8e01 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C @@ -271,7 +271,7 @@ RingBucket::RingBucket( PlatId i_plat, uint8_t* i_pRingStart, RingDebugMode_t i_ iv_cmnRingMap[ringIndex] = l_quadCmnRings[ringIndex]; } - for( ringIndex = 0; ringIndex < ( EQ::g_eqData.iv_num_instance_rings_scan_addrs * MAX_QUADS_PER_CHIP ); + for( ringIndex = 0; ringIndex < ( EQ::g_chipletData.iv_num_instance_rings_scan_addrs * MAX_QUADS_PER_CHIP ); ringIndex++ ) { iv_instRingMap[ringIndex] = l_quadSpecRings[ringIndex]; @@ -643,12 +643,12 @@ void RingBucket::dumpRings( ) if( iv_plat == PLAT_CME ) { FAPI_INF("---------------------------------CME Rings---------------------------------------"); - chipletNo = EC::g_ecData.iv_num_instance_rings_scan_addrs; + chipletNo = EC::g_chipletData.iv_num_instance_rings_scan_addrs; } else if( iv_plat == PLAT_SGPE ) { FAPI_INF("---------------------------------SGPE Rings--------------------------------------"); - chipletNo = EQ::g_eqData.iv_num_instance_rings_scan_addrs; + chipletNo = EQ::g_chipletData.iv_num_instance_rings_scan_addrs; } else { diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.C b/src/import/chips/p9/utils/imageProcs/p9_ringId.C index 02591046b..fc6b96811 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.C +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.C @@ -465,14 +465,14 @@ const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, CC, RL }; using namespace P9_RID; -ChipletType_t P9_RID::p9_ringid_get_chiplet(RingId_t i_ringId) +ChipletType_t P9_RID::ringid_get_chiplet(RingId_t i_ringId) { return RING_PROPERTIES[i_ringId].iv_type; } -void P9_RID::p9_ringid_get_chiplet_properties( +void P9_RID::ringid_get_chiplet_properties( ChipletType_t i_chiplet, - CHIPLET_DATA** o_cpltData, + ChipletData_t** o_cpltData, GenRingIdList** o_ringComm, GenRingIdList** o_ringInst, RingVariantOrder** o_varOrder, @@ -481,131 +481,131 @@ void P9_RID::p9_ringid_get_chiplet_properties( switch (i_chiplet) { case PERV_TYPE : - *o_cpltData = (CHIPLET_DATA*) &PERV::g_pervData; + *o_cpltData = (ChipletData_t*) &PERV::g_chipletData; *o_ringComm = (GenRingIdList*) PERV::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) PERV::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) PERV::RING_VARIANT_ORDER; - *o_varNumb = sizeof(PERV::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case N0_TYPE : - *o_cpltData = (CHIPLET_DATA*) &N0::g_n0Data; + *o_cpltData = (ChipletData_t*) &N0::g_chipletData; *o_ringComm = (GenRingIdList*) N0::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) N0::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) N0::RING_VARIANT_ORDER; - *o_varNumb = sizeof(N0::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case N1_TYPE : - *o_cpltData = (CHIPLET_DATA*) &N1::g_n1Data; + *o_cpltData = (ChipletData_t*) &N1::g_chipletData; *o_ringComm = (GenRingIdList*) N1::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) N1::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) N1::RING_VARIANT_ORDER; - *o_varNumb = sizeof(N1::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case N2_TYPE : - *o_cpltData = (CHIPLET_DATA*) &N2::g_n2Data; + *o_cpltData = (ChipletData_t*) &N2::g_chipletData; *o_ringComm = (GenRingIdList*) N2::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) N2::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) N2::RING_VARIANT_ORDER; - *o_varNumb = sizeof(N2::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case N3_TYPE : - *o_cpltData = (CHIPLET_DATA*) &N3::g_n3Data; + *o_cpltData = (ChipletData_t*) &N3::g_chipletData; *o_ringComm = (GenRingIdList*) N3::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) N3::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) N3::RING_VARIANT_ORDER; - *o_varNumb = sizeof(N3::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case XB_TYPE : - *o_cpltData = (CHIPLET_DATA*) &XB::g_xbData; + *o_cpltData = (ChipletData_t*) &XB::g_chipletData; *o_ringComm = (GenRingIdList*) XB::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) XB::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) XB::RING_VARIANT_ORDER; - *o_varNumb = sizeof(XB::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case MC_TYPE : - *o_cpltData = (CHIPLET_DATA*) &MC::g_mcData; + *o_cpltData = (ChipletData_t*) &MC::g_chipletData; *o_ringComm = (GenRingIdList*) MC::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) MC::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) MC::RING_VARIANT_ORDER; - *o_varNumb = sizeof(MC::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case OB0_TYPE : - *o_cpltData = (CHIPLET_DATA*) &OB0::g_ob0Data; + *o_cpltData = (ChipletData_t*) &OB0::g_chipletData; *o_ringComm = (GenRingIdList*) OB0::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) OB0::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) OB0::RING_VARIANT_ORDER; - *o_varNumb = sizeof(OB0::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case OB1_TYPE : - *o_cpltData = (CHIPLET_DATA*) &OB1::g_ob1Data; + *o_cpltData = (ChipletData_t*) &OB1::g_chipletData; *o_ringComm = (GenRingIdList*) OB1::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) OB1::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) OB1::RING_VARIANT_ORDER; - *o_varNumb = sizeof(OB1::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case OB2_TYPE : - *o_cpltData = (CHIPLET_DATA*) &OB2::g_ob2Data; + *o_cpltData = (ChipletData_t*) &OB2::g_chipletData; *o_ringComm = (GenRingIdList*) OB2::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) OB2::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) OB2::RING_VARIANT_ORDER; - *o_varNumb = sizeof(OB2::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case OB3_TYPE : - *o_cpltData = (CHIPLET_DATA*) &OB3::g_ob3Data; + *o_cpltData = (ChipletData_t*) &OB3::g_chipletData; *o_ringComm = (GenRingIdList*) OB3::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) OB3::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) OB3::RING_VARIANT_ORDER; - *o_varNumb = sizeof(OB3::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case PCI0_TYPE : - *o_cpltData = (CHIPLET_DATA*) &PCI0::g_pci0Data; + *o_cpltData = (ChipletData_t*) &PCI0::g_chipletData; *o_ringComm = (GenRingIdList*) PCI0::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) PCI0::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) PCI0::RING_VARIANT_ORDER; - *o_varNumb = sizeof(PCI0::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case PCI1_TYPE : - *o_cpltData = (CHIPLET_DATA*) &PCI1::g_pci1Data; + *o_cpltData = (ChipletData_t*) &PCI1::g_chipletData; *o_ringComm = (GenRingIdList*) PCI1::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) PCI1::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) PCI1::RING_VARIANT_ORDER; - *o_varNumb = sizeof(PCI1::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case PCI2_TYPE : - *o_cpltData = (CHIPLET_DATA*) &PCI2::g_pci2Data; + *o_cpltData = (ChipletData_t*) &PCI2::g_chipletData; *o_ringComm = (GenRingIdList*) PCI2::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) PCI2::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) PCI2::RING_VARIANT_ORDER; - *o_varNumb = sizeof(PCI2::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case EQ_TYPE : - *o_cpltData = (CHIPLET_DATA*) &EQ::g_eqData; + *o_cpltData = (ChipletData_t*) &EQ::g_chipletData; *o_ringComm = (GenRingIdList*) EQ::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) EQ::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) EQ::RING_VARIANT_ORDER; - *o_varNumb = sizeof(EQ::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; case EC_TYPE : - *o_cpltData = (CHIPLET_DATA*) &EC::g_ecData; + *o_cpltData = (ChipletData_t*) &EC::g_chipletData; *o_ringComm = (GenRingIdList*) EC::RING_ID_LIST_COMMON; *o_ringInst = (GenRingIdList*) EC::RING_ID_LIST_INSTANCE; *o_varOrder = (RingVariantOrder*) EC::RING_VARIANT_ORDER; - *o_varNumb = sizeof(EC::RingVariants) / sizeof(uint16_t); + *o_varNumb = (*(*o_cpltData)).iv_num_ring_variants; break; default : @@ -613,21 +613,21 @@ void P9_RID::p9_ringid_get_chiplet_properties( *o_ringComm = NULL; *o_ringInst = NULL; *o_varOrder = NULL; - *o_varNumb = 0; + *o_varNumb = 0; break; } } -GenRingIdList* P9_RID::p9_ringid_get_ring_properties(RingId_t i_ringId) +GenRingIdList* P9_RID::ringid_get_ring_properties(RingId_t i_ringId) { - CHIPLET_DATA* l_cpltData; + ChipletData_t* l_cpltData; GenRingIdList* l_ringList[2]; // 0: common, 1: instance RingVariantOrder* l_varOrder; uint8_t l_varNumb; int i, j, n; - P9_RID::p9_ringid_get_chiplet_properties( - P9_RID::p9_ringid_get_chiplet(i_ringId), + P9_RID::ringid_get_chiplet_properties( + P9_RID::ringid_get_chiplet(i_ringId), &l_cpltData, &l_ringList[0], &l_ringList[1], &l_varOrder, &l_varNumb); if (!l_ringList[0]) diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H index cdac737f4..08a65527b 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H @@ -175,13 +175,6 @@ extern const RingVariantOrder RING_VARIANT_ORDER[]; namespace PERV { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -210,24 +203,18 @@ enum RingOffset occ_repr = (1 | INSTANCE_RING_MARK), }; -static const CHIPLET_DATA g_pervData = +static const ChipletData_t g_chipletData = { 1, // Pervasive Chiplet ID is 1 15, // 15 common rings for pervasive chiplet 2, // 2 instance specific rings for pervasive chiplet - 2 + 2, + 2, // 2 ring variants: BASE, RL }; }; // end of namespace PERV namespace N0 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -246,24 +233,18 @@ enum RingOffset n0_cxa0_repr = (2 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_n0Data = +static const ChipletData_t g_chipletData = { - 2, // N0 Chiplet ID is 2. - 9, // 9 common rings for N0 Chiplet - 3, // 3 instance specific rings for N0 chiplet - 3 + 2, // N0 Chiplet ID is 2. + 9, // 9 common rings for N0 Chiplet + 3, // 3 instance specific rings for N0 chiplet + 3, + 2, // 2 ring variants: BASE, RL }; }; namespace N1 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -286,24 +267,18 @@ enum RingOffset n1_mcs23_repr = (3 | INSTANCE_RING_MARK), }; -static const CHIPLET_DATA g_n1Data = +static const ChipletData_t g_chipletData = { 3, // N1 Chiplet ID is 3. 12, // 12 common rings for N1 Chiplet 4, // 4 instance specific rings for N1 chiplet - 4 + 4, + 2, // 2 ring variants: BASE, RL }; }; namespace N2 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -322,24 +297,18 @@ enum RingOffset n2_psi_repr = (2 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_n2Data = +static const ChipletData_t g_chipletData = { 4, // N2 Chiplet ID is 4. 9, // 9 common rings for N2 Chiplet 3, // 3 instance specific rings for N2 chiplet - 3 + 3, + 2, // 2 ring variants: BASE, RL }; }; namespace N3 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -359,24 +328,18 @@ enum RingOffset n3_np_repr = (2 | INSTANCE_RING_MARK), }; -static const CHIPLET_DATA g_n3Data = +static const ChipletData_t g_chipletData = { 5, // N3 Chiplet ID is 5 10,// 10 common rings for N3 Chiplet 3, // 3 instance specific rings for N3 chiplet - 3 + 3, + 2, // 2 ring variants: BASE, RL }; }; namespace XB { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -402,24 +365,18 @@ enum RingOffset xb_io2_repr = (3 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_xbData = +static const ChipletData_t g_chipletData = { 6, // X-Bus Chiplet ID is 6 15, // 15 common rings for X-Bus Chiplet 4, // 4 instance specific rings for XB chiplet - 4 + 4, + 2, // 2 ring variants: BASE, RL }; }; // end of namespace XB namespace MC { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -446,24 +403,18 @@ enum RingOffset mc_iom23_repr = (2 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_mcData = +static const ChipletData_t g_chipletData = { 7, // MC Chiplet ID range is 7 - 8. The base ID is 7. 16, // 16 common rings for MC Chiplet 3, // 3 instance specific rings for each MC instance - 3 + 3, + 2, // 2 ring variants: BASE, RL }; }; // end of namespace MC namespace OB0 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -479,24 +430,18 @@ enum RingOffset ob0_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_ob0Data = +static const ChipletData_t g_chipletData = { 9, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet - 1 + 1, + 2, // 2 ring variants: BASE, RL }; }; // end of namespace OB0 namespace OB1 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -512,25 +457,19 @@ enum RingOffset ob1_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_ob1Data = +static const ChipletData_t g_chipletData = { 10, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet - 1 + 1, + 2, // 2 ring variants: BASE, RL }; }; // end of namespace OB1 namespace OB2 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -546,24 +485,18 @@ enum RingOffset ob2_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_ob2Data = +static const ChipletData_t g_chipletData = { 11, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet - 1 + 1, + 2, // 2 ring variants: BASE, RL }; }; // end of namespace OB2 namespace OB3 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -579,23 +512,18 @@ enum RingOffset ob3_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_ob3Data = +static const ChipletData_t g_chipletData = { 12, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet - 1 + 1, + 2, // 2 ring variants: BASE, RL }; }; // end of namespace OB2 + namespace PCI0 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -608,24 +536,18 @@ enum RingOffset pci0_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_pci0Data = +static const ChipletData_t g_chipletData = { 13, // PCI0 Chiplet Chiplet ID is 13 5, // 5 common rings for PCI0 chiplet 1, // 1 instance specific rings for PCI0 chiplet - 1 + 1, + 2, // 2 ring variants: BASE, RL }; }; namespace PCI1 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -638,24 +560,18 @@ enum RingOffset pci1_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_pci1Data = +static const ChipletData_t g_chipletData = { 14, // PCI1 Chiplet Chiplet ID is 14 5, // 5 common rings for PCI1 chiplet 1, // 1 instance specific rings for PCI1 chiplet - 1 + 1, + 2, // 2 ring variants: BASE, RL }; }; namespace PCI2 { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -668,26 +584,18 @@ enum RingOffset pci2_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_pci2Data = +static const ChipletData_t g_chipletData = { 15, // PCI2 Chiplet Chiplet ID is 15 5, // 5 common rings for PCI2 chiplet 1, // 1 instance specific rings for PCI2 chiplet - 1 + 1, + 2, // 2 ring variants: BASE, RL }; - }; namespace EQ { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_cacheContained; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -767,25 +675,18 @@ enum RingOffset ex_l3_refr_time = (4 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_eqData = +static const ChipletData_t g_chipletData = { 16, // Quad Chiplet ID range is 16 - 21. The base ID is 16. 66, // 66 common rings for Quad chiplet. 5, // 5 instance specific rings for each EQ chiplet - 9 // 9 different rings since 2 per EX ring and 1 per EQ + 9, // 9 different rings since 2 per EX ring and 1 per EQ + 3, // 3 ring variants: BASE, CC, RL }; }; // end of namespace EQ namespace EC { -// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number) -struct RingVariants -{ - uint16_t iv_base; - uint16_t iv_cacheContained; - uint16_t iv_riskLevel; -}; - enum RingOffset { // Common Rings @@ -799,19 +700,20 @@ enum RingOffset ec_repr = (0 | INSTANCE_RING_MARK) }; -static const CHIPLET_DATA g_ecData = +static const ChipletData_t g_chipletData = { 32, // Core Chiplet ID range is 32-55. The base ID is 32. 6, // 6 common rings for Core chiplet 1, // 1 instance specific ring for each Core chiplet - 1 + 1, + 3, // 3 ring variants: BASE, CC, RL }; }; // end of namespace EC #ifndef __PPE__ -static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = +static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { { PERV::perv_fure , "perv_fure" , PERV_TYPE }, // 0 { PERV::perv_gptr , "perv_gptr" , PERV_TYPE }, // 1 @@ -1070,7 +972,7 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = #endif #ifdef __PPE__ -static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = +static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { { PERV::perv_fure , PERV_TYPE }, // 0 { PERV::perv_gptr , PERV_TYPE }, // 1 @@ -1328,25 +1230,27 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = }; #endif -// returns our own chiplet enum value for this ringId + +// Returns our own chiplet enum value for this ringId ChipletType_t -p9_ringid_get_chiplet( +ringid_get_chiplet( RingId_t i_ringId); -// returns data structures defined for chiplet type +// Returns data structures defined for chiplet type // as determined by ringId void -p9_ringid_get_chiplet_properties( +ringid_get_chiplet_properties( ChipletType_t i_chiplet, - CHIPLET_DATA** o_cpltData, + ChipletData_t** o_cpltData, GenRingIdList** o_ringComm, GenRingIdList** o_ringInst, RingVariantOrder** o_varOrder, uint8_t* o_varNumb); -// returns properties of a ring as determined by ringId +// Returns properties of a ring as determined by ringId GenRingIdList* -p9_ringid_get_ring_properties( +ringid_get_ring_properties( RingId_t i_ringId); + #endif diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.C b/src/import/chips/p9/utils/imageProcs/p9_tor.C index e128ec3cf..eabe01576 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.C +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.C @@ -46,6 +46,10 @@ namespace P9_RID { #include "p9_ringId.H" } +namespace CEN_RID +{ +#include "cen_ringId.H" +} #include "p9_scan_compression.H" #include "p9_infrastruct_help.H" @@ -83,23 +87,27 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section char* o_ringName, // Name of ring uint32_t i_dbgl ) // Debug option { - int rc = TOR_SUCCESS; - uint32_t torMagic; - uint32_t tor_slot_no = 0; // TOR slot number (within a TOR chiplet section) - uint16_t dd_level_offset; // Local DD level offset, if any (wrt i_ringSection) - uint32_t acc_offset = 0; // Accumulating offset to next TOR offset - uint32_t ppe_offset = 0; // Local offset to where SBE PPE ring section starts - uint32_t ppe_cplt_offset = 0; // Local offset to where the pool of chiplets starts - uint32_t cplt_offset = 0; // Local offset to where a specific chiplet section starts - uint16_t ring_offset = 0; // Local offset to where SBE ring container/block starts - uint32_t ring_size = 0; // Size of whole ring container/block. + int rc = TOR_SUCCESS; + uint32_t torMagic = 0xffffffff; + ChipType_t chipType = INVALID_CHIP_TYPE; + uint32_t tor_slot_no = 0; // TOR slot number (within a TOR chiplet section) + uint16_t dd_level_offset; // Local DD level offset, if any (wrt i_ringSection) + uint32_t acc_offset = 0; // Accumulating offset to next TOR offset + uint32_t ppe_offset = 0; // Local offset to where SBE PPE ring section starts + uint32_t ppe_cplt_offset = 0; // Local offset to where the pool of chiplets starts + uint32_t cplt_offset = 0; // Local offset to where a specific chiplet section starts + uint16_t ring_offset = 0; // Local offset to where SBE ring container/block starts + uint32_t ring_size = 0; // Size of whole ring container/block. RingVariantOrder* ring_variant_order; - GenRingIdList* ring_id_list_common; - GenRingIdList* ring_id_list_instance; - CHIPLET_DATA* l_cpltData; - uint8_t l_num_variant; + GenRingIdList* ring_id_list_common; + GenRingIdList* ring_id_list_instance; + ChipletData_t* l_cpltData; + uint8_t l_num_variant; + ChipletType_t numChiplets = 0; + const RingProperties_t* ringProperties; torMagic = be32toh( ((TorHeader_t*)i_ringSection)->magic ); + chipType = ((TorHeader_t*)i_ringSection)->chipType; // Calculate the offset (wrt start of ringSection) to the SBE PPE // ring section. This offset, ppe_offset, will point to the @@ -109,13 +117,25 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section dd_level_offset = i_ddLevelOffset; ppe_offset = *(uint32_t*)((uint8_t*)i_ringSection + dd_level_offset); ppe_offset = be32toh(ppe_offset); + numChiplets = P9_RID::SBE_NOOF_CHIPLETS; + ringProperties = &P9_RID::RING_PROPERTIES[0]; } else if (torMagic == TOR_MAGIC_SBE || - torMagic == TOR_MAGIC_OVRD || + (torMagic == TOR_MAGIC_OVRD && (chipType == CT_P9N || chipType == CT_P9C)) || torMagic == TOR_MAGIC_OVLY) { ppe_offset = 0; dd_level_offset = 0; + numChiplets = P9_RID::SBE_NOOF_CHIPLETS; + ringProperties = &P9_RID::RING_PROPERTIES[0]; + } + else if (torMagic == TOR_MAGIC_CEN || + (torMagic == TOR_MAGIC_OVRD && chipType == CT_CEN)) + { + ppe_offset = 0; + dd_level_offset = 0; + numChiplets = CEN_RID::CEN_NOOF_CHIPLETS; + ringProperties = &CEN_RID::RING_PROPERTIES[0]; } else { @@ -129,17 +149,31 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section ppe_cplt_offset = ppe_offset + sizeof(TorHeader_t); // Looper for each SBE chiplet - for (ChipletType_t iCplt = 0; iCplt < P9_RID::SBE_NOOF_CHIPLETS; iCplt++) + for (ChipletType_t iCplt = 0; iCplt < numChiplets; iCplt++) { - P9_RID::p9_ringid_get_chiplet_properties( - iCplt, - &l_cpltData, - &ring_id_list_common, - &ring_id_list_instance, - &ring_variant_order, - &l_num_variant); - - if (!ring_id_list_common) + if (torMagic == TOR_MAGIC_CEN || + (torMagic == TOR_MAGIC_OVRD && chipType == CT_CEN)) + { + CEN_RID::ringid_get_chiplet_properties( + iCplt, + &l_cpltData, + &ring_id_list_common, + &ring_id_list_instance, + &ring_variant_order, + &l_num_variant); + } + else + { + P9_RID::ringid_get_chiplet_properties( + iCplt, + &l_cpltData, + &ring_id_list_common, + &ring_id_list_instance, + &ring_variant_order, + &l_num_variant); + } + + if (!ring_id_list_common && !ring_id_list_instance) { MY_ERR("Chiplet=%d is not valid for SBE. \n", iCplt); return TOR_INVALID_CHIPLET; @@ -171,12 +205,12 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section } if ( ( strcmp( (ring_id_list_common + i)->ringName, - P9_RID::RING_PROPERTIES[i_ringId].iv_name) == 0 ) && + ringProperties[i_ringId].iv_name) == 0 ) && ( i_RingVariant == ring_variant_order->variant[iVariant] || torMagic == TOR_MAGIC_OVRD || torMagic == TOR_MAGIC_OVLY ) ) { - strcpy(o_ringName, P9_RID::RING_PROPERTIES[i_ringId].iv_name); + strcpy(o_ringName, ringProperties[i_ringId].iv_name); acc_offset = dd_level_offset + ppe_cplt_offset + iCplt * sizeof(TorPpeBlock_t); @@ -287,159 +321,163 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section // // Sequentially walk the TOR slots within the chiplet's INSTANCE section // - tor_slot_no = 0; - - for ( uint8_t i = (ring_id_list_instance + 0)->instanceIdMin; - i < (ring_id_list_instance + 0)->instanceIdMax + 1 ; i++ ) + if (ring_id_list_instance) { - for (uint8_t j = 0; j < l_cpltData->iv_num_instance_rings; j++) + + tor_slot_no = 0; + + for ( uint8_t i = (ring_id_list_instance + 0)->instanceIdMin; + i < (ring_id_list_instance + 0)->instanceIdMax + 1 ; i++ ) { - for (uint8_t iVariant = 0; iVariant < l_num_variant ; iVariant++) + for (uint8_t j = 0; j < l_cpltData->iv_num_instance_rings; j++) { - if (i_dbgl > 2) + for (uint8_t iVariant = 0; iVariant < l_num_variant ; iVariant++) { - MY_INF(" Ring name %s Cplt instance ring id %d Variant id %d Instance id %d\n", - (ring_id_list_instance + j)->ringName, j, iVariant, i); - } + if (i_dbgl > 2) + { + MY_INF(" Ring name %s Cplt instance ring id %d Variant id %d Instance id %d\n", + (ring_id_list_instance + j)->ringName, j, iVariant, i); + } - if (strcmp( (ring_id_list_instance + j)->ringName, - P9_RID::RING_PROPERTIES[i_ringId].iv_name) == 0) - { - if ( io_instanceId >= (ring_id_list_instance + 0)->instanceIdMin - && io_instanceId <= (ring_id_list_instance + 0)->instanceIdMax ) + if (strcmp( (ring_id_list_instance + j)->ringName, + ringProperties[i_ringId].iv_name) == 0) { - if (i == io_instanceId && i_RingVariant == ring_variant_order->variant[iVariant]) + if ( io_instanceId >= (ring_id_list_instance + 0)->instanceIdMin + && io_instanceId <= (ring_id_list_instance + 0)->instanceIdMax ) { - strcpy(o_ringName, P9_RID::RING_PROPERTIES[i_ringId].iv_name); - - acc_offset = dd_level_offset + - ppe_cplt_offset + - iCplt * sizeof(TorPpeBlock_t) + - sizeof(cplt_offset); // Jump to instance offset - cplt_offset = *(uint32_t*)( (uint8_t*)i_ringSection + - acc_offset ); - cplt_offset = be32toh(cplt_offset); - - acc_offset = cplt_offset + - dd_level_offset + - ppe_cplt_offset; - ring_offset = *(uint16_t*)( (uint8_t*)i_ringSection + - acc_offset + - tor_slot_no * sizeof(ring_offset) ); - ring_offset = be16toh(ring_offset); - - if (i_RingBlockType == GET_SINGLE_RING) + if (i == io_instanceId && i_RingVariant == ring_variant_order->variant[iVariant]) { + strcpy(o_ringName, ringProperties[i_ringId].iv_name); + acc_offset = dd_level_offset + ppe_cplt_offset + - cplt_offset + - ring_offset; - ring_size = be16toh( ((CompressedScanData*) - ((uint8_t*)i_ringSection + - acc_offset))->iv_size ); - io_RingType = INSTANCE_RING; - - if (ring_offset) + iCplt * sizeof(TorPpeBlock_t) + + sizeof(cplt_offset); // Jump to instance offset + cplt_offset = *(uint32_t*)( (uint8_t*)i_ringSection + + acc_offset ); + cplt_offset = be32toh(cplt_offset); + + acc_offset = cplt_offset + + dd_level_offset + + ppe_cplt_offset; + ring_offset = *(uint16_t*)( (uint8_t*)i_ringSection + + acc_offset + + tor_slot_no * sizeof(ring_offset) ); + ring_offset = be16toh(ring_offset); + + if (i_RingBlockType == GET_SINGLE_RING) { - if (io_ringBlockSize == 0) + acc_offset = dd_level_offset + + ppe_cplt_offset + + cplt_offset + + ring_offset; + ring_size = be16toh( ((CompressedScanData*) + ((uint8_t*)i_ringSection + + acc_offset))->iv_size ); + io_RingType = INSTANCE_RING; + + if (ring_offset) { + if (io_ringBlockSize == 0) + { + if (i_dbgl > 0) + { + MY_INF("\tio_ringBlockSize is zero. Returning required size.\n"); + } + + io_ringBlockSize = ring_size; + return 0; + } + + if (io_ringBlockSize < ring_size) + { + MY_ERR("\tio_ringBlockSize is less than required size.\n"); + return TOR_BUFFER_TOO_SMALL; + } + if (i_dbgl > 0) { - MY_INF("\tio_ringBlockSize is zero. Returning required size.\n"); + MY_INF(" ring container of %s is found in the SBE image container \n", + o_ringName); } - io_ringBlockSize = ring_size; - return 0; - } + memcpy( (uint8_t*)(*io_ringBlockPtr), (uint8_t*)i_ringSection + acc_offset, + (size_t)ring_size); - if (io_ringBlockSize < ring_size) - { - MY_ERR("\tio_ringBlockSize is less than required size.\n"); - return TOR_BUFFER_TOO_SMALL; - } + io_ringBlockSize = ring_size; - if (i_dbgl > 0) - { - MY_INF(" ring container of %s is found in the SBE image container \n", - o_ringName); - } + if (i_dbgl > 0) + { + MY_INF(" After get_ring_from_sbe_image Size %d \n", io_ringBlockSize); + } - memcpy( (uint8_t*)(*io_ringBlockPtr), (uint8_t*)i_ringSection + acc_offset, - (size_t)ring_size); + rc = TOR_RING_FOUND; + } + else + { + if (i_dbgl > 0) + { + MY_INF(" Ring %s not found in SBE section \n", o_ringName); + } - io_ringBlockSize = ring_size; + rc = TOR_RING_NOT_FOUND; + } if (i_dbgl > 0) { - MY_INF(" After get_ring_from_sbe_image Size %d \n", io_ringBlockSize); + MY_INF(" Hex details (SBE) for Chiplet #%d: \n" + " DD number section's offset to DD level section = 0x%08x \n" + " DD level section's offset to PpeType = 0x%08x \n" + " PpeType section's offset to chiplet = 0x%08x \n" + " Chiplet section's offset to RS4 header = 0x%08x \n" + " Full offset to RS4 header = 0x%08x \n" + " Ring size = 0x%08x \n", + i, dd_level_offset, ppe_cplt_offset, cplt_offset, ring_offset, acc_offset, ring_size); } - rc = TOR_RING_FOUND; + return rc; } - else + else if (i_RingBlockType == PUT_SINGLE_RING) { - if (i_dbgl > 0) + if (ring_offset) { - MY_INF(" Ring %s not found in SBE section \n", o_ringName); + MY_ERR("Ring container is already present in the SBE section \n"); + return TOR_RING_AVAILABLE_IN_RINGSECTION; } - rc = TOR_RING_NOT_FOUND; - } + // Special [mis]use of io_ringBlockPtr and io_ringBlockSize: + // Put location of chiplet's instance section into ringBlockPtr + memcpy( (uint8_t*)(*io_ringBlockPtr), &acc_offset, sizeof(acc_offset)); + // Put location of ring_offset slot into ringBlockSize + io_ringBlockSize = acc_offset + (tor_slot_no * sizeof(ring_offset)); - if (i_dbgl > 0) - { - MY_INF(" Hex details (SBE) for Chiplet #%d: \n" - " DD number section's offset to DD level section = 0x%08x \n" - " DD level section's offset to PpeType = 0x%08x \n" - " PpeType section's offset to chiplet = 0x%08x \n" - " Chiplet section's offset to RS4 header = 0x%08x \n" - " Full offset to RS4 header = 0x%08x \n" - " Ring size = 0x%08x \n", - i, dd_level_offset, ppe_cplt_offset, cplt_offset, ring_offset, acc_offset, ring_size); + return TOR_RING_FOUND; } - - return rc; - } - else if (i_RingBlockType == PUT_SINGLE_RING) - { - if (ring_offset) + else { - MY_ERR("Ring container is already present in the SBE section \n"); - return TOR_RING_AVAILABLE_IN_RINGSECTION; + MY_ERR("Ring block type (i_RingBlockType=%d) is not supported for SBE \n", i_RingBlockType); + return TOR_INVALID_RING_BLOCK_TYPE; } - - // Special [mis]use of io_ringBlockPtr and io_ringBlockSize: - // Put location of chiplet's instance section into ringBlockPtr - memcpy( (uint8_t*)(*io_ringBlockPtr), &acc_offset, sizeof(acc_offset)); - // Put location of ring_offset slot into ringBlockSize - io_ringBlockSize = acc_offset + (tor_slot_no * sizeof(ring_offset)); - - return TOR_RING_FOUND; } - else + } + else + { + if (i_dbgl > 0) { - MY_ERR("Ring block type (i_RingBlockType=%d) is not supported for SBE \n", i_RingBlockType); - return TOR_INVALID_RING_BLOCK_TYPE; + MY_INF(" SBE ring instance ID %d is invalid, Valid ID is from %d to %d \n", + io_instanceId, (ring_id_list_instance + 0)->instanceIdMin, + (ring_id_list_instance + 0)->instanceIdMax); } + + return TOR_INVALID_INSTANCE_ID; } } - else - { - if (i_dbgl > 0) - { - MY_INF(" SBE ring instance ID %d is invalid, Valid ID is from %d to %d \n", - io_instanceId, (ring_id_list_instance + 0)->instanceIdMin, - (ring_id_list_instance + 0)->instanceIdMax); - } - return TOR_INVALID_INSTANCE_ID; - } + tor_slot_no++; } - - tor_slot_no++; } } - } + } // if (ring_id_list_instance) } if (i_dbgl > 0) @@ -510,13 +548,13 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio GenRingIdList* ring_id_list_common = NULL; GenRingIdList* ring_id_list_instance = NULL; - uint8_t l_num_variant = (uint8_t)sizeof(P9_RID::EQ::RingVariants) / sizeof(uint16_t); + uint8_t l_num_variant = P9_RID::EQ::g_chipletData.iv_num_ring_variants; ring_id_list_common = (GenRingIdList*) P9_RID::EQ::RING_ID_LIST_COMMON; ring_id_list_instance = (GenRingIdList*) P9_RID::EQ::RING_ID_LIST_INSTANCE; uint32_t local = 0; - for (uint8_t i = 0; i < P9_RID::EQ::g_eqData.iv_num_common_rings ; i++) + for (uint8_t i = 0; i < P9_RID::EQ::g_chipletData.iv_num_common_rings ; i++) { for (uint8_t j = 0; j < l_num_variant ; j++) { @@ -628,7 +666,7 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio for(uint8_t i = (ring_id_list_instance + 0)->instanceIdMin; i < (ring_id_list_instance + 0)->instanceIdMax + 1 ; i++) { - for (uint8_t j = 0; j < P9_RID::EQ::g_eqData.iv_num_instance_rings; j++) + for (uint8_t j = 0; j < P9_RID::EQ::g_chipletData.iv_num_instance_rings; j++) { for(uint8_t k = 0; k < l_num_variant ; k++) { @@ -817,13 +855,13 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section GenRingIdList* ring_id_list_common = NULL; GenRingIdList* ring_id_list_instance = NULL; - uint8_t l_num_variant = (uint8_t)sizeof(P9_RID::EC::RingVariants) / sizeof(uint16_t); + uint8_t l_num_variant = P9_RID::EC::g_chipletData.iv_num_ring_variants; ring_id_list_common = (GenRingIdList*) P9_RID::EC::RING_ID_LIST_COMMON; ring_id_list_instance = (GenRingIdList*) P9_RID::EC::RING_ID_LIST_INSTANCE; uint32_t local = 0; - for (uint8_t i = 0; i < P9_RID::EC::g_ecData.iv_num_common_rings ; i++) + for (uint8_t i = 0; i < P9_RID::EC::g_chipletData.iv_num_common_rings ; i++) { for (uint8_t j = 0; j < l_num_variant ; j++) { @@ -935,7 +973,7 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section i <= (ring_id_list_instance + 0)->instanceIdMax; i++ ) { - for (uint8_t j = 0; j < P9_RID::EC::g_ecData.iv_num_instance_rings; j++) + for (uint8_t j = 0; j < P9_RID::EC::g_chipletData.iv_num_instance_rings; j++) { for (uint8_t k = 0; k < l_num_variant ; k++) { @@ -1162,7 +1200,8 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr } else if ( torMagic == TOR_MAGIC_SBE || torMagic == TOR_MAGIC_OVRD || - torMagic == TOR_MAGIC_OVLY ) + torMagic == TOR_MAGIC_OVLY || + torMagic == TOR_MAGIC_CEN ) { if ( i_PpeType == PT_CME || i_PpeType == PT_SGPE || i_RingBlockType == GET_DD_LEVEL_RINGS @@ -1247,7 +1286,7 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr io_ringBlockSize = ddBlockSize; - return TOR_RING_BLOCKS_FOUND; + return TOR_RING_FOUND; } else if (i_RingBlockType == GET_PPE_LEVEL_RINGS) { @@ -1320,7 +1359,7 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr (size_t)l_ppe_size); io_ringBlockSize = l_ppe_size; - return TOR_RING_BLOCKS_FOUND; + return TOR_RING_FOUND; } else if ( i_RingBlockType == GET_SINGLE_RING || i_RingBlockType == PUT_SINGLE_RING ) @@ -1329,7 +1368,8 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr ( torMagic == TOR_MAGIC_HW || torMagic == TOR_MAGIC_SBE || torMagic == TOR_MAGIC_OVRD || - torMagic == TOR_MAGIC_OVLY ) ) + torMagic == TOR_MAGIC_OVLY || + torMagic == TOR_MAGIC_CEN ) ) { rc = get_ring_from_sbe_image( i_ringSection, i_ringId, @@ -1360,7 +1400,7 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr io_ringBlockSize ); } - return TOR_RING_BLOCKS_FOUND; + return TOR_RING_FOUND; } } else if ( i_PpeType == PT_CME && @@ -1426,7 +1466,7 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr io_ringBlockSize ); } - return TOR_RING_BLOCKS_FOUND; + return TOR_RING_FOUND; } } else if ( i_PpeType == PT_SGPE && @@ -1492,7 +1532,7 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr io_ringBlockSize ); } - return TOR_RING_BLOCKS_FOUND; + return TOR_RING_FOUND; } } else diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.H b/src/import/chips/p9/utils/imageProcs/p9_tor.H index 821362f59..ec6e644ac 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.H +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.H @@ -98,7 +98,6 @@ typedef enum TorOffsetSize #define TOR_SUCCESS 0 #define TOR_RING_FOUND 0 -#define TOR_RING_BLOCKS_FOUND 0 #define TOR_RING_NOT_FOUND 1 #define TOR_AMBIGUOUS_API_PARMS 2 #define TOR_SECTION_NOT_FOUND 3 diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.mk b/src/import/chips/p9/utils/imageProcs/p9_tor.mk index 6e59c38f4..a9ef8b839 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.mk +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.mk @@ -24,7 +24,8 @@ # IBM_PROLOG_END_TAG PROCEDURE=p9_tor lib$(PROCEDURE)_DEPLIBS += p9_ringId -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/xip) +lib$(PROCEDURE)_DEPLIBS += cen_ringId +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/centaur/utils/imageProcs) $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/common/utils/imageProcs) $(call BUILD_PROCEDURE) diff --git a/src/usr/isteps/pm/pm.mk b/src/usr/isteps/pm/pm.mk index 147d9e851..b6ea71771 100644 --- a/src/usr/isteps/pm/pm.mk +++ b/src/usr/isteps/pm/pm.mk @@ -33,6 +33,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/pmlib/include/registers/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/lib/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/utils/stopreg/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/utils/imageProcs/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ HWP_PM_PATH += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/pm @@ -44,9 +45,9 @@ EXTRAINCDIR += ${HWP_ACC_PATH} HWP_XIP_PATH += ${ROOTPATH}/src/import/chips/p9/xip EXTRAINCDIR += ${HWP_XIP_PATH} HWP_IMAGEPROCS_PATH += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs/ +HWP_CEN_IMAGEPROCS_PATH += ${ROOTPATH}/src/import/chips/centaur/utils/imageProcs/ HWP_STOPUTIL_PATH += ${ROOTPATH}/src/import/chips/p9/procedures/utils/stopreg/ EXTRAINCDIR += ${HWP_STOPUTIL_PATH} -EXTRAINCDIR += ${HWP_IMAGEPROCS_PATH} NEST_UTIL_PATH += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/nest EXTRAINCDIR += ${NEST_UTIL_PATH} @@ -66,7 +67,7 @@ OBJS += occCheckstop.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${HWP_PM_PATH} ${HWP_CUST_PATH} ${HWP_ACC_PATH} VPATH += ${HWP_XIP_PATH} ${HWP_IMAGEPROCS_PATH} -VPATH += ${HWP_XIP_PATH} ${HWP_IMAGEPROCS_PATH} ${HWP_STOPUTIL_PATH} +VPATH += ${HWP_XIP_PATH} ${HWP_IMAGEPROCS_PATH} ${HWP_CEN_IMAGEPROCS_PATH} ${HWP_STOPUTIL_PATH} VPATH += ${NEST_UTIL_PATH} # TODO RTC: 164237 @@ -105,6 +106,7 @@ include ${HWP_IMAGEPROCS_PATH}/p9_dd_container.mk include ${HWP_IMAGEPROCS_PATH}/p9_tor.mk include ${HWP_IMAGEPROCS_PATH}/p9_ring_identification.mk include ${HWP_IMAGEPROCS_PATH}/p9_ringId.mk +include ${HWP_CEN_IMAGEPROCS_PATH}/cen_ringId.mk include ${HWP_STOPUTIL_PATH}/p9_stop_util.mk include ${HWP_STOPUTIL_PATH}/p9_stop_api.mk include ${HWP_IMAGEPROCS_PATH}/p9_scan_compression.mk diff --git a/src/usr/sbe/makefile b/src/usr/sbe/makefile index 1f072046f..f484185e2 100644 --- a/src/usr/sbe/makefile +++ b/src/usr/sbe/makefile @@ -32,6 +32,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ ## pointer to common HWP files EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/utils/imageProcs/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/lib/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/utils/stopreg/ @@ -42,7 +43,7 @@ EXTRAINCDIR += ${HWP_ACCESSORS_PATH}/ HWP_XIP_PATH += ${ROOTPATH}/src/import/chips/p9/xip EXTRAINCDIR += ${HWP_XIP_PATH}/ UTILS_PATH += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs -EXTRAINCDIR += ${UTILS_PATH}/ +CEN_UTILS_PATH += ${ROOTPATH}/src/import/chips/centaur/utils/imageProcs OBJS += sbe_update.o @@ -50,7 +51,7 @@ SUBDIRS += test.d ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${HWP_CUSTOMIZE_PATH} ${HWP_ACCESSORS_PATH} ${HWP_XIP_PATH} -VPATH += ${UTILS_PATH} +VPATH += ${UTILS_PATH} ${CEN_UTILS_PATH} include ${ROOTPATH}/procedure.rules.mk @@ -62,6 +63,7 @@ include ${HWP_ACCESSORS_PATH}/p9_mvpd_ring_funcs.mk include ${HWP_XIP_PATH}/p9_xip_image.mk include ${UTILS_PATH}/p9_ring_identification.mk include ${UTILS_PATH}/p9_ringId.mk +include ${CEN_UTILS_PATH}/cen_ringId.mk include ${UTILS_PATH}/p9_scan_compression.mk include ${UTILS_PATH}/p9_tor.mk |
