diff options
12 files changed, 2405 insertions, 72 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C index 65acae295..17643e5fc 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C @@ -36,6 +36,7 @@ #include <exp_inband.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/exp_draminit_utils.H> +#include <lib/shared/exp_consts.H> /// /// @brief Initializes DRAM diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C index 3e97ba3b4..c2d4fa1e6 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C @@ -60,6 +60,90 @@ void setup_cmd_params(const uint32_t i_cmd_data_crc, host_fw_command_struct& o_c memset(o_cmd.padding, 0, sizeof(o_cmd.padding)); } +/// +/// @brief user_input_msdg structure setup +/// @tparam T the fapi2 TargetType +/// @param[in] i_target the fapi2 target +/// @param[out] o_phy_params the phy params data struct +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + user_input_msdg& o_phy_params) +{ + for (const auto l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + fapi2::ReturnCode l_rc; + + // Create an object + auto l_set_phy_params = phy_params(l_port, l_rc); + FAPI_TRY(l_rc, "Unable to set parameters for target %s", mss::c_str(i_target)); + + // Set the params by fetching them from the attributes + FAPI_TRY(l_set_phy_params.setup_DimmType(l_port, o_phy_params)); + FAPI_TRY(l_set_phy_params.setup_CsPresent(l_port, o_phy_params)); + FAPI_TRY(l_set_phy_params.setup_DramDataWidth(l_port, o_phy_params)); + FAPI_TRY(l_set_phy_params.setup_Height3DS(l_port, o_phy_params)); + FAPI_TRY(l_set_phy_params.set_ActiveDBYTE(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_ActiveNibble(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_AddrMirror(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_ColumnAddrWidth(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_RowAddrWidth(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_SpdCLSupported(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_SpdtAAmin(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_Rank4Mode(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_DDPCompatible(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_TSV8HSupport(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_MRAMSupport(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_NumPStates(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_Frequency(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_PhyOdtImpedance(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_PhyDrvImpedancePU(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_PhyDrvImpedancePD(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_PhySlewRate(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_ATxImpedance(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_ATxSlewRate(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_CKTxImpedance(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_CKTxSlewRate(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_AlertOdtImpedance(o_phy_params)); + + // TK to use the rank API once it's available + // For now we are assuming ranks 2 and 3 are on DIMM1 for RttNom, RttWr and RttPark + FAPI_TRY(l_set_phy_params.set_RttNom(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_RttWr(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_RttPark(o_phy_params)); + + FAPI_TRY(l_set_phy_params.set_DramDic(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_DramWritePreamble(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_DramReadPreamble(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_PhyEqualization(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_InitVrefDQ(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_InitPhyVref(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_OdtWrMapCs(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_OdtRdMapCs(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_Geardown(o_phy_params)); + + // TK need to check if this also includes RC0E + FAPI_TRY(l_set_phy_params.set_CALatencyAdder(o_phy_params)); + + FAPI_TRY(l_set_phy_params.set_BistCALMode(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_BistCAParityLatency(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_RcdDic(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_RcdVoltageCtrl(o_phy_params)); + + // TK check bit ordering here for RcdIBTCtrl and RcdDBDic + FAPI_TRY(l_set_phy_params.set_RcdIBTCtrl(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_RcdDBDic(o_phy_params)); + + FAPI_TRY(l_set_phy_params.set_RcdSlewRate(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_EmulationSupport(o_phy_params)); + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + namespace check { diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H index ca835cff2..7ab0b0c59 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H @@ -39,6 +39,11 @@ #include <fapi2.H> #include <lib/shared/exp_consts.H> #include <exp_data_structs.H> +#include <mss_generic_attribute_getters.H> +#include <mss_explorer_attribute_getters.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/mss_buffer_utils.H> namespace mss { @@ -46,6 +51,78 @@ namespace exp { /// +/// @brief defines the supported DIMM types in Explorer +/// +enum msdg_dimm_types +{ + MSDG_UDIMM = 0x0000, + MSDG_RDIMM = 0x0001, + MSDG_LRDIMM = 0x0002, +}; + +/// +/// @brief defines the supported DRAM data width in Explorer +/// +enum msdg_dram_data_width +{ + MSDG_X4 = 0x0004, + MSDG_X8 = 0x0008, + MSDG_X16 = 0x0010, +}; + +/// +/// @brief defines the valid 3DS stack in Explorer +/// +enum msdg_height_3DS +{ + MSDG_SDP = 0x0000, + MSDG_DDP_QDP = 0x0002, + MSDG_3DS = 0x0004, +}; + +/// +/// @brief defines the flags for valid and invalid values +/// +enum msdg_flags +{ + MSDG_VALID = 1, + MSDG_INVALID = 0, + MSDG_TRUE = 1, + MSDG_FALSE = 0, +}; + +/// +/// @brief defines the ranks +/// +enum msdg_ranks +{ + MSDG_1RANK = 0x0001, + MSDG_2RANK = 0x0002, + MSDG_4RANK = 0x0004, + MSDG_NO_RANK = 0x0000, +}; + +/// +/// @brief defines the value for initialization +/// +enum msdg_height +{ + MSDG_PLANAR = 0x0000, + MSDG_H2 = 0x0002, + MSDG_H4 = 0x0004, + MSDG_H8 = 0x0008, +}; + +/// +/// @brief defines variables for Enable/Disable +/// +enum msdg_enable +{ + MSDG_ENABLE = 0x0001, + MSDG_DISABLE = 0x0000, +}; + +/// /// @brief host_fw_command_struct structure setup /// @param[in] i_cmd_data_crc the command data CRC /// @param[out] o_cmd the command parameters to set @@ -59,71 +136,787 @@ void setup_cmd_params(const uint32_t i_cmd_data_crc, host_fw_command_struct& o_c /// @param[out] o_param /// @return FAPI2_RC_SUCCESS iff okay /// -template < fapi2::TargetType T > -fapi2::ReturnCode setup_phy_params(const fapi2::Target<T>& i_target, - user_input_msdg& o_params) +fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + user_input_msdg& o_param ); + +/// +/// @class phy_params_t +/// @brief Structure of variables +/// +struct phy_params_t { - // TODO: exp_mss_draminit VPO prep: Replace hardcode with attr derived data - o_params.DimmType = 0; - o_params.CsPresent = 0x1; - o_params.DramDataWidth = 8; - o_params.Height3DS = 0; - o_params.ActiveDBYTE = 0; - o_params.ActiveNibble = 0; - o_params.AddrMirror = 0; - o_params.ColumnAddrWidth = 10; - o_params.RowAddrWidth = 16; - o_params.SpdCLSupported = 0x002BFFFC; - o_params.SpdtAAmin = 12500; - o_params.Rank4Mode = 0; - o_params.DDPCompatible = 0; - o_params.TSV8HSupport = 0; - o_params.MRAMSupport = 0; - o_params.NumPStates = 1; - o_params.Frequency[0] = 1600; - - // PHY parameters are fabricated and not relevant for emulation - o_params.PhyOdtImpedance[0] = 0; - o_params.PhyDrvImpedancePU[0] = 240; - o_params.PhySlewRate[0] = 0; - o_params.ATxImpedance = 120; - o_params.ATxSlewRate = 0; - o_params.CKTxImpedance = 120; - o_params.CKTxSlewRate = 0; - o_params.AlertOdtImpedance = 0; - o_params.DramRttNomR0[0] = 0; - o_params.DramRttNomR1[0] = 0; - o_params.DramRttNomR2[0] = 0; - o_params.DramRttNomR3[0] = 0; - o_params.DramRttWrR0[0] = 0; - o_params.DramRttWrR1[0] = 0; - o_params.DramRttWrR2[0] = 0; - o_params.DramRttWrR3[0] = 0; - o_params.DramRttParkR0[0] = 0; - o_params.DramRttParkR1[0] = 0; - o_params.DramRttParkR2[0] = 0; - o_params.DramRttParkR3[0] = 0; - o_params.DramDic[0] = 48; - o_params.DramWritePreamble[0] = 0; - o_params.DramReadPreamble[0] = 0; - o_params.PhyEqualization = 0; - o_params.InitVrefDQ[0] = 0x9; - o_params.InitPhyVref[0] = 0x60; - o_params.OdtWrMapCs[0] = 0; - o_params.OdtRdMapCs[0] = 0; - o_params.Geardown[0] = 0; - o_params.CALatencyAdder[0] = 0; - o_params.BistCALMode[0] = 0; - o_params.BistCAParityLatency[0] = 0; - o_params.RcdDic[0] = 0; - o_params.RcdVoltageCtrl[0] = 0; - o_params.RcdIBTCtrl = 0; - o_params.RcdDBDic = 0; - o_params.RcdSlewRate = 0; - o_params.EmulationSupport = 1; - - return fapi2::FAPI2_RC_SUCCESS; -} + /// + /// Declare variables to be used + /// + uint8_t iv_dimm_type[MAX_DIMM_PER_PORT]; + uint8_t iv_chip_select; + uint8_t iv_dram_data_width[MAX_DIMM_PER_PORT]; + uint8_t iv_height_3DS; + uint16_t iv_dbyte_macro; + uint32_t iv_nibble; + uint8_t iv_addr_mirror[MAX_DIMM_PER_PORT]; + uint8_t iv_column_width[MAX_DIMM_PER_PORT]; + uint8_t iv_row_width[MAX_DIMM_PER_PORT]; + uint32_t iv_spdcl_support; + uint8_t iv_taa_min; + uint8_t iv_rank4_mode; + uint8_t iv_ddp_compatible; + uint8_t iv_tsv8h; + uint8_t iv_mram_support; + uint8_t iv_num_pstate; + uint64_t iv_frequency; + uint8_t iv_odt_impedance; + uint8_t iv_drv_impedance_pu[MSDG_MAX_PSTATE]; + uint8_t iv_drv_impedance_pd[MSDG_MAX_PSTATE]; + uint8_t iv_slew_rate[MSDG_MAX_PSTATE]; + uint8_t iv_atx_impedance; + uint8_t iv_atx_slew_rate; + uint8_t iv_ck_tx_impedance; + uint8_t iv_ck_tx_slew_rate; + uint8_t iv_alert_odt_impedance; + uint8_t iv_dram_rtt_nom[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_dram_rtt_wr[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_dram_rtt_park[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_dram_dic[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_dram_preamble; + uint8_t iv_phy_equalization; + uint8_t iv_init_vref_dq; + uint16_t iv_init_phy_vref; + uint8_t iv_odt_wr_map_cs; + uint8_t iv_odt_rd_map_cs; + uint8_t iv_geardown_mode[MAX_DIMM_PER_PORT]; + uint8_t iv_ca_latency_adder[MAX_DIMM_PER_PORT]; + uint8_t iv_bist_cal_mode[MAX_DIMM_PER_PORT]; + uint8_t iv_bist_ca_parity_latency[MAX_DIMM_PER_PORT]; + uint8_t iv_rcd_dic; + uint8_t iv_rcd_voltage_ctrl; + uint8_t iv_f0rc7x[MAX_DIMM_PER_PORT]; + uint8_t iv_f1rc00[MAX_DIMM_PER_PORT]; + uint16_t iv_rcd_slew_rate; + uint8_t iv_firmware_mode; +}; + +/// +/// @class phy_params +/// +/// @note This class provides storage and methods for setting +/// up the parameters for user_input_msdg structure +/// +class phy_params +{ + private: + phy_params_t iv_params; + + public: + /// + /// @brief Delete default constructor + /// + phy_params() = delete; + + /// + /// @brief Constructor to fetch attributes + /// + /// @brief fetch the attributes and initialize it to the params + /// @param[in] i_port the fapi2 target + /// @param[in,out] o_rc the fapi2 output + /// + phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, fapi2::ReturnCode o_rc) + { + // Fetch attributes and populate the member variables + FAPI_TRY(mss::attr::get_dimm_type(i_port, iv_params.iv_dimm_type)); + FAPI_TRY(mss::attr::get_exp_chip_select(i_port, iv_params.iv_chip_select)); + FAPI_TRY(mss::attr::get_dram_width(i_port, iv_params.iv_dram_data_width)); + FAPI_TRY(mss::attr::get_3ds_height(i_port, iv_params.iv_height_3DS)); + FAPI_TRY(mss::attr::get_byte_enables(i_port, iv_params.iv_dbyte_macro)); + FAPI_TRY(mss::attr::get_nibble_enables(i_port, iv_params.iv_nibble)); + FAPI_TRY(mss::attr::get_exp_dram_address_mirroring(i_port, iv_params.iv_addr_mirror)); + FAPI_TRY(mss::attr::get_dram_column_bits(i_port, iv_params.iv_column_width)); + FAPI_TRY(mss::attr::get_dram_row_bits(i_port, iv_params.iv_row_width)); + FAPI_TRY(mss::attr::get_exp_spd_cl(i_port, iv_params.iv_spdcl_support)); + FAPI_TRY(mss::attr::get_taa_min(i_port, iv_params.iv_taa_min)); + FAPI_TRY(mss::attr::get_rank4_mode(i_port, iv_params.iv_rank4_mode)); + FAPI_TRY(mss::attr::get_ddp_compatibility(i_port, iv_params.iv_ddp_compatible)); + FAPI_TRY(mss::attr::get_tsv8h_support(i_port, iv_params.iv_tsv8h)); + FAPI_TRY(mss::attr::get_mram_support(i_port, iv_params.iv_mram_support)); + FAPI_TRY(mss::attr::get_pstates(i_port, iv_params.iv_num_pstate)); + FAPI_TRY(mss::attr::get_freq(i_port, iv_params.iv_frequency)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_cntl(i_port, iv_params.iv_odt_impedance)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_dq_dqs_pull_up(i_port, iv_params.iv_drv_impedance_pu)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_dq_dqs_pull_down(i_port, iv_params.iv_drv_impedance_pd)); + FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_dq_dqs(i_port, iv_params.iv_slew_rate)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_cmd_addr(i_port, iv_params.iv_atx_impedance)); + FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_cmd_addr(i_port, iv_params.iv_atx_slew_rate)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_clk(i_port, iv_params.iv_ck_tx_impedance)); + FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_clk(i_port, iv_params.iv_ck_tx_slew_rate)); + FAPI_TRY(mss::attr::get_si_mc_rcv_imp_alert_n(i_port, iv_params.iv_alert_odt_impedance)); + FAPI_TRY(mss::attr::get_si_dram_rtt_nom(i_port, iv_params.iv_dram_rtt_nom)); + FAPI_TRY(mss::attr::get_si_dram_rtt_wr(i_port, iv_params.iv_dram_rtt_wr)); + FAPI_TRY(mss::attr::get_si_dram_rtt_park(i_port, iv_params.iv_dram_rtt_park)); + FAPI_TRY(mss::attr::get_si_dram_drv_imp_dq_dqs(i_port, iv_params.iv_dram_dic)); + FAPI_TRY(mss::attr::get_si_dram_preamble(i_port, iv_params.iv_dram_preamble)); + FAPI_TRY(mss::attr::get_exp_phy_equalization(i_port, iv_params.iv_phy_equalization)); + FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_port, iv_params.iv_init_vref_dq)); + FAPI_TRY(mss::attr::get_exp_init_phy_vref(i_port, iv_params.iv_init_phy_vref)); + FAPI_TRY(mss::attr::get_exp_odt_map_cs_wr(i_port, iv_params.iv_odt_wr_map_cs)); + FAPI_TRY(mss::attr::get_exp_odt_map_cs_rd(i_port, iv_params.iv_odt_rd_map_cs)); + FAPI_TRY(mss::attr::get_geardown_mode(i_port, iv_params.iv_geardown_mode)); + FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc0f(i_port, iv_params.iv_ca_latency_adder)); + FAPI_TRY(mss::attr::get_cs_cmd_latency(i_port, iv_params.iv_bist_cal_mode)); + FAPI_TRY(mss::attr::get_ca_parity_latency(i_port, iv_params.iv_bist_ca_parity_latency)); + FAPI_TRY(mss::attr::get_exp_rcd_dic(i_port, iv_params.iv_rcd_dic)); + FAPI_TRY(mss::attr::get_exp_rcd_voltage_ctrl(i_port, iv_params.iv_rcd_voltage_ctrl)); + FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc7x(i_port, iv_params.iv_f0rc7x)); + FAPI_TRY(mss::attr::get_dimm_ddr4_f1rc00(i_port, iv_params.iv_f1rc00)); + FAPI_TRY(mss::attr::get_exp_rcd_slew_rate(i_port, iv_params.iv_rcd_slew_rate)); + FAPI_TRY(mss::attr::get_exp_firmware_emulation_mode(i_port, iv_params.iv_firmware_mode)); + + fapi_try_exit: + o_rc = fapi2::current_err; + } + + /// + /// @brief Constructor for UTs + /// + /// @brief Set params as per the value initialized for the UT + /// @param[in] i_phy_params - data struct for UT + /// + phy_params(const phy_params_t& i_phy_params): iv_params(i_phy_params) {} + + /// + /// @brief Destructor + /// + ~phy_params() = default; + + /// + /// @brief user_input_msdg structure setup for parameter DimmType + /// @param[in] i_port the fapi2 target + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS iff okay + /// + fapi2::ReturnCode setup_DimmType(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, + user_input_msdg& io_phy_params) const + { + switch (iv_params.iv_dimm_type[0]) + { + case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM: + io_phy_params.DimmType = MSDG_RDIMM; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM: + io_phy_params.DimmType = MSDG_UDIMM; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM: + io_phy_params.DimmType = MSDG_LRDIMM; + break; + + default: + const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_port); + FAPI_ASSERT(false, + fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_DIMM_TYPE(). + set_OCMB_TARGET(l_ocmb). + set_PORT(i_port). + set_TYPE(iv_params.iv_dimm_type[0]), + "%s DIMM0 is not a supported DIMM type (%d)", + mss::c_str(i_port), iv_params.iv_dimm_type[0]); + break; + } + + return fapi2::FAPI2_RC_SUCCESS; + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief user_input_msdg structure setup for parameter CsPresent + /// @param[in] i_port the fapi2 target + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS iff okay + /// + fapi2::ReturnCode setup_CsPresent(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, + user_input_msdg& io_phy_params) const + { + io_phy_params.CsPresent = iv_params.iv_chip_select; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief user_input_msdg structure setup for parameter DramDataWidth + /// @param[in] i_port the fapi2 target + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS iff okay + /// + fapi2::ReturnCode setup_DramDataWidth(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, + user_input_msdg& io_phy_params) const + { + switch (iv_params.iv_dram_data_width[0]) + { + case fapi2::ENUM_ATTR_MEM_EFF_DRAM_WIDTH_X4: + io_phy_params.DramDataWidth = MSDG_X4; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_DRAM_WIDTH_X8: + io_phy_params.DramDataWidth = MSDG_X8; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_DRAM_WIDTH_X16: + io_phy_params.DramDataWidth = MSDG_X16; + break; + + default: + const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_port); + FAPI_ASSERT(false, + fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_DRAM_WIDTH(). + set_OCMB_TARGET(l_ocmb). + set_PORT(i_port). + set_DATA_WIDTH(iv_params.iv_dram_data_width[0]), + "%s DRAM Data Width of DIMM0 is not a supported (%d)", + mss::c_str(i_port), iv_params.iv_dram_data_width[0]); + break; + } + + return fapi2::FAPI2_RC_SUCCESS; + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief user_input_msdg structure setup for parameter Height3DS + /// @param[in] i_port the fapi2 target + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS iff okay + /// + fapi2::ReturnCode setup_Height3DS(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, + user_input_msdg& io_phy_params) const + { + switch (iv_params.iv_height_3DS) + { + case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_PLANAR: + io_phy_params.Height3DS = MSDG_PLANAR; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_H2: + io_phy_params.Height3DS = MSDG_H2; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_H4: + io_phy_params.Height3DS = MSDG_H4; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_H8: + io_phy_params.Height3DS = MSDG_H8; + break; + + default: + const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_port); + FAPI_ASSERT(false, + fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_3DS_HEIGHT(). + set_OCMB_TARGET(l_ocmb). + set_PORT(i_port). + set_HEIGHT(iv_params.iv_height_3DS), + "%s 3DS Height is not a supported (%d)", + mss::c_str(i_port), iv_params.iv_height_3DS); + break; + } + + return fapi2::FAPI2_RC_SUCCESS; + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Get the value for parameter ActiveDBYTE + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_ActiveDBYTE(user_input_msdg& io_phy_params) const + { + io_phy_params.ActiveDBYTE = iv_params.iv_dbyte_macro; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter ActiveNibble + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_ActiveNibble(user_input_msdg& io_phy_params) const + { + io_phy_params.ActiveNibble = iv_params.iv_nibble; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter AddrMirror + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_AddrMirror(user_input_msdg& io_phy_params) const + { + io_phy_params.AddrMirror = iv_params.iv_addr_mirror[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter ColumnAddrWidth + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_ColumnAddrWidth(user_input_msdg& io_phy_params) const + { + io_phy_params.ColumnAddrWidth = iv_params.iv_column_width[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RowAddrWidth + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RowAddrWidth(user_input_msdg& io_phy_params) const + { + io_phy_params.RowAddrWidth = iv_params.iv_row_width[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter SpdCLSupported + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_SpdCLSupported(user_input_msdg& io_phy_params) const + { + io_phy_params.SpdCLSupported = iv_params.iv_spdcl_support; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter SpdtAAmin + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_SpdtAAmin(user_input_msdg& io_phy_params) const + { + io_phy_params.SpdtAAmin = iv_params.iv_taa_min; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter Rank4Mode + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_Rank4Mode(user_input_msdg& io_phy_params) const + { + io_phy_params.Rank4Mode = iv_params.iv_rank4_mode; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter DDPCompatible + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_DDPCompatible(user_input_msdg& io_phy_params) const + { + io_phy_params.DDPCompatible = iv_params.iv_ddp_compatible; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter TSV8HSupport + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_TSV8HSupport(user_input_msdg& io_phy_params) const + { + io_phy_params.TSV8HSupport = iv_params.iv_tsv8h; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter MRAMSupport + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_MRAMSupport(user_input_msdg& io_phy_params) const + { + io_phy_params.MRAMSupport = iv_params.iv_mram_support; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter NumPStates + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_NumPStates(user_input_msdg& io_phy_params) const + { + io_phy_params.NumPStates = iv_params.iv_num_pstate; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter Frequency + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_Frequency(user_input_msdg& io_phy_params) const + { + io_phy_params.Frequency[0] = static_cast<uint16_t>(iv_params.iv_frequency); + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter PhyOdtImpedance + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_PhyOdtImpedance(user_input_msdg& io_phy_params) const + { + io_phy_params.PhyOdtImpedance[0] = iv_params.iv_odt_impedance; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter PhyDrvImpedancePU + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_PhyDrvImpedancePU(user_input_msdg& io_phy_params) const + { + io_phy_params.PhyDrvImpedancePU[0] = iv_params.iv_drv_impedance_pu[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter PhyDrvImpedancePD + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_PhyDrvImpedancePD(user_input_msdg& io_phy_params) const + { + io_phy_params.PhyDrvImpedancePD[0] = iv_params.iv_drv_impedance_pd[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter PhySlewRate + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_PhySlewRate(user_input_msdg& io_phy_params) const + { + io_phy_params.PhySlewRate[0] = iv_params.iv_slew_rate[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter ATxImpedance + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_ATxImpedance(user_input_msdg& io_phy_params) const + { + io_phy_params.ATxImpedance = iv_params.iv_atx_impedance; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter ATxSlewRate + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_ATxSlewRate(user_input_msdg& io_phy_params) const + { + io_phy_params.ATxSlewRate = iv_params.iv_atx_slew_rate; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter CKTxImpedance + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_CKTxImpedance(user_input_msdg& io_phy_params) const + { + io_phy_params.CKTxImpedance = iv_params.iv_ck_tx_impedance; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter CKTxSlewRate + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_CKTxSlewRate(user_input_msdg& io_phy_params) const + { + io_phy_params.CKTxSlewRate = iv_params.iv_ck_tx_slew_rate; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter AlertOdtImpedance + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_AlertOdtImpedance(user_input_msdg& io_phy_params) const + { + io_phy_params.AlertOdtImpedance = iv_params.iv_alert_odt_impedance; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RttNom + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RttNom(user_input_msdg& io_phy_params) const + { + io_phy_params.DramRttNomR0[0] = iv_params.iv_dram_rtt_nom[0][0]; + io_phy_params.DramRttNomR1[0] = iv_params.iv_dram_rtt_nom[0][1]; + io_phy_params.DramRttNomR2[0] = iv_params.iv_dram_rtt_nom[0][2]; + io_phy_params.DramRttNomR3[0] = iv_params.iv_dram_rtt_nom[0][3]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RttWr + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RttWr(user_input_msdg& io_phy_params) const + { + io_phy_params.DramRttWrR0[0] = iv_params.iv_dram_rtt_wr[0][0]; + io_phy_params.DramRttWrR1[0] = iv_params.iv_dram_rtt_wr[0][1]; + io_phy_params.DramRttWrR2[0] = iv_params.iv_dram_rtt_wr[0][2]; + io_phy_params.DramRttWrR3[0] = iv_params.iv_dram_rtt_wr[0][3]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RttPark + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RttPark(user_input_msdg& io_phy_params) const + { + io_phy_params.DramRttParkR0[0] = iv_params.iv_dram_rtt_park[0][0]; + io_phy_params.DramRttParkR1[0] = iv_params.iv_dram_rtt_park[0][1]; + io_phy_params.DramRttParkR2[0] = iv_params.iv_dram_rtt_park[0][2]; + io_phy_params.DramRttParkR3[0] = iv_params.iv_dram_rtt_park[0][3]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter DramDic + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_DramDic(user_input_msdg& io_phy_params) const + { + io_phy_params.DramDic[0] = iv_params.iv_dram_dic[0][0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter DramWritePreamble + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_DramWritePreamble(user_input_msdg& io_phy_params) const + { + fapi2::buffer<uint8_t> l_dram_preamble_buf(iv_params.iv_dram_preamble); + io_phy_params.DramWritePreamble[0] = + l_dram_preamble_buf.getBit<fapi2::ENUM_ATTR_MEM_SI_DRAM_PREAMBLE_WRITE_PREAMBLE_BIT>(); + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter DramReadPreamble + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_DramReadPreamble(user_input_msdg& io_phy_params) const + { + fapi2::buffer<uint8_t> l_dram_preamble_buf(iv_params.iv_dram_preamble); + io_phy_params.DramReadPreamble[0] = + l_dram_preamble_buf.getBit<fapi2::ENUM_ATTR_MEM_SI_DRAM_PREAMBLE_READ_PREAMBLE_BIT>(); + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter PhyEqualization + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_PhyEqualization(user_input_msdg& io_phy_params) const + { + io_phy_params.PhyEqualization = iv_params.iv_phy_equalization; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter InitVrefDQ + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_InitVrefDQ(user_input_msdg& io_phy_params) const + { + io_phy_params.InitVrefDQ[0] = iv_params.iv_init_vref_dq; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter InitPhyVref + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_InitPhyVref(user_input_msdg& io_phy_params) const + { + // Attr Vref = percentage of VDDQ, Receiver Vref = VDDQ*PhyVref[6:0]/128 + // conversion is attr_value * 128 / 100 + io_phy_params.InitPhyVref[0] = iv_params.iv_init_phy_vref * 128 / 100; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter OdtWrMapCs + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_OdtWrMapCs(user_input_msdg& io_phy_params) const + { + io_phy_params.OdtWrMapCs[0] = iv_params.iv_odt_wr_map_cs; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter OdtRdMapCs + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_OdtRdMapCs(user_input_msdg& io_phy_params) const + { + io_phy_params.OdtRdMapCs[0] = iv_params.iv_odt_rd_map_cs; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter Geardown + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_Geardown(user_input_msdg& io_phy_params) const + { + io_phy_params.Geardown[0] = iv_params.iv_geardown_mode[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter CALatencyAdder + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_CALatencyAdder(user_input_msdg& io_phy_params) const + { + io_phy_params.CALatencyAdder[0] = iv_params.iv_ca_latency_adder[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter BistCALMode + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_BistCALMode(user_input_msdg& io_phy_params) const + { + io_phy_params.BistCALMode[0] = iv_params.iv_bist_cal_mode[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter BistCAParityLatency + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_BistCAParityLatency(user_input_msdg& io_phy_params) const + { + io_phy_params.BistCAParityLatency[0] = iv_params.iv_bist_ca_parity_latency[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RcdDic + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RcdDic(user_input_msdg& io_phy_params) const + { + io_phy_params.RcdDic[0] = iv_params.iv_rcd_dic; + + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RcdVoltageCtrl + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RcdVoltageCtrl(user_input_msdg& io_phy_params) const + { + io_phy_params.RcdVoltageCtrl[0] = iv_params.iv_rcd_voltage_ctrl; + + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RcdIBTCtrl + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RcdIBTCtrl(user_input_msdg& io_phy_params) const + { + io_phy_params.RcdIBTCtrl = iv_params.iv_f0rc7x[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RcdDBDic + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RcdDBDic(user_input_msdg& io_phy_params) const + { + io_phy_params.RcdDBDic = iv_params.iv_f1rc00[0]; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter RcdSlewRate + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_RcdSlewRate(user_input_msdg& io_phy_params) const + { + io_phy_params.RcdSlewRate = iv_params.iv_rcd_slew_rate; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter EmulationSupport + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_EmulationSupport(user_input_msdg& io_phy_params) const + { + io_phy_params.EmulationSupport = iv_params.iv_firmware_mode; + return fapi2::FAPI2_RC_SUCCESS; + } +}; namespace check { diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index ab6d347d7..7b394b7aa 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -49,6 +49,15 @@ namespace exp constexpr uint32_t OCMB_ADDR_SHIFT = 3; /// +/// @brief common explorer sizes +/// +enum sizes +{ + MAX_DIMM_PER_PORT = 2, + MAX_RANK_PER_DIMM = 4, +}; + +/// /// @brief explorer ffdc codes /// enum ffdc_codes diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml index 2c7407962..927bdcf83 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml @@ -120,4 +120,153 @@ <mssAccessorName>mvpd_fwms</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Enable Special mode for Emulation Support + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>NORMAL = 0, EMULATION = 1</enum> + <writeable/> + <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_CHIP_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Indicate presence of DRAM at each Chip Select for PHY + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>exp_chip_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_PHY_EQUALIZATION</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Phy Equalization mode enable + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <mssAccessorName>exp_phy_equalization</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_INIT_VREF_DQ</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Initial VrefDQ setting before training + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>exp_init_vref_dq</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_INIT_PHY_VREF</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Initial DQ Vref setting of PHY before training + </description> + <valueType>uint16</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>exp_init_phy_vref</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_ODT_MAP_CS_WR</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Desired ODT Value to write to the ranks + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>exp_odt_map_cs_wr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_ODT_MAP_CS_RD</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Desired ODT Value when reading from the ranks + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>exp_odt_map_cs_rd</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_RCD_DIC</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05 + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>exp_rcd_dic</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_RCD_VOLTAGE_CTRL</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>exp_rcd_voltage_ctrl</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Ranks that have address mirroring. + This data is derived from SPD or VPD. + Note: This is a bit-wise map and muliple ranks can be mirrored. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <array>2</array> + <writeable/> + <mssAccessorName>exp_dram_address_mirroring</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_SPD_CL</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Cas Latency Supported by DRAM + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <mssAccessorName>exp_spd_cl</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_RCD_SLEW_RATE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05 + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssAccessorName>exp_rcd_slew_rate</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml index 2163e8c57..278d3790d 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml @@ -25,6 +25,51 @@ <hwpErrors> <hwpError> + <rc>RC_MSS_EXP_DRAMINIT_UNSUPPORTED_DIMM_TYPE</rc> + <description>Unsupported DIMM type encountered in draminit_training procedure</description> + <ffdc>OCMB_TARGET</ffdc> + <ffdc>PORT</ffdc> + <ffdc>TYPE</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_DRAMINIT_UNSUPPORTED_DRAM_WIDTH</rc> + <description>Unsupported DRAM width encountered in draminit_training procedure</description> + <ffdc>OCMB_TARGET</ffdc> + <ffdc>PORT</ffdc> + <ffdc>DATA_WIDTH</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_DRAMINIT_UNSUPPORTED_3DS_HEIGHT</rc> + <description>Unsupported 3DS height encountered in draminit_training procedure</description> + <ffdc>OCMB_TARGET</ffdc> + <ffdc>PORT</ffdc> + <ffdc>HEIGHT</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> <rc>RC_MSS_EXP_ENTERPRISE_SETUP_ERROR</rc> <description>The enterprise mode bit is in the incorrect state</description> <ffdc>EXPECTED</ffdc> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index ff92b3fca..0a3c2e2b4 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1599,8 +1599,8 @@ creator: mss_eff_cnfg consumer: various firmware notes: none - </description> - <initToZero></initToZero> + </description> + <initToZero></initToZero> <valueType>uint8</valueType> <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> <writeable/> @@ -3350,7 +3350,7 @@ <valueType>int8</valueType> <platInit/> <overrideOnly/> - <initToZero/> + <initToZero></initToZero> <writeable/> <mssAccessorName>wr_vref_offset</mssAccessorName> </attribute> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_override_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_override_attributes.xml index 4269fa2aa..43e8fd112 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_override_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_override_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -166,7 +166,7 @@ fapi2::getSPD() instead of the actual SPD contents. </description> <valueType>uint8</valueType> - <array>512</array> + <array>4096</array> <platInit/> <overrideOnly/> </attribute> diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index 96024c17e..d97816d47 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -101,6 +101,816 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel +/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none +/// +inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel +/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none +/// +inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from +/// 00 to 04. No need to calculate; User can override with desired experimental value. +/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0F, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0F: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from +/// 00 to 04. No need to calculate; User can override with desired experimental value. +/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0F, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0F: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CS_CMD_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CS_CMD_LATENCY, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CS_CMD_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CS_CMD_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CS_CMD_LATENCY, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CS_CMD_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CA_PARITY_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CA_PARITY_LATENCY, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CA_PARITY_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_CA_PARITY_LATENCY getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: +/// none +/// +inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_CA_PARITY_LATENCY, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_CA_PARITY_LATENCY: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC02 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. +/// No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC02, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC02: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC02 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. +/// No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC02, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC02: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC03 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC03, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC03: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC03 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC03, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC03: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC04 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value +/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC04, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC04: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC04 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value +/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC04, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC04: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC05 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate +/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble +/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC05, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC05: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC05 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate +/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble +/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC05, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC05: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0B getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User +/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0B, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0B: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC0B getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User +/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init +/// firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC0B, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC0B: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC1X getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 +/// to 3F.No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC1X, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC1X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC1X getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 +/// to 3F.No need to calculate; User can override with desired experimental value. creator: +/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC1X, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC1X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC7X getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need +/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg +/// consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC7X, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC7X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F0RC7X getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need +/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg +/// consumer: mss_dram_init firmware notes: none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F0RC7X, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F0RC7X: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F1RC00 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value +/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired +/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: +/// none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC00, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC00: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_DDR4_F1RC00 getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value +/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired +/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: +/// none +/// +inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) +{ + uint8_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC00, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC00: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory +/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: +/// none +/// +inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_PSTATES getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Number of p-states used Always set NumPStates to 1 for Explorer. +/// +inline fapi2::ReturnCode get_pstates(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_PSTATES, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_PSTATES: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_BYTE_ENABLES getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint16_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Enable/Disable DBYTE macro (clock gating and IO tri-state) 10-bit bitmap Right aligned +/// +inline fapi2::ReturnCode get_byte_enables(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint16_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_BYTE_ENABLES, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_BYTE_ENABLES: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_NIBBLE_ENABLES getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Account/Ignore training/dfi_bist result on the selected nibble. 20-bit bitmap Right +/// aligned +/// +inline fapi2::ReturnCode get_nibble_enables(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint32_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_NIBBLE_ENABLES, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_NIBBLE_ENABLES: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_TAA_MIN getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Timing value used to calculate CAS Latency +/// +inline fapi2::ReturnCode get_taa_min(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_TAA_MIN, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_TAA_MIN: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_RANK_FOUR_MODE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note DIMM Rank 4 mode enable +/// +inline fapi2::ReturnCode get_rank4_mode(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_RANK_FOUR_MODE, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_RANK_FOUR_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_REORDER_QUEUE_SETTING getter @@ -489,7 +1299,7 @@ fapi_try_exit: /// @note ARRAY[DIMM] Column Address Bits. Decoded SPD Byte 5 (bits 2~0). Actual number of /// DRAM columns is 2^N, where N is the number of column address bits /// -inline fapi2::ReturnCode get_dram_columns_bits(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode get_dram_column_bits(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); @@ -513,7 +1323,7 @@ fapi_try_exit: /// @note ARRAY[DIMM] Column Address Bits. Decoded SPD Byte 5 (bits 2~0). Actual number of /// DRAM columns is 2^N, where N is the number of column address bits /// -inline fapi2::ReturnCode get_dram_columns_bits(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, +inline fapi2::ReturnCode get_dram_column_bits(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) { uint8_t l_value[2] = {}; @@ -1666,6 +2476,89 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_EFF_MRAM_SUPPORT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Supports MRAM or not +/// +inline fapi2::ReturnCode get_mram_support(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_MRAM_SUPPORT, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_MRAM_SUPPORT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_EFF_3DS_HEIGHT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM] Primary SDRAM Package Type. Decodes Byte 6. This byte defines the primary +/// set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = +/// 3DS +/// +inline fapi2::ReturnCode get_3ds_height(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_3DS_HEIGHT, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_3DS_HEIGHT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_EFF_DDP_COMPATIBLE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note DDP Compatibility +/// +inline fapi2::ReturnCode get_ddp_compatibility(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DDP_COMPATIBLE, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_DDP_COMPATIBLE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_EFF_TSV8H_SUPPORT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note TSVH8 Support +/// +inline fapi2::ReturnCode get_tsv8h_support(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_TSV8H_SUPPORT, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_EFF_TSV8H_SUPPORT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_EFF_VOLT_VDDR getter diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml index 9b5d3a271..d10983bdb 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml @@ -95,4 +95,306 @@ <array>72</array> </attribute> + <attribute> + <id>ATTR_MEM_GEARDOWN_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Gear Down Mode. + This is for DDR4 MRS3. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>HALF =0, QUARTER=1</enum> + <writeable/> + <array>2</array> + <mssAccessorName>geardown_mode</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0F</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0f</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_CS_CMD_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + CS to CMD/ADDR Latency. + This is for DDR4 MRS4. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>cs_cmd_latency</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_CA_PARITY_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + C/A Parity Latency Mode. This is for DDR4 MRS5. + Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>ca_parity_latency</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC02</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC02: Timing and IBT Control Word; Default value - 0x00. + Values Range from 0-8. No need to calculate; + User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc02</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC03</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC03 - CA and CS Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc03</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC04</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc04</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC05</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + F0RC05 - Clock Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc05</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0B</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0b</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC1X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc1x</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC7X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc7x</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC00</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc00</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_VREF_DQ_TRAIN_VALUE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + vrefdq_train value. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array> 2 4</array> + <mssAccessorName>vref_dq_train_value</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_VREF_DQ_TRAIN_RANGE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + vrefdq_train range. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>RANGE1 = 0, RANGE2 = 1</enum> + <writeable/> + <array> 2 4</array> + <mssAccessorName>vref_dq_train_range</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_PSTATES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Number of p-states used + Always set NumPStates to 1 for Explorer. + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>pstates</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_BYTE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Enable/Disable DBYTE macro (clock gating and IO tri-state) + 10-bit bitmap + Right aligned + </description> + <valueType>uint16</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>byte_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_NIBBLE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Account/Ignore training/dfi_bist result on the selected nibble. + 20-bit bitmap + Right aligned + </description> + <valueType>uint32</valueType> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>nibble_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_TAA_MIN</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Timing value used to calculate CAS Latency + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nck</mssUnits> + <mssAccessorName>taa_min</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_RANK_FOUR_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DIMM Rank 4 mode enable + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <initToZero></initToZero> + <writeable/> + <mssAccessorName>rank4_mode</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index c94dc98fe..b34019c60 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -172,7 +172,7 @@ <valueType>uint8</valueType> <writeable/> <array>2</array> - <mssAccessorName>dram_columns_bits</mssAccessorName> + <mssAccessorName>dram_column_bits</mssAccessorName> </attribute> <attribute> @@ -787,4 +787,60 @@ <mssAccessorName>volt_vpp</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_EFF_MRAM_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Supports MRAM or not + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>NORMAL = 0, EVERSPIN = 1</enum> + <writeable/> + <mssAccessorName>mram_support</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_3DS_HEIGHT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Primary SDRAM Package Type. + Decodes Byte 6. + This byte defines the primary set of SDRAMs. + Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> + <writeable/> + <mssAccessorName>3ds_height</mssAccessorName> + </attribute> + +<attribute> + <id>ATTR_MEM_EFF_DDP_COMPATIBLE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DDP Compatibility + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <mssAccessorName>ddp_compatibility</mssAccessorName> + </attribute> + +<attribute> + <id>ATTR_MEM_EFF_TSV8H_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + TSVH8 Support + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <mssAccessorName>tsv8h_support</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index df5194424..008a90974 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -122,6 +122,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> + <enum>READ_PREAMBLE_BIT = 3, WRITE_PREAMBLE_BIT = 7</enum> <mssUnits>nCK</mssUnits> <mssAccessorName>si_dram_preamble</mssAccessorName> </attribute> |
