diff options
17 files changed, 304 insertions, 157 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C index 0568b7470..acb514894 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C @@ -27,10 +27,10 @@ /// @brief Wrapper that initializes or resets the OCC complex. /// // *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP HWP Backup Owner : -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> // *HWP Team : PM -// *HWP Level : 2 +// *HWP Level : 3 // *HWP Consumed by : HS /// diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H index 5551c6dd0..2a97db868 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.H @@ -27,10 +27,10 @@ /// @brief Wrapper that initializes or resets the OCC complex. /// // *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP HWP Backup Owner : -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> // *HWP Team : PM -// *HWP Level : 2 +// *HWP Level : 3 // *HWP Consumed by : HS #ifndef _P9_PM_INIT_H diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C index 41e072919..837a50da0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,15 +26,16 @@ /// @file p9_pm_occ_gpe_init.C /// @brief Initialize or reset the targeted GPE0 and/or GPE1 /// -// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: HS +// *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS /// /// High-level procedure flow: -/// \verbatim +/// @verbatim /// /// Check for valid parameters /// if PM_RESET { @@ -45,25 +46,22 @@ /// clear interrupt vector prefix register /// } /// if PM_INIT { -/// operation performed by OC firmware. +/// operation performed by OCC firmware. /// Thus, noop /// } /// /// Procedure Prereq: /// - System clocks are running /// -/// \endverbatim +/// @endverbatim /// // ----------------------------------------------------------------------------- // Includes // ----------------------------------------------------------------------------- #include <p9_pm_occ_gpe_init.H> - -// ----------------------------------------------------------------------------- -// Constants -// ----------------------------------------------------------------------------- -const uint64_t OCC_GPE_HALT = 0x1; +#include <p9_ppe_defs.H> +#include <p9_ppe_utils.H> // ----------------------------------------------------------------------------- // Function prototypes @@ -92,7 +90,7 @@ fapi2::ReturnCode p9_pm_occ_gpe_init( const p9pm::PM_FLOW_MODE i_mode, const p9occgpe::GPE_ENGINES i_engine) { - FAPI_IMP("p9_pm_occ_gpe_init Enter"); + FAPI_IMP(">> p9_pm_occ_gpe_init"); // Initialization: perform order or dynamic operations to initialize // the GPEs using necessary Platform or Feature attributes. @@ -125,7 +123,7 @@ fapi2::ReturnCode p9_pm_occ_gpe_init( } fapi_try_exit: - FAPI_IMP("p9_pm_occ_gpe_init Exit"); + FAPI_IMP("<< p9_pm_occ_gpe_init"); return fapi2::current_err; } @@ -133,7 +131,7 @@ fapi2::ReturnCode pm_occ_gpe_reset( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const p9occgpe::GPE_ENGINES i_engine) { - FAPI_IMP("pm_occ_gpe_reset Enter"); + FAPI_IMP(">> pm_occ_gpe_reset"); fapi2::buffer<uint64_t> l_data64; uint64_t l_controlReg = 0; @@ -145,10 +143,22 @@ fapi2::ReturnCode pm_occ_gpe_reset( if (i_engine == p9occgpe::GPE0) { - l_controlReg = PU_GPE0_PPE_XIXCR; - l_statusReg = PU_GPE0_GPEXIXSR_SCOM; - l_instrAddrReg = PU_GPE0_PPE_XIDBGPRO; - l_intVecReg = PU_GPE0_GPEIVPR_SCOM; + l_controlReg = PU_GPE0_PPE_XIXCR; + l_statusReg = PU_GPE0_GPEXIXSR_SCOM; + l_instrAddrReg = PU_GPE0_PPE_XIDBGPRO; + l_intVecReg = PU_GPE0_GPEIVPR_SCOM; + + //Check if GPE0 is already halted + FAPI_TRY(fapi2::getScom(i_target, l_statusReg, l_data64), + "ERROR: Failed to get the OCC GPE0 status"); + + FAPI_ASSERT( (l_data64.getBit<0>() != 1), + fapi2::GPE0_IN_HALT_BEFORE_RESET() + .set_CHIP( i_target ) + .set_GPE0_STATUS( l_data64 ) + .set_GPE0_MODE( HALT ) + .set_GPE0_BASE_ADDRESS( GPE0_BASE_ADDRESS ), + "OCC GPE0 in Halt State Before Reset"); } else if (i_engine == p9occgpe::GPE1) { @@ -156,10 +166,23 @@ fapi2::ReturnCode pm_occ_gpe_reset( l_statusReg = PU_GPE1_GPEXIXSR_SCOM; l_instrAddrReg = PU_GPE1_PPE_XIDBGPRO; l_intVecReg = PU_GPE1_GPEIVPR_SCOM; + + //Check if GPE1 is already halted + FAPI_TRY(fapi2::getScom(i_target, l_statusReg, l_data64), + "ERROR: Failed to get the OCC GPE1 status"); + + FAPI_ASSERT( (l_data64.getBit<0>() != 1), + fapi2::GPE1_IN_HALT_BEFORE_RESET() + .set_CHIP( i_target ) + .set_GPE1_STATUS( l_data64 ) + .set_GPE1_MODE( HALT ) + .set_GPE1_BASE_ADDRESS( GPE1_BASE_ADDRESS ), + "OCC GPE1 in Halt State Before Reset"); } + // Halt the OCC GPE - l_data64.flush<0>().insertFromRight(OCC_GPE_HALT, 1, 3); + l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3); FAPI_TRY(putScom(i_target, l_controlReg, l_data64), "ERROR: Failed to halt the OCC GPE"); @@ -180,10 +203,24 @@ fapi2::ReturnCode pm_occ_gpe_reset( } while(--l_pollCount != 0); - FAPI_ASSERT((l_pollCount != 0), - fapi2::PM_OCC_GPE_RESET_TIMEOUT() - .set_CHIP(i_target), - "OCC GPE could not be halted during reset operation."); + if (i_engine == p9occgpe::GPE0) + { + FAPI_ASSERT((l_pollCount != 0), + fapi2::PM_OCC_GPE0_RESET_TIMEOUT() + .set_CHIP( i_target ) + .set_GPE0_MODE( HALT ) + .set_GPE0_BASE_ADDRESS( GPE0_BASE_ADDRESS ), + "OCC GPE0 could not be halted during reset operation."); + } + else if (i_engine == p9occgpe::GPE1) + { + FAPI_ASSERT((l_pollCount != 0), + fapi2::PM_OCC_GPE1_RESET_TIMEOUT() + .set_CHIP( i_target ) + .set_GPE1_MODE( HALT ) + .set_GPE1_BASE_ADDRESS( GPE1_BASE_ADDRESS ), + "OCC GPE1 could not be halted during reset operation."); + } //Clear status (Instruction Address) register l_data64.flush<0>(); @@ -195,5 +232,6 @@ fapi2::ReturnCode pm_occ_gpe_reset( "ERROR: Failed to clear interrupt vector prefix register"); fapi_try_exit: + FAPI_IMP("<< pm_occ_gpe_reset"); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.H index adf70cec0..230aa586d 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,12 +26,13 @@ /// @file p9_pm_occ_gpe_init.H /// @brief Initialize or reset the targeted GPE0 and/or GPE1 /// -/// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -/// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -/// *HWP Team: PM -/// *HWP Level: 2 -/// *HWP Consumed by: HS -/// +// *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS +// #ifndef _P9_PM_OCC_GPE_INIT_H #define _P9_PM_OCC_GPE_INIT_H @@ -42,6 +43,7 @@ #include <fapi2.H> #include <p9_pm.H> #include <p9_misc_scom_addresses.H> +#include <p9_hcd_common.H> //------------------------------------------------------------------------------ // Constant definitions @@ -56,9 +58,6 @@ enum GPE_ENGINES }; } -//------------------------------------------------------------------------------ -// Parameter structure definitions -//------------------------------------------------------------------------------ // function pointer typedef definition for HWP call support typedef fapi2::ReturnCode (*p9_pm_occ_gpe_init_FP_t) ( diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.mk index 4ab83505c..08aa8e67c 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_gpe_init.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -23,4 +23,6 @@ # # IBM_PROLOG_END_TAG PROCEDURE=p9_pm_occ_gpe_init +$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib) +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C index 6c1f43539..2ab615c97 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C @@ -26,30 +26,29 @@ /// @file p9_pm_pba_init.C /// @brief Initialize PBA registers for modes PM_INIT, PM_RESET /// - -/* - - RESET flow - Sets up PBA Mode register (in general) - Set the values of PBASLV 0 to allow the IPL phase accesses for - SGPE and PPC405 boot - Set the values of PBASLV 2 to allow the IPL phase accesses for - PGPE boot - upon boot of the OCC, OCC FW will re-establish - this slave for its use - INIT flow - Set the values of PBASLV 0 to allow Runtime phase access for - SGPE STOP (read accesses) - Set the values of PBASLV 1 to allow Runtime phase access for - SGPE 24x7 (read accesses). SGPE 24x7 thread will re-establish - this slave for write access as necessary - -*/ -/// -// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: HS +// *HWP HW Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS + +/// +/// @verbatim +/// RESET flow +/// Sets up PBA Mode register (in general) +/// Set the values of PBASLV 0 to allow the IPL phase accesses for +/// SGPE and PPC405 boot +/// Set the values of PBASLV 2 to allow the IPL phase accesses for +/// PGPE boot - upon boot of the OCC, OCC FW will re-establish +/// this slave for its use +/// INIT flow +/// Set the values of PBASLV 0 to allow Runtime phase access for +/// SGPE STOP (read accesses) +/// Set the values of PBASLV 1 to allow Runtime phase access for +/// SGPE 24x7 (read accesses). SGPE 24x7 thread will re-establish +/// this slave for write access as necessary +///@endverbatim // ---------------------------------------------------------------------- // Includes @@ -242,6 +241,7 @@ fapi2::ReturnCode pba_slave_reset( fapi2::ReturnCode pba_bc_stop( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + // ----------------------------------------------------------------------------- // Function definition // ----------------------------------------------------------------------------- @@ -497,7 +497,6 @@ fapi2::ReturnCode pba_slave_reset( } // Check if the slave is still actually busy. - // Slave %x still busy after reset,consider whether this should be polled. if ( l_data64 & 0x0000000000000001 << (63 - ( 8 + sl)) ) { const uint64_t& l_BUFFCONT = uint64_t(l_data64); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.H index efd914f19..cb365ca2b 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,23 +26,13 @@ /// @file: p9_pm_pba_init.H /// @brief: Initialize PBA registers for modes PM_INIT, PM_RESET /// -// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 1 -// *HWP Consumed by: HS -// +// *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS -/// -/// @verbatim -/// -/// high level flow: -/// if {i_mode == PM_INIT) -/// rc = pba_init_init(i_target); -/// else if (i_mode == PM_RESET) -/// rc = pba_init_reset(i_target); -/// @endverbatim -/// #ifndef _P9_PBAINIT_H_ #define _P9_PBAINIT_H_ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.C index 4f5f9f505..55ae05979 100755 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.C @@ -25,12 +25,12 @@ /// @file p9_pm_pss_init.C /// @brief Initializes P2S and HWC logic /// -// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> -// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: FSP:HS +// *HWP HW Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS // ----------------------------------------------------------------------------- // Includes @@ -73,7 +73,7 @@ fapi2::ReturnCode p9_pm_pss_init( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const p9pm::PM_FLOW_MODE i_mode) { - FAPI_IMP("p9_pm_pss_init Enter"); + FAPI_IMP(">> p9_pm_pss_init"); // Initialization: perform order or dynamic operations to initialize // the PMC using necessary Platform or Feature attributes. @@ -88,19 +88,18 @@ fapi2::ReturnCode p9_pm_pss_init( } fapi_try_exit: - FAPI_IMP("p9_pm_pss_init Exit"); + FAPI_IMP("<< p9_pm_pss_init"); return fapi2::current_err; } fapi2::ReturnCode pm_pss_init( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { - FAPI_IMP("pm_pss_init Enter"); + FAPI_IMP(">> pm_pss_init Enter"); fapi2::buffer<uint64_t> l_data64; - const uint32_t l_default_attr_proc_pss_init_nest_frequency = 2400; - const uint8_t l_default_apss_chip_select = 1; + const uint8_t l_default_apss_chip_select = 0; const uint8_t l_default_spipss_frame_size = 0x20; const uint8_t l_default_spipss_in_delay = 0; const uint8_t l_default_spipss_clock_polarity = 0; @@ -125,9 +124,9 @@ fapi2::ReturnCode pm_pss_init( const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sysTarget = i_target.getParent<fapi2::TARGET_TYPE_SYSTEM>(); - GETATTR_DEFAULT(fapi2::ATTR_FREQ_PB_MHZ, "ATTR_FREQ_PB_MHZ", l_sysTarget, - l_attr_proc_pss_init_nest_frequency, - l_default_attr_proc_pss_init_nest_frequency); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, l_sysTarget, + l_attr_proc_pss_init_nest_frequency), + "Error: Could not fetch the system Frequency") GETATTR_DEFAULT(fapi2::ATTR_PM_APSS_CHIP_SELECT, "ATTR_PM_APSS_CHIP_SELECT", @@ -281,6 +280,7 @@ fapi2::ReturnCode pm_pss_init( "Error: Failed to set 100ns clear SPI PSS P2S WDATA"); fapi_try_exit: + FAPI_IMP("<< pm_pss_init"); return fapi2::current_err; } @@ -288,7 +288,7 @@ fapi_try_exit: fapi2::ReturnCode pm_pss_reset( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { - FAPI_IMP("pm_pss_reset Enter"); + FAPI_IMP(">> pm_pss_reset"); fapi2::buffer<uint64_t> l_data64; uint32_t l_pollcount = 0; @@ -319,7 +319,8 @@ fapi2::ReturnCode pm_pss_reset( // ADC error FAPI_ASSERT(l_data64.getBit<7>() != 1, fapi2::PM_PSS_ADC_ERROR() - .set_CHIP(i_target), + .set_CHIP(i_target) + .set_POLLCOUNT(l_pollcount), "Error while sending the frames from ADC to APSS device"); FAPI_DBG("Delay before next poll"); @@ -361,7 +362,8 @@ fapi2::ReturnCode pm_pss_reset( // P2S error FAPI_ASSERT(l_data64.getBit<7>() != 1, fapi2::PM_PSS_P2S_ERROR() - .set_CHIP(i_target), + .set_CHIP(i_target) + .set_POLLCOUNT(l_pollcount), "Error while sending the frames from P2S to APSS device"); FAPI_DBG("Delay before next poll"); @@ -404,5 +406,6 @@ fapi2::ReturnCode pm_pss_reset( "Error: Could not clear the P2S reset register"); fapi_try_exit: + FAPI_IMP("<< pm_pss_reset"); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H index 22a99a1a0..efb7c53f6 100755 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pss_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -25,12 +25,12 @@ /// @file p9_pm_pss_init.H /// @brief Initializes P2S and HWC logic /// -// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> -// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: FSP:HS +// *HWP HW Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS /// /// Procedure Summary: diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C index 143e7797d..c0fbde2e1 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C @@ -28,10 +28,10 @@ /// Reset function when needing to restart the OCC complex. /// // *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP HWP Backup Owner : -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> // *HWP Team : PM -// *HWP Level : 2 +// *HWP Level : 3 // *HWP Consumed by : HS /// @@ -75,28 +75,13 @@ enum PPM_MASK }; // ----------------------------------------------------------------------------- -// Function prototypes -// ----------------------------------------------------------------------------- - -/// -/// @brief Clear the Deep Exit Masks -/// -/// @param[in] i_target Chip target -/// -/// @return FAPI2_RC_SUCCESS If the special wake-up is successful, -/// else error code. -/// -fapi2::ReturnCode clear_deep_exit_mask( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); - -// ----------------------------------------------------------------------------- // Function definitions // ----------------------------------------------------------------------------- fapi2::ReturnCode p9_pm_reset( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { - FAPI_IMP("Entering p9_pm_reset ..."); + FAPI_IMP(">> p9_pm_reset"); fapi2::buffer<uint64_t> l_data64; fapi2::ReturnCode l_rc; @@ -222,21 +207,6 @@ fapi2::ReturnCode p9_pm_reset( FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of PSS")); fapi_try_exit: - FAPI_IMP("Exiting p9_pm_reset ..."); + FAPI_IMP("<< p9_pm_reset"); return fapi2::current_err; } - -/// -/// @brief Clear deep exit mask -/// -/// @param[in] i_target Chip target -/// -/// @return FAPI2_RC_SUCCESS on success, else error. -/// -fapi2::ReturnCode clear_deep_exit_mask( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) -{ - FAPI_INF("clear_deep_exit_mask Enter"); - - return fapi2::FAPI2_RC_SUCCESS; -} diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H index 7056dcac1..300b9624a 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H @@ -28,10 +28,10 @@ /// Reset function when needing to restart the OCC complex. /// // *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP HWP Backup Owner : +// *HWP HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com> // *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> // *HWP Team : PM -// *HWP Level : 2 +// *HWP Level : 3 // *HWP Consumed by : HS #ifndef _P9_PM_RESET_H diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml index b0d9e7797..02eafb14a 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -394,6 +394,7 @@ <valueType>uint8</valueType> <enum>NONE = 0xFF, CS0 = 0x00, CS1 = 0x01</enum> <platInit/> + <initToZero/> </attribute> <!-- ********************************************************************* --> <attribute> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml index 3043387ae..a338389b2 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -23,6 +23,14 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <!-- Error definitions for p9_pm_init procedure --> +<!-- + *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> + *HWP HWP Backup Owner: Prasad BG Ranganath <prasadbgr@in.ibm.com> + *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> + *HWP Team: PM + *HWP Level: 3 + *HWP Consumed by: HS +--> <hwpErrors> <!-- ******************************************************************** --> <hwpError> @@ -30,6 +38,10 @@ <description>Unknown mode passed to p9_pm_init. </description> <ffdc>BADMODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml index e8b948db7..64d7041c0 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_gpe_init_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -22,22 +22,117 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- + *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> + *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com> + *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> + *HWP Team: PM + *HWP Level: 3 + *HWP Consumed by: HS +--> <hwpErrors> <!-- ********************************************************************* --> <hwpError> <rc>RC_PM_OCC_GPE_BAD_MODE</rc> <description>Unknown mode passed to p9_pm_occ_gpe_init.</description> <ffdc>BADMODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ********************************************************************* --> <hwpError> - <rc>RC_PM_OCC_GPE_RESET_TIMEOUT</rc> - <description>Failed to halt OCC GPE during RESET operation.</description> + <rc>RC_GPE0_IN_HALT_BEFORE_RESET</rc> + <description>Reset not attempted as GPE0 was already in a halt state </description> + <ffdc>CHIP</ffdc> + <ffdc>GPE0_STATUS</ffdc> + <ffdc>GPE0_MODE</ffdc> + + <collectRegisterFfdc> + <id>OCCGPE0_FFDC_REGISTERS</id> + <target>CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, GPE0_MODE, GPE0_BASE_ADDRESS</collectFfdc> + + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + + </hwpError> + <!-- ********************************************************************* --> + <hwpError> + <rc>RC_GPE1_IN_HALT_BEFORE_RESET</rc> + <description>Reset not attempted as GPE1 was already in a halt state </description> + <ffdc>CHIP</ffdc> + <ffdc>GPE1_STATUS</ffdc> + <ffdc>GPE1_MODE</ffdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, GPE1_MODE, GPE1_BASE_ADDRESS</collectFfdc> + + <collectRegisterFfdc> + <id>OCCGPE1_FFDC_REGISTERS</id> + <target>CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ********************************************************************* --> + <hwpError> + <rc>RC_PM_OCC_GPE0_RESET_TIMEOUT</rc> + <description>Failed to halt OCC GPE0 during RESET operation.</description> + <ffdc>CHIP</ffdc> + <ffdc>GPE0_MODE</ffdc> + <ffdc>GPE0_BASE_ADDRESS</ffdc> + <collectRegisterFfdc> - <id>OCCGPE_FFDC_REGISTERS</id> + <id>OCCGPE0_FFDC_REGISTERS</id> <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, GPE0_MODE, GPE0_BASE_ADDRESS</collectFfdc> + + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ********************************************************************* --> + <hwpError> + <rc>RC_PM_OCC_GPE1_RESET_TIMEOUT</rc> + <description>Failed to halt OCC GPE1 during RESET operation.</description> + <ffdc>CHIP</ffdc> + <ffdc>GPE1_MODE</ffdc> + <ffdc>GPE1_BASE_ADDRESS</ffdc> + + <collectRegisterFfdc> + <id>OCCGPE1_FFDC_REGISTERS</id> + <target>CHIP</target> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + </collectRegisterFfdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, GPE1_MODE, GPE1_BASE_ADDRESS</collectFfdc> + + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ********************************************************************* --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pba_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pba_init_errors.xml index 93f2d6d98..b7926e042 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pba_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pba_init_errors.xml @@ -23,6 +23,14 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <!-- Error definitions for p9_pm_pba_init procedure --> +<!-- + *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> + *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com> + *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> + *HWP Team: PM + *HWP Level: 3 + *HWP Consumed by: FSP:HS +--> <hwpErrors> <!-- *********************************************************************--> <hwpError> @@ -43,6 +51,7 @@ <ffdc>POLLCOUNT</ffdc> <ffdc>SLAVENUM</ffdc> <ffdc>PBASLVREG</ffdc> + <ffdc>CHIP</ffdc> <collectRegisterFfdc> <id>PBA_FFDC_REGISTERS</id> <target>CHIP</target> @@ -61,6 +70,7 @@ <ffdc>POLLCOUNT</ffdc> <ffdc>SLAVENUM</ffdc> <ffdc>PBASLVREG</ffdc> + <ffdc>CHIP</ffdc> <collectRegisterFfdc> <id>PBA_FFDC_REGISTERS</id> <target>CHIP</target> @@ -79,6 +89,7 @@ </description> <ffdc>POLLCOUNT</ffdc> <ffdc>POLLVALUE</ffdc> + <ffdc>CHIP</ffdc> <collectRegisterFfdc> <id>PBA_FFDC_REGISTERS</id> <target>CHIP</target> @@ -97,6 +108,7 @@ </description> <ffdc>POLLCOUNT</ffdc> <ffdc>POLLVALUE</ffdc> + <ffdc>CHIP</ffdc> <collectRegisterFfdc> <id>PBA_FFDC_REGISTERS</id> <target>CHIP</target> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml index 4e9e3e42d..4e830f492 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pss_errors.xml @@ -23,11 +23,22 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <!-- Error definitions for p9_pm_pss_init procedure --> +<!-- + *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> + *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com> + *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> + *HWP Team: PM + *HWP Level: 3 + *HWP Consumed by: HS +--> <hwpErrors> <!-- *********************************************************************** --> <hwpError> <rc>RC_PM_PSS_ADC_ERROR</rc> - <description>SPIADC error bit asserted waiting for operation to complete.</description> + <description>SPIADC error bit asserted waiting for operation to complete. + </description> + <ffdc>CHIP</ffdc> + <ffdc>POLLCOUNT</ffdc> <collectRegisterFfdc> <id>PSS_FFDC_REGISTERS</id> <target>CHIP</target> @@ -37,11 +48,18 @@ <target>CHIP</target> <priority>HIGH</priority> </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PM_PSS_P2S_ERROR</rc> - <description>SPIP2S error bit asserted waiting for operation to complete.</description> + <description>SPIP2S error bit asserted waiting for operation to complete. + </description> + <ffdc>CHIP</ffdc> + <ffdc>POLLCOUNT</ffdc> <collectRegisterFfdc> <id>PSS_FFDC_REGISTERS</id> <target>CHIP</target> @@ -51,6 +69,10 @@ <target>CHIP</target> <priority>HIGH</priority> </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> </hwpError> <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml index ce6cec022..f6df0e6d1 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml @@ -84,13 +84,10 @@ </registerFfdc> <!-- ******************************************************************** --> <registerFfdc> - <id>OCCGPE_FFDC_REGISTERS</id> + <id>OCCGPE0_FFDC_REGISTERS</id> <scomRegister>PU_GPE0_GPEXIXSR_SCOM</scomRegister> <scomRegister>PU_GPE0_GPEXIIAR_SCOM</scomRegister> <scomRegister>PU_GPE0_GPEXIIR_SCOM</scomRegister> - <scomRegister>PU_GPE1_GPEXIXSR_SCOM</scomRegister> - <scomRegister>PU_GPE1_GPEXIIAR_SCOM</scomRegister> - <scomRegister>PU_GPE1_GPEXIIR_SCOM</scomRegister> <scomRegister>PU_GPE0_GPETSEL_SCOM</scomRegister> <scomRegister>PU_GPE0_GPEIVPR_SCOM</scomRegister> <scomRegister>PU_GPE0_GPESTR_SCOM</scomRegister> @@ -98,6 +95,13 @@ <scomRegister>PU_GPE0_MIB_XISGB</scomRegister> <scomRegister>PU_GPE0_MIB_XIICAC</scomRegister> <scomRegister>PU_GPE0_MIB_XIDCAC_SCOM</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>OCCGPE1_FFDC_REGISTERS</id> + <scomRegister>PU_GPE1_GPEXIXSR_SCOM</scomRegister> + <scomRegister>PU_GPE1_GPEXIIAR_SCOM</scomRegister> + <scomRegister>PU_GPE1_GPEXIIR_SCOM</scomRegister> <scomRegister>PU_GPE1_GPETSEL_SCOM</scomRegister> <scomRegister>PU_GPE1_GPEIVPR_SCOM</scomRegister> <scomRegister>PU_GPE1_GPESTR_SCOM</scomRegister> |
