diff options
46 files changed, 4451 insertions, 1949 deletions
diff --git a/src/include/usr/isteps/istep06list.H b/src/include/usr/isteps/istep06list.H index 49a45799f..e804df5f7 100644 --- a/src/include/usr/isteps/istep06list.H +++ b/src/include/usr/isteps/istep06list.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -155,6 +157,7 @@ const DepModInfo g_istep06Dependancies = { DEP_LIB(libbuild_winkle_images.so), //proc_mailbox_utils DEP_LIB(libslave_sbe.so), DEP_LIB(libsbe.so), + DEP_LIB(libporeve.so), NULL } }; diff --git a/src/usr/hwpf/fapi/fapiParseErrorInfo.pl b/src/usr/hwpf/fapi/fapiParseErrorInfo.pl index 6481b9ca9..b08bbeeb7 100755 --- a/src/usr/hwpf/fapi/fapiParseErrorInfo.pl +++ b/src/usr/hwpf/fapi/fapiParseErrorInfo.pl @@ -6,7 +6,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2011,2014 +# Contributors Listed Below - COPYRIGHT 2011,2014 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -21,7 +23,7 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG -# $Id: fapiParseErrorInfo.pl,v 1.29 2014/06/11 16:47:16 maploetz Exp $ +# $Id: fapiParseErrorInfo.pl,v 1.30 2014/07/25 00:36:41 jmcgill Exp $ # Purpose: This perl script will parse HWP Error XML files and create required # FAPI code. # @@ -1205,15 +1207,6 @@ print SBFILE " default:\\\n"; print SBFILE " FAPI_SET_HWP_ERROR(RC, RC_SBE_UNKNOWN_ERROR);\\\n"; print SBFILE " break;\\\n"; print SBFILE "}\\\n"; -print SBFILE "const void * l_objects[] = {&CHIP_IN_ERROR};\\\n"; -print SBFILE "fapi::ReturnCode::ErrorInfoEntry l_entries[1];\\\n"; -print SBFILE "l_entries[0].iv_type = fapi::ReturnCode::EI_TYPE_CDG;\\\n"; -print SBFILE "l_entries[0].target_cdg.iv_targetObjIndex = 0;\\\n"; -print SBFILE "l_entries[0].target_cdg.iv_callout = 1;\\\n"; -print SBFILE "l_entries[0].target_cdg.iv_deconfigure = 1;\\\n"; -print SBFILE "l_entries[0].target_cdg.iv_gard = 1;\\\n"; -print SBFILE "l_entries[0].target_cdg.iv_calloutPriority = fapi::CalloutPriorities::HIGH;\\\n"; -print SBFILE "RC.addErrorInfo(l_objects, l_entries, 1);\\\n"; print SBFILE "}\n\n"; print SBFILE "#endif\n"; diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C index e0a36d6e6..0983c977d 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -20,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_image_help.C,v 1.60 2014/01/25 05:28:39 cmolsen Exp $ +// $Id: p8_image_help.C,v 1.61 2014/07/23 20:08:36 jmcgill Exp $ // /*------------------------------------------------------------------------------*/ /* *! TITLE : p8_image_help.C */ @@ -485,7 +487,8 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s pore_XORI( &ctx, D0, D0, ((uint64_t)scanRingCheckWord) << 32); PORE_LOCATION( &ctx, src5); pore_BRAZ( &ctx, D0, tgt5); - pore_HALT( &ctx); + pore_inline_instruction1( &ctx, 0x34, 0x616C74); + pore_inline_instruction1( &ctx, 0x00, 0xCB0DA9); PORE_LOCATION( &ctx, tgt5); if (ctx.error > 0) { MY_ERR("***LD, XORI, BRANZ, RET or HALT went wrong rc = %d", ctx.error); @@ -519,7 +522,8 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s pore_XORI( &ctx, D0, D0, ((uint64_t)scanRingCheckWord) << 32); PORE_LOCATION( &ctx, src8); pore_BRAZ( &ctx, D0, tgt8); - pore_HALT( &ctx); + pore_inline_instruction1( &ctx, 0x34, 0x616C74); + pore_inline_instruction1( &ctx, 0x00, 0xCB0DA9); PORE_LOCATION( &ctx, tgt8); pore_STI(&ctx, GENERIC_CLK_SCAN_UPDATEDR_0x0003A000, P0, 0x0); pore_RET( &ctx); diff --git a/src/usr/hwpf/hwp/cen_fir_registers.xml b/src/usr/hwpf/hwp/cen_fir_registers.xml new file mode 100644 index 000000000..b1c973685 --- /dev/null +++ b/src/usr/hwpf/hwp/cen_fir_registers.xml @@ -0,0 +1,158 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/cen_fir_registers.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: cen_fir_registers.xml,v 1.1 2014/07/23 20:16:05 jmcgill Exp $ --> +<!-- Definition of FIR registers to collect on some errors --> +<hwpErrors> + <!-- ******************************************************************** --> + <!-- All FIRs *********************************************************** --> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_CEN_FIR_FFDC</rc> + <description> + FFDC collected on Centaur FIR errors + </description> + <ffdc>TARGET</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_CHIP_MASTER_INTERRUPT_REGISTERS</id> + <id>REG_FFDC_CEN_CHIP_GLOB_XFIR_REGISTERS</id> + <id>REG_FFDC_CEN_CHIP_GLOB_RFIR_REGISTERS</id> + <id>REG_FFDC_CEN_CHIP_GLOB_FIR_MASK_REGISTERS</id> + <id>REG_FFDC_CEN_CHIP_GLOB_ATTN_REGISTERS</id> + <id>REG_FFDC_CEN_CHIP_GLOB_ATTN_MASK_REGISTERS</id> + <id>REG_FFDC_CEN_CHIP_LFIR_REGISTERS</id> + <id>REG_FFDC_CEN_CHIP_LFIR_MASK_REGISTERS</id> + <target>TARGET</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_MBA_LFIR_REGISTERS</id> + <id>REG_FFDC_CEN_MBA_LFIR_MASK_REGISTERS</id> + <childTargets> + <parent>TARGET</parent> + <childType>TARGET_TYPE_MBA_CHIPLET</childType> + </childTargets> + </collectRegisterFfdc> + </hwpError> + <!-- ******************************************************************** --> + <!-- Chip Level FFDC **************************************************** --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_MASTER_INTERRUPT_REGISTERS</id> + <cfamRegister>CFAM_FSI_STATUS_0x00001007</cfamRegister> + <scomRegister>MASTER_PCB_INT_0x000F001A</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_GLOB_XFIR_REGISTERS</id> + <scomRegister>READ_GLOBAL_XSTOP_FIR_0x570F001B</scomRegister> + <scomRegister>TP_XSTOP_0x01040000</scomRegister> + <scomRegister>NEST_XSTOP_0x02040000</scomRegister> + <scomRegister>MEM_XSTOP_0x03040000</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_GLOB_RFIR_REGISTERS</id> + <scomRegister>READ_GLOBAL_RECOV_FIR_0x570F001C</scomRegister> + <scomRegister>TP_RECOV_0x01040001</scomRegister> + <scomRegister>NEST_RECOV_0x02040001</scomRegister> + <scomRegister>MEM_RECOV_0x03040001</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_GLOB_FIR_MASK_REGISTERS</id> + <scomRegister>TP_FIR_MASK_0x01040002</scomRegister> + <scomRegister>NEST_FIR_MASK_0x02040002</scomRegister> + <scomRegister>MEM_FIR_MASK_0x03040002</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_GLOB_ATTN_REGISTERS</id> + <scomRegister>READ_GLOBAL_SPATT_FIR_0x570F001A</scomRegister> + <scomRegister>TP_SPATTN_0x01040004</scomRegister> + <scomRegister>NEST_SPATTN_0x02040004</scomRegister> + <scomRegister>MEM_SPATTN_0x03040004</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_GLOB_ATTN_MASK_REGISTERS</id> + <scomRegister>TP_SPATTN_MASK_0x01040007</scomRegister> + <scomRegister>NEST_SPATTN_MASK_0x02040007</scomRegister> + <scomRegister>MEM_SPATTN_MASK_0x03040007</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_LFIR_REGISTERS</id> + <scomRegister>TP_PERV_LFIR_0x0104000A</scomRegister> + <scomRegister>NEST_PERV_LFIR_0x0204000A</scomRegister> + <scomRegister>CEN_DMIFIR_0x02010400</scomRegister> + <scomRegister>MBI_FIR_0x02010800</scomRegister> + <scomRegister>MBS_FIR_REG_0x02011400</scomRegister> + <scomRegister>MBS_ECC0_MBECCFIR_0x02011440</scomRegister> + <scomRegister>MBS_ECC1_MBECCFIR_0x02011480</scomRegister> + <scomRegister>MBS01_MBSFIRQ_0x02011600</scomRegister> + <scomRegister>MBS23_MBSFIRQ_0x02011700</scomRegister> + <scomRegister>FBISTN_FIR_REG_0x02010880</scomRegister> + <scomRegister>SCAC_LFIR_0x020115C0</scomRegister> + <scomRegister>MBSS_FIR_REG_0x0201141E</scomRegister> + <scomRegister>MEM_PERV_LFIR_0x0304000A</scomRegister> + <scomRegister>FBISTM_FIR_REG_0x03010480</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_CHIP_LFIR_MASK_REGISTERS</id> + <scomRegister>TP_PERV_LFIR_MASK_0x0104000D</scomRegister> + <scomRegister>NEST_PERV_LFIR_MASK_0x0204000D</scomRegister> + <scomRegister>CEN_DMIFIR_MASK_0x02010403</scomRegister> + <scomRegister>MBI_FIRMASK_0x02010803</scomRegister> + <scomRegister>MBS_FIR_MASK_REG_0x02011403</scomRegister> + <scomRegister>MBS_ECC0_MBECCFIR_MASK_0x02011443</scomRegister> + <scomRegister>MBS_ECC1_MBECCFIR_MASK_0x02011483</scomRegister> + <scomRegister>MBS01_MBSFIRMASK_0x02011603</scomRegister> + <scomRegister>MBS23_MBSFIRMASK_0x02011703</scomRegister> + <scomRegister>FBISTN_FIR_MASK_REG_0x02010883</scomRegister> + <scomRegister>SCAC_FIRMASK_0x020115C3</scomRegister> + <scomRegister>MBSS_FIR_MASK_REG_0x02011421</scomRegister> + <scomRegister>MEM_PERV_LFIR_MASK_0x0304000D</scomRegister> + <scomRegister>FBISTM_FIR_MASK_REG_0x03010483</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <!-- MBA Chiplet Level FFDC ********************************************* --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_MBA_LFIR_REGISTERS</id> + <scomRegister>MBA01_MBACALFIR_0x03010400</scomRegister> + <scomRegister>MBA01_MBAFIRQ_0x03010600</scomRegister> + <scomRegister>PHY01_DDRPHY_FIR_REG_0x800200900301143f</scomRegister> + <scomRegister>MBAS_FIR_REG_0x0301041B</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CEN_MBA_LFIR_MASK_REGISTERS</id> + <scomRegister>MBA01_MBACALFIR_MASK_0x03010403</scomRegister> + <scomRegister>MBA01_MBAFIRMASK_0x03010603</scomRegister> + <scomRegister>PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143f</scomRegister> + <scomRegister>MBAS_FIR_MASK_REG_0x0301041E</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml index 7a8f726c4..151ca013a 100644 --- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml +++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2012,2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -21,7 +23,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> -<!-- $Id: memory_errors.xml,v 1.45 2014/03/26 21:30:50 lapietra Exp $ --> +<!-- $Id: memory_errors.xml,v 1.46 2014/07/23 20:16:05 jmcgill Exp $ --> <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID --> <!-- *********************************************************************** --> @@ -43,37 +45,159 @@ <hwpError> <rc>RC_MSS_UNEXPECTED_NEST_CLK_STATUS</rc> <description>A read of the nest clock status register returned an unexpected value.</description> -</hwpError> + <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_NEST_CHIPLET</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> <hwpError> <rc>RC_MSS_INIT1_OPCG_DONE_ERROR</rc> - <description>Timed out waiting for OPCG done bit(15).</description> -</hwpError> + <description>Timed out waiting for OPCG done bit in SCAN0 module.</description> + <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FLUSH_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> <hwpError> <rc>RC_MSS_INIT1_FSISTATUS_FAIL</rc> <description>Failed VDD status check on FSI2PIB Status Reg bit(16).</description> + <sbeError/> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_STANDBY_REGION</id> + <target>CHIP</target> + </collectRegisterFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <hwpError> <rc>RC_MSS_INIT3_FSISTATUS_FAIL</rc> <description>Failed clock region check on FSI2PIB Status Reg bit(31).</description> -</hwpError> + <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_TP_CHIPLET</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> <hwpError> - <rc>RC_MSS_PLL_LOCK_TIMEOUT</rc> - <description>Timed out waiting for PLL locks in FSI2PIB Status Reg bits(24,25). </description> -</hwpError> + <rc>RC_MSS_NEST_PLL_LOCK_TIMEOUT</rc> + <description>Timed out waiting for NEST PLL lock in FSI2PIB Status Reg bit 24. </description> + <sbeError/> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_STANDBY_REGION</id> + <target>CHIP</target> + </collectRegisterFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_MSS_MEM_PLL_LOCK_TIMEOUT</rc> + <description>Timed out waiting for MEM PLL lock in FSI2PIB Status Reg bit 25. </description> + <sbeError/> + <collectRegisterFfdc> + <id>REG_FFDC_CEN_STANDBY_REGION</id> + <target>CHIP</target> + </collectRegisterFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> + + <registerFfdc> + <id>REG_FFDC_CEN_STANDBY_REGION</id> + <cfamRegister>CFAM_FSI_STATUS_0x00001007</cfamRegister> + <cfamRegister>CFAM_FSI_GP3_0x00001012</cfamRegister> + <cfamRegister>CFAM_FSI_GP4_0x00001013</cfamRegister> + <cfamRegister>CFAM_FSI_GP4_0x00001013</cfamRegister> + <cfamRegister>CFAM_FSI_GP5_0x00001014</cfamRegister> + <cfamRegister>CFAM_FSI_GP6_0x00001015</cfamRegister> + <cfamRegister>CFAM_FSI_GP7_0x00001016</cfamRegister> + <cfamRegister>CFAM_FSI_GP3_MIRROR_0x0000101B</cfamRegister> + </registerFfdc> <hwpError> <rc>RC_MSS_THOLD_ERROR</rc> <description>THOLDS after Clock Start cmd do NOT match to the expected value.</description> -</hwpError> + <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_TP_CHIPLET</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> <hwpError> <rc>RC_MSS_CCREG_MISMATCH</rc> <description>Clock Control Register does not match the expected value.</description> -</hwpError> + <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_TP_CHIPLET</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> <hwpError> <rc>RC_MSS_ARRAY_REPAIR_BUSY</rc> diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H index dcc4c8fdd..7059a5395 100755 --- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_scom_addresses.H,v 1.69 2014/04/07 17:59:13 gollub Exp $ +// $Id: cen_scom_addresses.H,v 1.70 2014/07/15 13:42:27 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -219,9 +219,11 @@ CONST_UINT64_T( MEM_CHIPLET_0x03000000 , ULL(0x03000000) ); // CENTAUR REPAIR LOADER REGISTERS //------------------------------------------------------------------------------ CONST_UINT64_T( CEN_WRITE_ARRAY_REPAIR_REG_0x00050000, ULL(0x00050000) ); +CONST_UINT64_T( CEN_REPAIR_FRONTEND_REG_0x00050001, ULL(0x00050001) ); CONST_UINT64_T( CEN_WRITE_ARRAY_REPAIR_CMD_0x00050002, ULL(0x00050002) ); CONST_UINT64_T( CEN_READ_ARRAY_REPAIR_STATUS_0x00050003, ULL(0x00050003) ); CONST_UINT64_T( CEN_READ_ECC_TRAP_REGISTER_0x00050004, ULL(0x00050004) ); +CONST_UINT64_T( CEN_REPAIR_CONFIG_REG_0x00050005, ULL(0x00050005) ); CONST_UINT64_T( TP_TRACE_DATA_HI_0x01010440 , ULL(0x01010440) ); CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010441 , ULL(0x01010441) ); @@ -1040,6 +1042,7 @@ CONST_UINT64_T( MBS23_MBMPERQ_0x02011762 , ULL(0x02011762) ); CONST_UINT64_T( MBS01_MBUERQ_0x02011663 , ULL(0x02011663) ); CONST_UINT64_T( MBS23_MBUERQ_0x02011763 , ULL(0x02011763) ); + //------------------------------------------------------------------------------ // MBS FIR Registers //------------------------------------------------------------------------------ @@ -1052,6 +1055,42 @@ CONST_UINT64_T( MBS_FIR_ACTION1_REG_0x02011407 , ULL(0x02011407) ); CONST_UINT64_T( MBS_FIR_WOF_REG_0x02011408 , ULL(0x02011408) ); //------------------------------------------------------------------------------ +// FBIST NEST FIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( FBISTN_FIR_REG_0x02010880 , ULL(0x02010880) ); +CONST_UINT64_T( FBISTN_FIR_MASK_REG_0x02010883 , ULL(0x02010883) ); +CONST_UINT64_T( FBISTN_FIR_MASK_REG_AND_0x02010884 , ULL(0x02010884) ); +CONST_UINT64_T( FBISTN_FIR_MASK_REG_OR_0x02010885 , ULL(0x02010885) ); +CONST_UINT64_T( FBISTN_FIR_ACTION0_REG_0x02010886 , ULL(0x02010886) ); +CONST_UINT64_T( FBISTN_FIR_ACTION1_REG_0x02010887 , ULL(0x02010887) ); + +//------------------------------------------------------------------------------ +// FBIST MEM FIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( FBISTM_FIR_REG_0x03010480 , ULL(0x03010480) ); +CONST_UINT64_T( FBISTM_FIR_MASK_REG_0x03010483 , ULL(0x03010483) ); +CONST_UINT64_T( FBISTM_FIR_MASK_REG_AND_0x03010484 , ULL(0x03010484) ); +CONST_UINT64_T( FBISTM_FIR_MASK_REG_OR_0x03010485 , ULL(0x03010485) ); +CONST_UINT64_T( FBISTM_FIR_ACTION0_REG_0x03010486 , ULL(0x03010486) ); +CONST_UINT64_T( FBISTM_FIR_ACTION1_REG_0x03010487 , ULL(0x03010487) ); + +//------------------------------------------------------------------------------ +// MBS Secure FIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBSS_FIR_REG_0x0201141E , ULL(0x0201141E) ); +CONST_UINT64_T( MBSS_FIR_MASK_REG_0x02011421 , ULL(0x02011421) ); +CONST_UINT64_T( MBSS_FIR_ACTION0_REG_0x02011424 , ULL(0x02011424) ); +CONST_UINT64_T( MBSS_FIR_ACTION1_REG_0x02011425 , ULL(0x02011425) ); + +//------------------------------------------------------------------------------ +// MBA Secure FIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBAS_FIR_REG_0x0301041B , ULL(0x0301041B) ); +CONST_UINT64_T( MBAS_FIR_MASK_REG_0x0301041E , ULL(0x0301041E) ); +CONST_UINT64_T( MBAS_FIR_ACTION0_REG_0x03010421 , ULL(0x03010421) ); +CONST_UINT64_T( MBAS_FIR_ACTION1_REG_0x03010422 , ULL(0x03010422) ); + +//------------------------------------------------------------------------------ // DDRPHY FIR Registers //------------------------------------------------------------------------------ CONST_UINT64_T( PHY01_DDRPHY_FIR_REG_0x800200900301143f , ULL(0x800200900301143f) ); @@ -1815,6 +1854,9 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_scom_addresses.H,v $ +Revision 1.70 2014/07/15 13:42:27 jmcgill +add FIR/repair loader register definitions for FFDC collection (SW260441) + Revision 1.69 2014/04/07 17:59:13 gollub /!/ 1.69 | gollub |07-APR-14| Added MBSCFGQ so we can enable/disable exit point 1 diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H index 711d388f6..3eaa39dc3 100755 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_scom_addresses.H,v 1.183 2014/06/08 19:49:24 jmcgill Exp $ +// $Id: p8_scom_addresses.H,v 1.184 2014/07/15 21:12:03 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -1784,6 +1784,15 @@ CONST_UINT64_T( EX_PERV_TCTL5_SPATTN_0x10013057 , ULL(0x10013057) ); CONST_UINT64_T( EX_PERV_TCTL6_SPATTN_0x10013067 , ULL(0x10013067) ); CONST_UINT64_T( EX_PERV_TCTL7_SPATTN_0x10013077 , ULL(0x10013077) ); +CONST_UINT64_T( EX_PCNE_REG0_HOLD_OUT_0x1001300D , ULL(0x1001300D) ); +CONST_UINT64_T( EX_PCNE_REG1_HOLD_OUT_0x1001301D , ULL(0x1001301D) ); +CONST_UINT64_T( EX_PCNE_REG2_HOLD_OUT_0x1001302D , ULL(0x1001302D) ); +CONST_UINT64_T( EX_PCNE_REG3_HOLD_OUT_0x1001303D , ULL(0x1001303D) ); +CONST_UINT64_T( EX_PCNE_REG4_HOLD_OUT_0x1001304D , ULL(0x1001304D) ); +CONST_UINT64_T( EX_PCNE_REG5_HOLD_OUT_0x1001305D , ULL(0x1001305D) ); +CONST_UINT64_T( EX_PCNE_REG6_HOLD_OUT_0x1001306D , ULL(0x1001306D) ); +CONST_UINT64_T( EX_PCNE_REG7_HOLD_OUT_0x1001307D , ULL(0x1001307D) ); + // Thread Active Status CONST_UINT64_T( EX_PERV_THREAD_ACTIVE_0x1001310E , ULL(0x1001310E) ); @@ -2123,6 +2132,9 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_scom_addresses.H,v $ +Revision 1.184 2014/07/15 21:12:03 jmcgill +add PC_NE error report hold register definitions for FFDC collection (SW261816) + Revision 1.183 2014/06/08 19:49:24 jmcgill add XBUS skew adjust data register definition diff --git a/src/usr/hwpf/hwp/p8_fir_registers.xml b/src/usr/hwpf/hwp/p8_fir_registers.xml new file mode 100644 index 000000000..d8e1dd46e --- /dev/null +++ b/src/usr/hwpf/hwp/p8_fir_registers.xml @@ -0,0 +1,296 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/p8_fir_registers.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: p8_fir_registers.xml,v 1.3 2014/07/23 19:51:48 jmcgill Exp $ --> +<!-- Definition of FIR registers to collect on some errors --> +<hwpErrors> + <!-- ******************************************************************** --> + <!-- All FIRs *********************************************************** --> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_PROC_FIR_FFDC</rc> + <description> + FFDC collected on processor FIR errors + </description> + <ffdc>TARGET</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CHIP_MASTER_INTERRUPT_REGISTERS</id> + <id>REG_FFDC_CHIP_GLOB_XFIR_REGISTERS</id> + <id>REG_FFDC_CHIP_GLOB_RFIR_REGISTERS</id> + <id>REG_FFDC_CHIP_GLOB_FIR_MASK_REGISTERS</id> + <id>REG_FFDC_CHIP_GLOB_ATTN_REGISTERS</id> + <id>REG_FFDC_CHIP_GLOB_ATTN_MASK_REGISTERS</id> + <id>REG_FFDC_CHIP_LFIR_REGISTERS</id> + <id>REG_FFDC_CHIP_LFIR_MASK_REGISTERS</id> + <target>TARGET</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_EX_GLOB_XFIR_REGISTERS</id> + <id>REG_FFDC_EX_GLOB_RFIR_REGISTERS</id> + <id>REG_FFDC_EX_GLOB_FIR_MASK_REGISTERS</id> + <id>REG_FFDC_EX_GLOB_ATTN_REGISTERS</id> + <id>REG_FFDC_EX_GLOB_ATTN_MASK_REGISTERS</id> + <id>REG_FFDC_EX_LFIR_REGISTERS</id> + <id>REG_FFDC_EX_LFIR_MASK_REGISTERS</id> + <childTargets> + <parent>TARGET</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + </childTargets> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_MCS_LFIR_REGISTERS</id> + <id>REG_FFDC_MCS_LFIR_MASK_REGISTERS</id> + <childTargets> + <parent>TARGET</parent> + <childType>TARGET_TYPE_MCS_CHIPLET</childType> + </childTargets> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_XBUS_LFIR_REGISTERS</id> + <id>REG_FFDC_XBUS_LFIR_MASK_REGISTERS</id> + <childTargets> + <parent>TARGET</parent> + <childType>TARGET_TYPE_XBUS_ENDPOINT</childType> + </childTargets> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_ABUS_LFIR_REGISTERS</id> + <id>REG_FFDC_ABUS_LFIR_MASK_REGISTERS</id> + <childTargets> + <parent>TARGET</parent> + <childType>TARGET_TYPE_ABUS_ENDPOINT</childType> + </childTargets> + </collectRegisterFfdc> + </hwpError> + <!-- ******************************************************************** --> + <!-- Chip Level FFDC **************************************************** --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_MASTER_INTERRUPT_REGISTERS</id> + <cfamRegister>CFAM_FSI_STATUS_0x00001007</cfamRegister> + <scomRegister>MASTER_PCB_INT_0x000F001A</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_GLOB_XFIR_REGISTERS</id> + <scomRegister>READ_GLOBAL_XSTOP_FIR_0x570F001B</scomRegister> + <scomRegister>TP_XSTOP_0x01040000</scomRegister> + <scomRegister>NEST_XSTOP_0x02040000</scomRegister> + <scomRegister>X_XSTOP_0x04040000</scomRegister> + <scomRegister>A_XSTOP_0x08040000</scomRegister> + <scomRegister>PCIE_XSTOP_0x09040000</scomRegister> + <scomRegister>PB_RAS_FIR_0x02010C6E</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_GLOB_RFIR_REGISTERS</id> + <scomRegister>READ_GLOBAL_RECOV_FIR_0x570F001C</scomRegister> + <scomRegister>TP_RECOV_0x01040001</scomRegister> + <scomRegister>NEST_RECOV_0x02040001</scomRegister> + <scomRegister>X_RECOV_0x04040001</scomRegister> + <scomRegister>A_RECOV_0x08040001</scomRegister> + <scomRegister>PCIE_RECOV_0x09040001</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_GLOB_FIR_MASK_REGISTERS</id> + <scomRegister>TP_FIR_MASK_0x01040002</scomRegister> + <scomRegister>NEST_FIR_MASK_0x02040002</scomRegister> + <scomRegister>X_FIR_MASK_0x04040002</scomRegister> + <scomRegister>A_FIR_MASK_0x08040002</scomRegister> + <scomRegister>PCIE_FIR_MASK_0x09040002</scomRegister> + <scomRegister>PB_RAS_FIR_MASK_0x02010C71</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_GLOB_ATTN_REGISTERS</id> + <scomRegister>READ_GLOBAL_SPATT_FIR_0x570F001A</scomRegister> + <scomRegister>TP_SPATTN_0x01040004</scomRegister> + <scomRegister>NEST_SPATTN_0x02040004</scomRegister> + <scomRegister>X_SPATTN_0x04040004</scomRegister> + <scomRegister>A_SPATTN_0x08040004</scomRegister> + <scomRegister>PCIE_SPATTN_0x09040004</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_GLOB_ATTN_MASK_REGISTERS</id> + <scomRegister>TP_SPATTN_MASK_0x01040007</scomRegister> + <scomRegister>NEST_SPATTN_MASK_0x02040007</scomRegister> + <scomRegister>X_SPATTN_MASK_0x04040007</scomRegister> + <scomRegister>A_SPATTN_MASK_0x08040007</scomRegister> + <scomRegister>PCIE_SPATTN_MASK_0x09040007</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_LFIR_REGISTERS</id> + <scomRegister>OCC_LFIR_0x01010800</scomRegister> + <scomRegister>PMC_LFIR_0x01010840</scomRegister> + <scomRegister>OCC_PMC_LFIR_0x01010C00</scomRegister> + <scomRegister>TP_PERV_LFIR_0x0104000A</scomRegister> + <scomRegister>PBA_FIR_0x02010840</scomRegister> + <scomRegister>PSI_HB_FIR_0x02010900</scomRegister> + <scomRegister>HCA_EN_FIR_0x02010940</scomRegister> + <scomRegister>HCA_EN_EHHCA_FIR_0x02010980</scomRegister> + <scomRegister>EN_TPC_INTP_SYNC_FIR_0x020109C0</scomRegister> + <scomRegister>PB_FIR_WEST_0x02010C00</scomRegister> + <scomRegister>PB_FIR_CENT_0x02010C40</scomRegister> + <scomRegister>PB_FIR_EAST_0x02010C80</scomRegister> + <scomRegister>PCIE0_FIR_0x02012000</scomRegister> + <scomRegister>PCIE1_FIR_0x02012400</scomRegister> + <scomRegister>PCIE2_FIR_0x02012800</scomRegister> + <scomRegister>NX_CQ_FIR_0x02013080</scomRegister> + <scomRegister>NX_AS_FIR_0x020130C0</scomRegister> + <scomRegister>NX_DMA_ENG_FIR_0x02013100</scomRegister> + <scomRegister>NX_CAPP_FIR_0x02013000</scomRegister> + <scomRegister>MCD_FIR_0x02013400</scomRegister> + <scomRegister>NEST_PERV_LFIR_0x0204000A</scomRegister> + <scomRegister>PB_X_FIR_0x04010C00</scomRegister> + <scomRegister>X_PSI_FIR_0x04012400</scomRegister> + <scomRegister>X_PERV_LFIR_0x0404000A</scomRegister> + <scomRegister>PB_A_FIR_0x08010800</scomRegister> + <scomRegister>A_PERV_LFIR_0x0804000A</scomRegister> + <scomRegister>ES_PBES_WRAP_TOP_FIR_0x09010800</scomRegister> + <scomRegister>PCIE_IOP0_PLL_FIR_0x09011400</scomRegister> + <scomRegister>PCIE_IOP1_PLL_FIR_0x09011840</scomRegister> + <scomRegister>PCIE_PERV_LFIR_0x0904000A</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_CHIP_LFIR_MASK_REGISTERS</id> + <scomRegister>OCC_LFIR_MASK_0x01010803</scomRegister> + <scomRegister>PMC_LFIR_MASK_0x01010843</scomRegister> + <scomRegister>OCC_PMC_LFIR_MASK_0x01010C03</scomRegister> + <scomRegister>TP_PERV_LFIR_MASK_0x0104000D</scomRegister> + <scomRegister>PBA_FIR_MASK_0x02010843</scomRegister> + <scomRegister>PSI_HB_FIR_MASK_0x02010903</scomRegister> + <scomRegister>HCA_EN_FIR_MASK_0x02010943</scomRegister> + <scomRegister>HCA_EN_EHHCA_FIR_MASK_0x02010983</scomRegister> + <scomRegister>EN_TPC_INTP_SYNC_FIR_MASK_0x020109C3</scomRegister> + <scomRegister>PB_FIR_MASK_WEST_0x02010C03</scomRegister> + <scomRegister>PB_FIR_MASK_CENT_0x02010C43</scomRegister> + <scomRegister>PB_FIR_MASK_EAST_0x02010C83</scomRegister> + <scomRegister>PCIE0_FIR_MASK_0x02012003</scomRegister> + <scomRegister>PCIE1_FIR_MASK_0x02012403</scomRegister> + <scomRegister>PCIE2_FIR_MASK_0x02012803</scomRegister> + <scomRegister>NX_CQ_FIR_MASK_0x02013083</scomRegister> + <scomRegister>NX_AS_FIR_MASK_0x020130C3</scomRegister> + <scomRegister>NX_DMA_ENG_FIR_MASK_0x02013103</scomRegister> + <scomRegister>NX_CAPP_FIR_MASK_0x02013003</scomRegister> + <scomRegister>MCD_FIR_MASK_0x02013403</scomRegister> + <scomRegister>NEST_PERV_LFIR_MASK_0x0204000D</scomRegister> + <scomRegister>PB_X_FIR_MASK_0x04010C03</scomRegister> + <scomRegister>X_PSI_FIR_MASK_0x04012403</scomRegister> + <scomRegister>X_PERV_LFIR_MASK_0x0404000D</scomRegister> + <scomRegister>PB_A_FIR_MASK_0x08010803</scomRegister> + <scomRegister>A_PERV_LFIR_MASK_0x0804000D</scomRegister> + <scomRegister>ES_PBES_WRAP_TOP_FIR_MASK_0x09010803</scomRegister> + <scomRegister>PCIE_IOP0_PLL_FIR_MASK_0x09011403</scomRegister> + <scomRegister>PCIE_IOP1_PLL_FIR_MASK_0x09011843</scomRegister> + <scomRegister>PCIE_PERV_LFIR_MASK_0x0904000D</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <!-- EX Chiplet Level FFDC ********************************************** --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_EX_GLOB_XFIR_REGISTERS</id> + <scomRegister>EX_XSTOP_0x10040000</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_EX_GLOB_RFIR_REGISTERS</id> + <scomRegister>EX_RECOV_0x10040001</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_EX_GLOB_FIR_MASK_REGISTERS</id> + <scomRegister>EX_FIR_MASK_0x10040002</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_EX_GLOB_ATTN_REGISTERS</id> + <scomRegister>EX_SPATTN_0x10040004</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_EX_GLOB_ATTN_MASK_REGISTERS</id> + <scomRegister>EX_SPATTN_MASK_0x10040007</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_EX_LFIR_REGISTERS</id> + <scomRegister>EX_CORE_FIR_0x10013100</scomRegister> + <scomRegister>EX_L2_FIR_REG_0x10012800</scomRegister> + <scomRegister>EX_L3_FIR_REG_0x10010800</scomRegister> + <scomRegister>EX_NCU_FIR_REG_0x10010C00</scomRegister> + <scomRegister>EX_PERV_LFIR_0x1004000A</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_EX_LFIR_MASK_REGISTERS</id> + <scomRegister>EX_CORE_FIR_MASK_0x10013103</scomRegister> + <scomRegister>EX_L2_FIR_MASK_REG_0x10012803</scomRegister> + <scomRegister>EX_L3_FIR_MASK_REG_0x10010803</scomRegister> + <scomRegister>EX_NCU_FIR_MASK_REG_0x10010C03</scomRegister> + <scomRegister>EX_PERV_LFIR_MASK_0x1004000D</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <!-- MCS Chiplet Level FFDC ********************************************* --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_MCS_LFIR_REGISTERS</id> + <scomRegister>MCS_MCIFIR_0x02011840</scomRegister> + <scomRegister>IOMC0_BUSCNTL_FIR_0x02011A00</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_MCS_LFIR_MASK_REGISTERS</id> + <scomRegister>MCS_MCIFIRMASK_0x02011843</scomRegister> + <scomRegister>IOMC0_BUSCNTL_FIR_MASK_0x02011A03</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <!-- XBUS Chiplet Level FFDC ******************************************** --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_XBUS_LFIR_REGISTERS</id> + <scomRegister>X_XBUS0_BUSCNTL_FIR_0x04011000</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_XBUS_LFIR_MASK_REGISTERS</id> + <scomRegister>X_XBUS0_BUSCNTL_FIR_MASK_0x04011003</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <!-- ABUS Chiplet Level FFDC ******************************************** --> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_ABUS_LFIR_REGISTERS</id> + <scomRegister>A_ABUS_BUSCNTL_FIR_0x08010C00</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_ABUS_LFIR_MASK_REGISTERS</id> + <scomRegister>A_ABUS_BUSCNTL_FIR_MASK_0x08010C03</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/p8_slw_registers.xml b/src/usr/hwpf/hwp/p8_slw_registers.xml index c251ce4bb..cee0c97bb 100644 --- a/src/usr/hwpf/hwp/p8_slw_registers.xml +++ b/src/usr/hwpf/hwp/p8_slw_registers.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2013,2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_slw_registers.xml,v 1.5 2014/02/10 04:46:50 stillgs Exp $ --> +<!-- $Id: p8_slw_registers.xml,v 1.6 2014/07/23 19:51:48 jmcgill Exp $ --> <!-- Definition of SLW registers to collect on some errors --> <hwpErrors> <registerFfdc> @@ -99,4 +101,10 @@ <scomRegister>EX_PCBS_DPLL_STATUS_REG_100F0161</scomRegister> <scomRegister>EX_DPLL_CPM_PARM_REG_0x100F0152</scomRegister> </registerFfdc> + <registerFfdc> + <id>REG_FFDC_PROC_SLW_SPWKUP_REGISTERS</id> + <scomRegister>PM_SPECIAL_WKUP_FSP_0x100F010B</scomRegister> + <scomRegister>PM_SPECIAL_WKUP_OCC_0x100F010C</scomRegister> + <scomRegister>PM_SPECIAL_WKUP_PHYP_0x100F010D</scomRegister> + </registerFfdc> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_pba_utils_registers.xml b/src/usr/hwpf/hwp/proc_pba_utils_registers.xml new file mode 100644 index 000000000..102b7f0ff --- /dev/null +++ b/src/usr/hwpf/hwp/proc_pba_utils_registers.xml @@ -0,0 +1,54 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_pba_utils_registers.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_pba_utils_registers.xml,v 1.2 2014/07/23 19:51:49 jmcgill Exp $ --> +<!-- Definition of registers to collect on selected PBA errors --> +<hwpErrors> + <registerFfdc> + <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> + <scomRegister>OTPC_M_SECURITY_SWITCH_0x00010005</scomRegister> + <scomRegister>PBA_MODE_0x00064000</scomRegister> + <scomRegister>PBA_SLVRST_0x00064001</scomRegister> + <scomRegister>PBA_SLVCTL3_0x00064007</scomRegister> + <scomRegister>OCB3_ADDRESS_0x0006B070</scomRegister> + <scomRegister>OCB3_STATUS_CONTROL_0x0006B071</scomRegister> + <scomRegister>OCB3_ERROR_STATUS_0x0006B074</scomRegister> + <scomRegister>PBA_BAR3_0x02013F03</scomRegister> + <scomRegister>PBA_BARMSK3_0x02013F07</scomRegister> + <scomRegister>PBA_RBUFVAL2_0x02010852</scomRegister> + <scomRegister>PBA_RBUFVAL3_0x02010853</scomRegister> + <scomRegister>PBA_WBUFVAL0_0x02010858</scomRegister> + <scomRegister>PBA_WBUFVAL1_0x02010859</scomRegister> + <scomRegister>PBA_FIR_0x02010840</scomRegister> + <scomRegister>PBA_FIR_MASK_0x02010843</scomRegister> + <scomRegister>PBA_FIR_ACTION0_0x02010846</scomRegister> + <scomRegister>PBA_FIR_ACTION1_0x02010847</scomRegister> + <scomRegister>PBA_CONFIG_0x0201084B</scomRegister> + <scomRegister>PBA_ERR_RPT0_0x0201084C</scomRegister> + <scomRegister>PBA_ERR_RPT1_0x0201084D</scomRegister> + <scomRegister>PBA_ERR_RPT2_0x0201084E</scomRegister> + <scomRegister>PB_MODE_CENT_0x02010C4A</scomRegister> + <scomRegister>ADU_PMISC_MODE_0x0202000B</scomRegister> + </registerFfdc> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml index b8c9807d0..0201d6f97 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_check_master_errors.xml,v 1.2 2013/06/21 14:38:48 jeshua Exp $ --> +<!-- $Id: proc_sbe_check_master_errors.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_check_master --> <hwpErrors> <!-- ******************************************************************** --> @@ -28,14 +30,33 @@ <rc>RC_SBE_CHECK_MASTER_NO_VALID_MCS</rc> <description> Procedure: proc_sbe_check_master - Both MCL/MCR fences asserted, no functional MCS units are available for use. + Both MCL/MCR fences asserted, no functional MCS units are available for use on master chip. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_CHECK_MASTER</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>NEST_GP0_0x02000000</ffdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_SBE_CHECK_MASTER</id> + <scomRegister>NEST_GP0_0x02000000</scomRegister> + <scomRegister>DEVICE_ID_REG_0x000F000F</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml index 334896354..72cfce8be 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,49 +22,66 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_chiplet_init_errors.xml,v 1.2 2013/12/13 15:59:11 stillgs Exp $ --> +<!-- $Id: proc_sbe_chiplet_init_errors.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_chiplet_init.S --> <hwpErrors> <!-- ******************************************************************** --> <hwpError> <rc>RC_SBE_MPIPL_CLOCK_START_ERROR</rc> <description> - Procedure: proc_sbe_chiplet_init.S + Procedure: proc_sbe_chiplet_init Check that clocks were started to allow AISS access for PCB Fencing failed </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_SBE_MPIPL_PBC_FENCE_TIMEOUT_ERROR</rc> <description> - Procedure: proc_sbe_chiplet_init.S - Check that the PCB Fence was raised fOR MPIPL reset failed + Procedure: proc_sbe_chiplet_init + Check that the PCB Fence was raised for MPIPL reset failed </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_SBE_MPIPL_SECURITY_UNLOCK_ERROR</rc> <description> - Procedure: proc_sbe_chiplet_init.S + Procedure: proc_sbe_chiplet_init The security function failed to unlock for MPIPL restart </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml index 731dc5f73..0b0aa0e23 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_decompress_scan_halt_codes.xml,v 1.3 2013/06/21 22:46:29 jeshua Exp $ --> +<!-- $Id: proc_sbe_decompress_scan_halt_codes.xml,v 1.4 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_decompress_scan.S --> <hwpErrors> <!-- ******************************************************************** --> @@ -32,12 +34,21 @@ however it is not a multicast WRITE type as required. The bad chiplet Id will be found in P0 at the halt. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -49,12 +60,21 @@ register D0. The most likely cause of this error is a problem with the tool chain used to build the SBE IPL images. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -67,12 +87,22 @@ this error is a problem with the tool chain used to build the SBE IPL images. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -86,12 +116,22 @@ cause of this error is a problem with the tool chain used to build the SBE IPL images. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -103,14 +143,22 @@ excess bits. The most likely cause of this error is a problem with the tool chain used to build the SBE IPL images. </description> - <!-- JDS TODO - this FFDC should log the target chiplet - REG_FFDC_PROC_*_CLOCK_CONTROLLER registers as well --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -124,13 +172,22 @@ could be caused by broken hardware, or by any tool problem that would misrepresent the length of the actual hardware scan ring. </description> - <!-- JDS TODO - this FFDC should log the target chiplet - REG_FFDC_PROC_*_CLOCK_CONTROLLER registers as well --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml index 358066958..a36fd1c70 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_ex_dpll_setup_halt_codes.xml,v 1.2 2013/06/21 21:04:33 jeshua Exp $ --> +<!-- $Id: proc_sbe_ex_dpll_setup_halt_codes.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_ex_dpll_setup.S --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,14 +32,22 @@ Procedure: proc_sbe_ex_dpll_setup This error is signalled when the EX DPLL fails to lock after ~150us. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_DPLL_LOCK_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE </procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml index 96ba038a7..1797f7107 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_ex_startclocks_errors.xml,v 1.1 2013/08/30 18:43:18 jeshua Exp $ --> +<!-- $Id: proc_sbe_ex_startclocks_errors.xml,v 1.2 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Error definitions for proc_sbe_ex_startclocks procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -30,13 +32,18 @@ Procedure: proc_sbe_ex_startclocks After trying to start all of the EX clocks, some of the tholds were still high </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <!-- JDS TODO - add the clock status regs for the target EX here--> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -45,12 +52,19 @@ Procedure: proc_sbe_ex_startclocks After starting the EX clocks the system was xstopped </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <!-- JDS TODO - collect the fir regs of the target EX here --> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml index dae3ce4f1..3cab561af 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_fabricinit_errors.xml,v 1.3 2013/06/21 18:50:20 jeshua Exp $ --> +<!-- $Id: proc_sbe_fabricinit_errors.xml,v 1.4 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_fabricinit --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,13 +32,22 @@ Procedure: proc_sbe_fabricinit Fabric init sequence not attempted, fabric arbitration is stopped. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_FABRICINIT</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>ADU_PMISC_MODE_0x0202000B</ffdc> - <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -45,12 +56,32 @@ Procedure: proc_sbe_fabricinit Fabric init failed, or mismatch in expected ADU status. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_FABRICINIT</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>ADU_STATUS_0x02020002</ffdc> - <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_SBE_FABRICINIT</id> + <scomRegister>PB_MODE_CENT_0x02010C4A</scomRegister> + <scomRegister>PB_HP_MODE_NEXT_CENT_0x02010C4B</scomRegister> + <scomRegister>PB_HP_MODE_CURR_CENT_0x02010C4C</scomRegister> + <scomRegister>PB_HPX_MODE_NEXT_CENT_0x02010C4D</scomRegister> + <scomRegister>PB_HPX_MODE_CURR_CENT_0x02010C4E</scomRegister> + <scomRegister>ADU_PMISC_MODE_0x0202000B</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml index a82392d01..4479fa5d4 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_instruct_start_errors.xml,v 1.4 2013/11/04 15:16:34 jeshua Exp $ --> +<!-- $Id: proc_sbe_instruct_start_errors.xml,v 1.5 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_instruct_start --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,15 +32,18 @@ Procedure: proc_sbe_instruct_start Special wakeup before starting instructions failed. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_INSTRUCT_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -47,15 +52,18 @@ Procedure: proc_sbe_instruct_start Thread 0 is still in nap/sleep/winkle after the instruct start </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_INSTRUCT_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -64,14 +72,17 @@ Procedure: proc_sbe_instruct_start Can't start instructions because the core is still in maintenance mode. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_INSTRUCT_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml index 88733209d..6b6405f07 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_lco_loader_errors.xml,v 1.3 2013/06/21 19:15:05 jeshua Exp $ --> +<!-- $Id: proc_sbe_lco_loader_errors.xml,v 1.4 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_lco_loader --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,12 +32,11 @@ Procedure: proc_sbe_lco_loader Attempted to execute procedure with cv_multicast option. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -44,58 +45,73 @@ Procedure: proc_sbe_lco_loader LCO load sequence not attempted, fabric arbitration is stopped. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_FABRICINIT</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>ADU_PMISC_MODE_0x0202000B</ffdc> - <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_SBE_LCO_LOADER_IMAGE_SIZE_PAD_ERR</rc> <description> Procedure: proc_sbe_lco_loader - Image size is not evenly divisible by cacheline size. + Hostboot image size is not evenly divisible by cacheline size. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_SBE_LCO_LOADER_IMAGE_SIZE_OVERFLOW_ERR</rc> <description> Procedure: proc_sbe_lco_loader - Image size is larger than master chiplet cache size. + Hostboot image size is larger than master chiplet cache size. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_SBE_LCO_LOADER_IMAGE_WRAP_ERR</rc> <description> Procedure: proc_sbe_lco_loader - Combination of target base address and image size will wrap OCB address. + Combination of target base address and hostboot image size will wrap OCB address. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -104,13 +120,15 @@ Procedure: proc_sbe_lco_loader Target base address is not cacheline aligned. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -119,13 +137,45 @@ Procedure: proc_sbe_lco_loader PBA slave reset still in progress or buffer is busy. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>PBA_SLVRST_0x00064001</ffdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_LPCM_FIR_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + LPCM FIR register was non-zero after PNOR read. + </description> <sbeError/> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> + <target>CHIP</target> + </collectRegisterFfdc> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -134,13 +184,22 @@ Procedure: proc_sbe_lco_loader Unexpected state in OCB Status Control Register at end of write stream. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>OCB3_STATUS_CONTROL_0x0006B071</ffdc> - <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -149,13 +208,22 @@ Procedure: proc_sbe_lco_loader Unexpected state in PBA FIR Register at end of write stream. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>PBA_FIR_0x02010840</ffdc> - <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -164,13 +232,22 @@ Procedure: proc_sbe_lco_loader Unexpected state in PBA Write Buffer0 Register at end of write stream. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>PBA_WBUFVAL0_0x02010858</ffdc> - <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -179,12 +256,22 @@ Procedure: proc_sbe_lco_loader Unexpected state in PBA Write Buffer1 Register at end of write stream. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>PBA_WBUFVAL1_0x02010859</ffdc> - <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml index d5f239235..ae455f87e 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_npll_setup_errors.xml,v 1.4 2013/06/21 19:00:29 jeshua Exp $ --> +<!-- $Id: proc_sbe_npll_setup_errors.xml,v 1.5 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_npll_setup --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,15 +32,32 @@ Procedure: proc_sbe_npll_setup CP Filter PLL failed to lock. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_SBE_NPLL_SETUP_FILTER_PLL</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>TP_PLL_LOCK_0x010F0019</ffdc> - <ffdc>MBOX_FSIGP4_0x00050013</ffdc> - <ffdc>MBOX_FSIGP3_0x00050012</ffdc> - <sbeError/> + <callout> + <hw> + <hwid>PROC_REF_CLOCK</hwid> + <refTarget>CHIP</refTarget> + </hw> + <priority>HIGH</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE </procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -47,15 +66,32 @@ Procedure: proc_sbe_npll_setup EM Filter PLL failed to lock. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_SBE_NPLL_SETUP_FILTER_PLL</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>TP_PLL_LOCK_0x010F0019</ffdc> - <ffdc>MBOX_FSIGP4_0x00050013</ffdc> - <ffdc>MBOX_FSIGP3_0x00050012</ffdc> - <sbeError/> + <callout> + <hw> + <hwid>PROC_REF_CLOCK</hwid> + <refTarget>CHIP</refTarget> + </hw> + <priority>HIGH</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE </procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -64,14 +100,54 @@ Procedure: proc_sbe_npll_setup X-Bus PLL failed to lock. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_SBE_NPLL_SETUP_XBUS_PLL</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>MBOX_FSIGP4_0x00050013</ffdc> - <ffdc>MBOX_GP3MIR_0x0005001B</ffdc> - <ffdc>X_PLLLOCKREG_0x040F0019</ffdc> - <sbeError/> + <callout> + <hw> + <hwid>PROC_REF_CLOCK</hwid> + <refTarget>CHIP</refTarget> + </hw> + <priority>HIGH</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE </procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_PROC_SBE_NPLL_SETUP_FILTER_PLL</id> + <cfamRegister>CFAM_FSI_GP3_0x00002812</cfamRegister> + <cfamRegister>CFAM_FSI_GP4_0x00002813</cfamRegister> + <cfamRegister>CFAM_FSI_GP6_0x00002815</cfamRegister> + <cfamRegister>CFAM_FSI_GP7_0x00002816</cfamRegister> + <scomRegister>TP_PLL_LOCK_0x010F0019</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_PROC_SBE_NPLL_SETUP_XBUS_PLL</id> + <cfamRegister>CFAM_FSI_GP3_0x00002812</cfamRegister> + <cfamRegister>CFAM_FSI_GP4_0x00002813</cfamRegister> + <cfamRegister>CFAM_FSI_GP6_0x00002815</cfamRegister> + <cfamRegister>CFAM_FSI_GP7_0x00002816</cfamRegister> + <cfamRegister>CFAM_FSI_GP3_MIRROR_0x0000281B</cfamRegister> + <scomRegister>X_PLLLOCKREG_0x040F0019</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> </hwpErrors> + + + diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml index f3c67f7bb..26ab416a7 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_pb_startclocks.xml,v 1.2 2013/06/21 19:20:21 jeshua Exp $ --> +<!-- $Id: proc_sbe_pb_startclocks.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_pb_startclocks --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,12 +32,18 @@ Procedure: proc_sbe_pb_startclocks Failed to start clocks on PB chiplet. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_NEST_CLOCK_CONTROLLER</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_NEST_CHIPLET</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml index 178f7a70b..4db5b30b9 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_pibmem_loader_halt_codes.xml,v 1.2 2013/06/21 18:44:47 jeshua Exp $ --> +<!-- $Id: proc_sbe_pibmem_loader_halt_codes.xml,v 1.3 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_pibmem_loader.S --> <hwpErrors> <hwpError> @@ -32,12 +34,17 @@ Register are in D0 at the time of the halt. Resetting the PIBMEM prior to running proc_sbe_pibmem_loader should clear up this error. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -48,12 +55,17 @@ execution of the procedure. The contents of the PIBMEM Status Register are in D0 at the time of the halt. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -64,12 +76,17 @@ is a hard requirement due to the PORE architecture. The image size passed to the procedure can be found in SPRG0. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -80,12 +97,17 @@ is a hard requirement due to the PORE architecture. The load address passed to the procedure can be found in SPRG0. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -96,11 +118,17 @@ PIBMEM. The image size (in bytes) passed to the procedure is in SPRG0; D1 contains the PIBMEM load address passed to the procedure. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml index 135c39b65..2b5299ca1 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_scominit_errors.xml,v 1.6 2014/02/10 04:30:49 stillgs Exp $ --> +<!-- $Id: proc_sbe_scominit_errors.xml,v 1.7 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_scomint.S --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,24 +32,16 @@ Procedure: proc_sbe_scominit Check of winkle state across all IPLed chiplets using READ-OR failed. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> + <sbeError/> <collectRegisterFfdc> <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + <target>CHIP</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> </basedOnPresentChildren> </collectRegisterFfdc> - <callout> + <callout> <target>CHIP</target> <priority>HIGH</priority> </callout> @@ -55,7 +49,6 @@ <procedure>CODE</procedure> <priority>LOW</priority> </callout> - <sbeError/> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -64,21 +57,13 @@ Procedure: proc_sbe_scominit Check of winkle state across all IPLed chiplets using READ-AND failed. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> + <sbeError/> <collectRegisterFfdc> <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + <target>CHIP</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> </basedOnPresentChildren> </collectRegisterFfdc> <callout> @@ -89,7 +74,6 @@ <procedure>CODE</procedure> <priority>LOW</priority> </callout> - <sbeError/> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -99,20 +83,11 @@ Polling of Idle FSM timed out. </description> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectRegisterFfdc> <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + <target>CHIP</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> </basedOnPresentChildren> </collectRegisterFfdc> <callout> @@ -128,27 +103,19 @@ Procedure: proc_sbe_scominit Polling of PFET controller for idle timed out. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> + <sbeError/> <collectRegisterFfdc> <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + <target>CHIP</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> </basedOnPresentChildren> </collectRegisterFfdc> <callout> <target>CHIP</target> <priority>HIGH</priority> </callout> - <sbeError/> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml index b727e27d8..2d9bfe1ba 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_select_ex_errors.xml,v 1.2 2013/06/21 18:22:23 jeshua Exp $ --> +<!-- $Id: proc_sbe_select_ex_errors.xml,v 1.3 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Error definitions for proc_sbe_select_ex procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -30,13 +32,25 @@ Procedure: proc_sbe_select_ex None of the valid boot cores are enabled </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_SELECT_EX</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>EX_PARTIAL_GOOD_0x520F0012</ffdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -45,12 +59,30 @@ Procedure: proc_sbe_select_ex Skipped the first good boot core and no other good boot core was found </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_SELECT_EX</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>EX_PARTIAL_GOOD_0x520F0012</ffdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- *********************************************************************** --> + <registerFfdc> + <id>REG_FFDC_SBE_SELECT_EX</id> + <scomRegister>EX_PARTIAL_GOOD_0x520F0012</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml index bc2d75c62..c2317fbed 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,51 +22,31 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_setup_evid_errors.xml,v 1.3 2014/03/03 22:00:57 stillgs Exp $ --> +<!-- $Id: proc_sbe_setup_evid_errors.xml,v 1.4 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_setup_evid --> <hwpErrors> <!-- ******************************************************************** --> <hwpError> - <rc>RC_SBE_SET_VID_ERROR</rc> - <description> - Procedure: proc_sbe_setup_evid - Setting the VID with SPIVID returned bad status - </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> <rc>RC_SBE_SET_VID_TIMEOUT</rc> <description> Procedure: proc_sbe_setup_evid Setting EVID during boot timed out on the SPIVID bus </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_O2S_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SET_VID_ZERO_BOOT_VOLTAGE</rc> - <description> - Procedure: proc_sbe_setup_evid - Boot voltage IDs are invalid (0s) - </description> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_O2S_REGISTERS</id> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -73,13 +55,21 @@ Procedure: proc_sbe_setup_evid Errors detected in O2S Status Reg setting Boot Voltage </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> <id>REG_FFDC_O2S_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -88,13 +78,21 @@ Procedure: proc_sbe_setup_evid SPIVID Device did not return good status the Boot Voltage Write operation </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> <id>REG_FFDC_O2S_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml index f09822e9e..60a0f106e 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_tp_switch_gears_errors.xml,v 1.2 2013/06/21 14:45:05 jeshua Exp $ --> +<!-- $Id: proc_sbe_tp_switch_gears_errors.xml,v 1.3 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_tp_switch_gears --> <hwpErrors> <!-- ******************************************************************** --> @@ -30,13 +32,32 @@ Procedure: proc_sbe_tp_switch_gears X-Bus PLL failed to lock (Murano DD1.x workaround). </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_PROC_SBE_NPLL_SETUP_XBUS_PLL</id> + <target>CHIP</target> </collectRegisterFfdc> - <ffdc>X_PLLLOCKREG_0x040F0019</ffdc> - <sbeError/> + <callout> + <hw> + <hwid>PROC_REF_CLOCK</hwid> + <refTarget>CHIP</refTarget> + </hw> + <priority>HIGH</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>MEDIUM</priority> + </callout> + <callout> + <procedure>CODE </procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -45,12 +66,18 @@ Procedure: proc_sbe_tp_switch_gears X-Bus Murano DD1.x workaround header check fail (ie. scan failed) </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_XBUS_CLOCK_CONTROLLER</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml index 5e6911112..2a7a48ea5 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_trigger_winkle_errors.xml,v 1.4 2014/01/26 20:06:34 stillgs Exp $ --> +<!-- $Id: proc_sbe_trigger_winkle_errors.xml,v 1.5 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Error definitions for proc_sbe_trigger_winkle procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -30,24 +32,21 @@ Procedure: proc_sbe_trigger_winkle The master EX chiplet did not enter winkle before the deadman timer expired. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> - </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -56,24 +55,21 @@ Procedure: proc_sbe_trigger_winkle The master EX chiplet wakeup did not hit GOTO before the deadman timer expired. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -82,25 +78,21 @@ Procedure: proc_sbe_trigger_winkle The master EX chiplet wakeup didn't finish before the deadman timer expired. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -109,24 +101,21 @@ Procedure: proc_sbe_trigger_winkle The master EX chiplet woke up but hostboot didn't indicate that it was running before the deadman timer expired. </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP_IN_ERROR</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> - </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml index 61d87f10a..da69d145f 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_slw_base_halt_codes.xml,v 1.9 2013/11/23 00:33:44 cmolsen Exp $ --> +<!-- $Id: proc_slw_base_halt_codes.xml,v 1.10 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Halt codes for proc_slw_*.S --> <hwpErrors> <!-- ******************************************************************** --> @@ -31,11 +33,21 @@ invalid start vector was detected in the EXE_TRIGGER (ETR) register when kicking off an idle transition. The start vector is in ETR(8:11). </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -44,11 +56,17 @@ This error is signalled by proc_slw_poweronoff and indicates that a timeout occured waiting for the VDD PFET sequencer(s) to complete. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -57,11 +75,17 @@ This error is signalled by proc_slw_poweronoff and indicates that a timeout occured waiting for the VCS PFET sequencer(s) to complete. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -70,11 +94,21 @@ This error is signalled by proc_slw_poweronoff and indicates that an invalid PFET decode was detected. This is an SLW firmware issue. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -84,11 +118,17 @@ occured waiting for the internal VRM babystepper to synchronize the idle transition command during sleep entry. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -98,11 +138,17 @@ occured waiting for the internal VRM babystepper to synchronize the idle transition command during winkle entry. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -112,11 +158,17 @@ occured waiting for the internal VRM babystepper to synchronize the idle transition command during a fast exit. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -125,11 +177,17 @@ This error is signalled by proc_slw_base and indicates that a timeout occured while polling for the iVRM calibration to complete. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -139,11 +197,17 @@ occured waiting for the internal VRM babystepper to synchronize the idle transition command during a deep exit after iVRM calibration. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -152,11 +216,17 @@ This error is signalled by proc_slw_base and indicates that a timeout occured waiting for the internal VRM force safe mode to take effect. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -165,11 +235,17 @@ This error is signalled by proc_slw_ram and indicates that a timeout occured waiting the RAM hardware to accept the instruction given to it.. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -178,11 +254,17 @@ This error is signalled by proc_slw_ram and indicates that a timeout occured waiting the RAM hardware to quiesce. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -191,11 +273,17 @@ This error is signalled by proc_slw_ram and indicates that RAM controller indicates recovery is inprogress or an exception has occured.. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -204,24 +292,36 @@ This error is signalled by proc_slw_ram and indicates that a timeout occured looking for good status from the RAM Controller. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_SLW_GOTO_TIMEOUT_ERROR</rc> <description> This error is signalled by proc_slw_base and indicates that a timeout occured - looking for the proper PCBS-PM state before issuing a PCBS-PM GOTO command. + looking for the proper PCBS-PM state before issuing a PCBS-PM "GOTO" command. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -231,11 +331,17 @@ updated the PMC status reg but never reached the subsequent halt op. PMC SLW Timeouts will be indicated without further FIR bits. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -245,11 +351,11 @@ executed the simple halt error injection. PMC SLW Timeouts will be indicated without further FIR bits. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -258,11 +364,11 @@ This error is signalled by proc_slw_pro_epi_log and indicates that the image enabled invalid instruction error injection occured. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -271,11 +377,11 @@ This error is signalled by proc_slw_pro_epi_log and indicates that the image enabled invalid OCI address error injection occured. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -284,11 +390,11 @@ This error is signalled by proc_slw_pro_epi_log and indicates that the image enabled invalid PIB address error injection occured. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -297,11 +403,11 @@ This error is signalled by proc_slw_pro_epi_log and indicates that the image enabled PC underflow error injection occured. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -310,11 +416,11 @@ This error is signalled by proc_slw_pro_epi_log and indicates that the image enabled PC overflow error injection occured. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -323,11 +429,11 @@ This error is signalled by proc_slw_pro_epi_log and indicates that the image enabled timeout error injection occured. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -336,11 +442,17 @@ This error is signalled by proc_slw_error_handler upon a detected error 0 event (non-masked PIB error code). </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -349,11 +461,17 @@ This error is signalled by proc_slw_error_handler upon a detected error 1 event (non-masked OCI error code). </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -362,11 +480,17 @@ This error is signalled by proc_slw_error_handler upon a detected error 2 event (instruction fetch or decode). </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -375,11 +499,17 @@ This error is signalled by proc_slw_error_handler upon a detected error 3 event (internal data error). </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -388,11 +518,17 @@ This error is signalled by proc_slw_error_handler upon a detected error 4 event (an error was detected upon an error). </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -405,11 +541,21 @@ Deep Winkle power up bit. If these bits match, then a hardware fault is the next most probable. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -421,11 +567,21 @@ causes the loss of the High Availability Log Write pointer in the L3 before it could be saved for restoration upon Deep Winkle Exit. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -435,11 +591,17 @@ achieving the special wake-up state after hitting the PCBS GOTO operation to complete deep sleep exit. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -449,11 +611,21 @@ special wake-up override isnt enabled which it must be prior to calling any of the CPM install or enable routines. </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml index 9149a5c11..2842ad9ef 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: sbe_common_halt_codes.xml,v 1.5 2013/06/21 22:57:28 jeshua Exp $ --> +<!-- $Id: sbe_common_halt_codes.xml,v 1.6 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Halt codes for proc_sbe_* procedures common to P8 and Centaur --> <hwpErrors> <!-- ******************************************************************** --> @@ -33,13 +35,6 @@ with the normal successful completion of an IPL by an SBE istep procedure. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> </hwpError> <!-- ******************************************************************** --> @@ -50,13 +45,6 @@ with the normal successful completion of an IPL by an SBE istep procedure on a slave chip. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> </hwpError> <!-- ******************************************************************** --> @@ -67,13 +55,6 @@ with a procedure initiated halt of the SBE code, with the expectation that it will be resumed at a later point in time. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> </hwpError> <!-- ******************************************************************** --> @@ -87,13 +68,6 @@ by setting the PROC_CONTROL_ENTRY_HALT bit in the control word for the procedure. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> </hwpError> <!-- ******************************************************************** --> @@ -115,15 +89,18 @@ procedure. Use the fields of the SBEVITAL register to identify the procedure that failed. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and to log the FIR regs? --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -133,16 +110,17 @@ executing a procedure. Use the fields of the SBEVITAL register to identify the procedure that failed. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and to log the FIR regs? --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> - </hwpError> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_SBE_PROC_SPATTN</rc> @@ -151,15 +129,18 @@ executing a procedure. Use the fields of the SBEVITAL register to identify the procedure that failed. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and to log the FIR regs? --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <!-- ** Halt codes from proc_sbe_pore_errors.S --> @@ -171,15 +152,25 @@ returned a non-0 response. The PORE PIBMS_DBG registers 0 and 1 (plus the remainder of the PORE state) contain the information required for an initial debug of the problem. + + This error should never occur for SBE/SLW, based on the fact that the + HW error handler mechanism is disabled. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -190,17 +181,24 @@ PORE state) contain the information required for an initial debug of the problem. - This error should never occur during an SBE IPL since the SBE does not - include an OCI interface. + This error should never occur for SBE/SLW, based on the fact that the + HW error handler mechanism is disabled. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -212,15 +210,25 @@ o An I2C hang when fetching code from SEEPROM; o A bad branch that starts executing garbage or data; o Memory corruption + + This error should never occur for SBE/SLW, based on the fact that the + HW error handler mechanism is disabled. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -229,17 +237,24 @@ This halt code indicates an internal data error during consistency checking, e.g., a bad scan-data CRC. - This error should never occur during an SBE IPL since the SBE IPL does - not use the PORE SCAND instruction. + This error should never occur for SBE/SLW, based on the fact that the + HW error handler mechanism is disabled. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -248,18 +263,24 @@ This halt code indicates that a second error occurred during processing of an initial error. - It is extremely unlikely that this error would ever occur during an SBE - IPL since the PORE error handlers are nothing more than a single HALT - statement. + This error should never occur for SBE/SLW, based on the fact that the + HW error handler mechanism is disabled. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <!-- ** Halt codes from scan0 subroutine --> @@ -271,15 +292,18 @@ scan0 DONE polling reached the specified threshold value. The scan0 subroutine could have been called by various procedures. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target chiplet --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FLUSH_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- ******************************************************************** --> <!-- ** Halt codes from arrayinit subroutine --> @@ -291,14 +315,18 @@ arrayinit DONE polling reached the specified threshold value. The arrayinit subroutine could have been called by various procedures. </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target chiplet --> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <sbeError/> + <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_ARRAYINIT_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml index 002501f0f..876e0afca 100644 --- a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -20,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: sbe_load_ring_vec_ex_errors.xml,v 1.3 2013/06/21 22:50:58 jeshua Exp $ --> +<!-- $Id: sbe_load_ring_vec_ex_errors.xml,v 1.4 2014/07/23 19:51:50 jmcgill Exp $ --> <!-- Error definitions for sbe_load_ring_vec_ex procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -30,15 +32,21 @@ Procedure: proc_sbe_ex_core_gptr_time_initf Failed to find a chiplet to scan for ex_time_core </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_SELECT_EX</id> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -47,31 +55,44 @@ Procedure: proc_sbe_ex_gptr_time_initf Failed to find a chiplet to scan for ex_time_eco </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_SELECT_EX</id> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_SBE_LOAD_RING_VEC_EX_ex_repr_core_ERROR</rc> <description> Procedure: proc_sbe_ex_core_repair_initf - Failed to find a chiplet to scan for ex_repr_core</description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> + Failed to find a chiplet to scan for ex_repr_core + </description> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_SELECT_EX</id> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -80,14 +101,21 @@ Procedure: proc_sbe_ex_repair_initf Failed to find a chiplet to scan for ex_repr_eco </description> - <!-- JDS TODO - this FFDC should probably only log the target engine - and should log something about the target EX --> + <sbeError/> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> + <id>REG_FFDC_SBE_SELECT_EX</id> + <target>CHIP</target> </collectRegisterFfdc> - <sbeError/> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> </hwpError> + <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/slave_sbe/makefile b/src/usr/hwpf/hwp/slave_sbe/makefile index 9e8c71cf4..2ee5fe406 100644 --- a/src/usr/hwpf/hwp/slave_sbe/makefile +++ b/src/usr/hwpf/hwp/slave_sbe/makefile @@ -45,6 +45,8 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data +EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/porevesrc +EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/model/ ## NOTE: add new object files when you add a new HWP OBJS += slave_sbe.o @@ -58,6 +60,9 @@ OBJS += proc_spless_sbe_startWA.o OBJS += proc_reset_i2cm_bus_fence.o OBJS += proc_check_master_sbe_seeprom.o OBJS += proc_tp_collect_dbg_data.o +OBJS += proc_extract_pore_engine_state.o +OBJS += proc_extract_pore_base_ffdc.o +OBJS += proc_extract_pore_halt_ffdc.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C index 86d92eec0..373a6a49e 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C @@ -23,7 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.14 2014/06/10 12:41:40 dsanner Exp $ +// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.15 2014/07/23 19:30:59 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_slave_sbe_seeprom_complete.C,v $ //------------------------------------------------------------------------------ // *| @@ -61,7 +61,7 @@ const uint8_t SBE_EXIT_SUCCESS_0xF = 0xF; const uint64_t NS_TO_FINISH = 10000000; //(10 ms) const uint64_t MS_TO_FINISH = NS_TO_FINISH/1000000; const uint64_t SIM_CYCLES_TO_FINISH = 10000000; -//Should really be 19.6*NS_TO_FINISH, but sim runs at about 11 hours per +//Should really be 19.6*NS_TO_FINISH, but sim runs at about 11 hours per //simulated second which is longer than we want to wait in error cases @@ -242,7 +242,7 @@ extern "C" do { //Check if the SBE is still running. Loop until stopped - //or loop time is exceeded. + //or loop time is exceeded. bool still_running = true; size_t loop_time = 0; rc = proc_check_slave_sbe_seeprom_complete_check_running( @@ -327,12 +327,12 @@ extern "C" if( halt_code != SBE_EXIT_SUCCESS_0xF ) { FAPI_ERR( - "SBE halted with error %i (istep 0x%X, substep %i)", + "SBE halted with error %i (istep 0x%X, substep %i)", halt_code, istep_num, substep_num); //Get the error code from the SBE code - FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, i_pSEEPROM, SBE); + FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, NULL, i_pSEEPROM, SBE); break; } //Halt code was success @@ -343,7 +343,7 @@ extern "C" ( istep_num != PROC_SBE_EX_HOST_RUNTIME_SCOM_MAGIC_ISTEP_NUM )) { FAPI_ERR( - "SBE halted in wrong istep (istep 0x%X, substep %i)", + "SBE halted in wrong istep (istep 0x%X, substep %i)", istep_num, substep_num); const fapi::Target & CHIP_IN_ERROR = i_target; @@ -362,7 +362,7 @@ extern "C" ( substep_num != SUBSTEP_ENABLE_PNOR_SLAVE_CHIP ))) { FAPI_ERR( - "SBE halted in wrong substep (istep 0x%X, substep %i)", + "SBE halted in wrong substep (istep 0x%X, substep %i)", istep_num, substep_num); const fapi::Target & CHIP_IN_ERROR = i_target; diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C new file mode 100644 index 000000000..f6103356a --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C @@ -0,0 +1,144 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_extract_pore_base_ffdc.C,v 1.1 2014/07/23 19:38:05 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_base_ffdc.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** *** +// *| +// *! TITLE : proc_extract_pore_base_ffdc.C +// *! DESCRIPTION : Log base FFDC for SBE/SLW errors +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com +// *! +// *! Overview: +// *! - Dump state of SBE/SLW engine +// *! - Extract additional FFDC based on engine type +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p8_scom_addresses.H> +#include <proc_extract_pore_base_ffdc.H> +#include <proc_tp_collect_dbg_data.H> + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +extern "C" +{ + + +/** + * proc_extract_pore_engine_state - HWP entry point, log PORE engine state + * + * @param[in] i_pore_state - struct holding PORE state + * @param[in] i_pore_sbe_state - struct holding PORE SBE specific state + * @param[out] o_rc - target return code for extra FFDC + * + * @retval fapi::ReturnCode = SUCCESS + */ +fapi::ReturnCode proc_extract_pore_base_ffdc(const por_base_state & i_pore_state, + const por_sbe_base_state & i_pore_sbe_state, + fapi::ReturnCode & o_rc) + +{ + // return code + fapi::ReturnCode rc; + + FAPI_INF("proc_extract_pore_base_ffdc: Start"); + + do + { + // append to return code + const fapi::Target & CHIP = i_pore_state.target; + const por_engine_t & ENGINE = i_pore_state.engine; + const bool & VIRTUAL = i_pore_state.is_virtual; + const uint64_t & PORE_VITAL_REG = i_pore_state.vital_state.getDoubleWord(0); + const uint64_t & PORE_STATUS_REG = i_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET); + const uint64_t & PORE_CONTROL_REG = i_pore_state.engine_state.getDoubleWord(PORE_CONTROL_OFFSET); + const uint64_t & PORE_RESET_REG = i_pore_state.engine_state.getDoubleWord(PORE_RESET_OFFSET); + const uint64_t & PORE_ERR_MASK_REG = i_pore_state.engine_state.getDoubleWord(PORE_ERR_MASK_OFFSET); + const uint64_t & PORE_P0_REG = i_pore_state.engine_state.getDoubleWord(PORE_P0_OFFSET); + const uint64_t & PORE_P1_REG = i_pore_state.engine_state.getDoubleWord(PORE_P1_OFFSET); + const uint64_t & PORE_A0_REG = i_pore_state.engine_state.getDoubleWord(PORE_A0_OFFSET); + const uint64_t & PORE_A1_REG = i_pore_state.engine_state.getDoubleWord(PORE_A1_OFFSET); + const uint64_t & PORE_TBL_BASE_REG = i_pore_state.engine_state.getDoubleWord(PORE_TBL_BASE_OFFSET); + const uint64_t & PORE_EXE_TRIGGER_REG = i_pore_state.engine_state.getDoubleWord(PORE_EXE_TRIGGER_OFFSET); + const uint64_t & PORE_CTR_REG = i_pore_state.engine_state.getDoubleWord(PORE_CTR_OFFSET); + const uint64_t & PORE_D0_REG = i_pore_state.engine_state.getDoubleWord(PORE_D0_OFFSET); + const uint64_t & PORE_D1_REG = i_pore_state.engine_state.getDoubleWord(PORE_D1_OFFSET); + const uint64_t & PORE_IBUF0_REG = i_pore_state.engine_state.getDoubleWord(PORE_IBUF0_OFFSET); + const uint64_t & PORE_IBUF1_REG = i_pore_state.engine_state.getDoubleWord(PORE_IBUF1_OFFSET); + const uint64_t & PORE_DEBUG0_REG = i_pore_state.engine_state.getDoubleWord(PORE_DEBUG0_OFFSET); + const uint64_t & PORE_DEBUG1_REG = i_pore_state.engine_state.getDoubleWord(PORE_DEBUG1_OFFSET); + const uint64_t & PORE_STACK0_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK0_OFFSET); + const uint64_t & PORE_STACK1_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK1_OFFSET); + const uint64_t & PORE_STACK2_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK2_OFFSET); + const uint64_t & PORE_IDFLAGS_REG = i_pore_state.engine_state.getDoubleWord(PORE_IDFLAGS_OFFSET); + const uint64_t & PORE_SPRG0_REG = i_pore_state.engine_state.getDoubleWord(PORE_SPRG0_OFFSET); + const uint64_t & PORE_MRR_REG = i_pore_state.engine_state.getDoubleWord(PORE_MRR_OFFSET); + const uint64_t & PORE_I2CE0_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE0_OFFSET); + const uint64_t & PORE_I2CE1_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE1_OFFSET); + const uint64_t & PORE_I2CE2_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE2_OFFSET); + const uint64_t & PORE_PC = i_pore_state.pc; + const uint64_t & PORE_RC = i_pore_state.rc; + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_ENGINE_STATE); + + + // + // collect additional FFDC based on engine type + // + + if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP) + { + if (i_pore_state.engine == SBE) + { + const uint64_t & PNOR_ECCB_STATUS = i_pore_sbe_state.pnor_eccb_status.getDoubleWord(0); + const uint64_t & SEEPROM_ECCB_STATUS = i_pore_sbe_state.i2cm_eccb_status.getDoubleWord(0); + const uint8_t & SOFT_ERROR_STATUS = i_pore_sbe_state.soft_err; + const bool & ATTN_REPORTED = i_pore_sbe_state.reported_attn; + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_SBE); + } + else + { + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_SLW); + } + } + } while(0); + + FAPI_INF("proc_extract_pore_base_ffdc: End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H new file mode 100644 index 000000000..10424d9f8 --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H @@ -0,0 +1,86 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_extract_pore_base_ffdc.H,v 1.1 2014/07/23 19:38:05 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_base_ffdc.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** *** +// *| +// *! TITLE : proc_extract_pore_base_ffdc.C +// *! DESCRIPTION : Log base FFDC for SBE/SLW errors +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_EXTRACT_PORE_BASE_FFDC_H_ +#define _PROC_EXTRACT_PORE_BASE_FFDC_H_ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi.H> +#include <proc_extract_sbe_rc.H> + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*proc_extract_pore_base_ffdc_FP_t)(const por_base_state &, + const por_sbe_base_state &, + fapi::ReturnCode &); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + + +extern "C" +{ + +/** + * proc_extract_pore_engine_state - HWP entry point, log PORE engine state + * + * @param[in] i_pore_state - struct holding PORE state + * @param[in] i_pore_sbe_state - struct holding PORE SBE specific state + * @param[out] o_rc - target return code for extra FFDC + * + * @retval fapi::ReturnCode = SUCCESS + */ +fapi::ReturnCode proc_extract_pore_base_ffdc(const por_base_state & i_pore_state, + const por_sbe_base_state & i_pore_sbe_state, + fapi::ReturnCode & o_rc); + + + +} // extern "C" + +#endif // _PROC_EXTRACT_PORE_BASE_FFDC_H_ diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml new file mode 100644 index 000000000..a28556771 --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml @@ -0,0 +1,119 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_extract_pore_base_ffdc.xml,v 1.1 2014/07/23 19:43:18 jmcgill Exp $ --> +<!-- Error definitions for proc_extract_pore_base_ffdc procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC</rc> + <description> + Base error code used to invoke PORE engine state FFDC logging function + </description> + <collectFfdc>proc_extract_pore_base_ffdc, pore_state, pore_sbe_state</collectFfdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_ENGINE_STATE</rc> + <description> + PORE engine state collected on all SBE/SLW fails + </description> + <!-- target/engine type --> + <ffdc>CHIP</ffdc> + <ffdc>ENGINE</ffdc> + <ffdc>VIRTUAL</ffdc> + <!-- SBE/SLW vital state --> + <ffdc>PORE_VITAL_REG</ffdc> + <!-- PORE register state --> + <ffdc>PORE_STATUS_REG</ffdc> + <ffdc>PORE_CONTROL_REG</ffdc> + <ffdc>PORE_RESET_REG</ffdc> + <ffdc>PORE_ERR_MASK_REG</ffdc> + <ffdc>PORE_P0_REG</ffdc> + <ffdc>PORE_P1_REG</ffdc> + <ffdc>PORE_A0_REG</ffdc> + <ffdc>PORE_A1_REG</ffdc> + <ffdc>PORE_TBL_BASE_REG</ffdc> + <ffdc>PORE_EXE_TRIGGER_REG</ffdc> + <ffdc>PORE_CTR_REG</ffdc> + <ffdc>PORE_D0_REG</ffdc> + <ffdc>PORE_D1_REG</ffdc> + <ffdc>PORE_IBUF0_REG</ffdc> + <ffdc>PORE_IBUF1_REG</ffdc> + <ffdc>PORE_DEBUG0_REG</ffdc> + <ffdc>PORE_DEBUG1_REG</ffdc> + <ffdc>PORE_STACK0_REG</ffdc> + <ffdc>PORE_STACK1_REG</ffdc> + <ffdc>PORE_STACK2_REG</ffdc> + <ffdc>PORE_IDFLAGS_REG</ffdc> + <ffdc>PORE_SPRG0_REG</ffdc> + <ffdc>PORE_MRR_REG</ffdc> + <ffdc>PORE_I2CE0_REG</ffdc> + <ffdc>PORE_I2CE1_REG</ffdc> + <ffdc>PORE_I2CE2_REG</ffdc> + <!-- PORE engine PC --> + <ffdc>PORE_PC</ffdc> + <!-- RC associated with SBE/SLW halt point --> + <ffdc>PORE_RC</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_SBE</rc> + <description> + SBE specific register FFDC to collect (via chip target) on all fails + </description> + <ffdc>PNOR_ECCB_STATUS</ffdc> + <ffdc>SEEPROM_ECCB_STATUS</ffdc> + <ffdc>SOFT_ERROR_STATUS</ffdc> + <ffdc>ATTN_REPORTED</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP</target> + </collectRegisterFfdc> + <collectFfdc>proc_tp_collect_dbg_data, CHIP</collectFfdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_SLW</rc> + <description> + SLW specific register FFDC to collect (via chip target) on all fails + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <target>CHIP</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + </hwpError> + <!-- *********************************************************************** --> +</hwpErrors>
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C new file mode 100644 index 000000000..7ca0ad37d --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C @@ -0,0 +1,558 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_extract_pore_engine_state.C,v 1.3 2014/08/07 15:04:41 thi Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_engine_state.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** *** +// *| +// *! TITLE : proc_extract_pore_engine_state.C +// *! DESCRIPTION : Extract PORE (SBE/SLW) engine state +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com +// *! +// *! Overview: +// *! - Dump state of SBE/SLW engine +// *! +//------------------------------------------------------------------------------ + + +#ifdef FAPIECMD + #if FAPIECMD == 1 + #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 0 + #else + #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 1 + #endif +#else + #ifdef __HOSTBOOT_MODULE + #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 1 + #else + #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 0 + #endif +#endif + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <proc_extract_pore_engine_state.H> +#include <p8_scom_addresses.H> +#include <proc_extract_sbe_rc.H> + +#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1 + #include <poreve.H> +#endif + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ +const uint32_t SLW_VITAL_PIBMEM_OFFSET = 0x12; + + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +extern "C" +{ + + +/** + * proc_extract_pore_engine_state_sbe_ffdc - Extract SBE-specific engine state + * + * @param[in] i_target - target of chip with failed SBE + * @param[out] o_pore_sbe_state - PORE SBE-specific state/FFDC content + * + * @retval fapi::ReturnCode = SUCCESS + * @retval fapi::ReturnCode = results of cfam/SCOM access + */ +fapi::ReturnCode proc_extract_pore_engine_state_sbe_ffdc( + const fapi::Target & i_target, + por_sbe_base_state & o_pore_sbe_state) +{ + // return codes + fapi::ReturnCode rc; + + FAPI_DBG("proc_extract_pore_engine_state_sbe_ffdc: Start"); + + do + { + // check cfam status register for any PIB errors + ecmdDataBufferBase cfam_status(32); + rc = fapiGetCfamRegister(i_target, CFAM_FSI_STATUS_0x00001007, cfam_status); + if (rc) + { + FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetCfamRegister (CFAM_FSI_STATUS_0x00001007)"); + break; + } + + // bit 30 indicates SBE reported attention + if (cfam_status.isBitSet(30)) + { + FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: SBE reported attention to CFAM Status register"); + o_pore_sbe_state.reported_attn = true; + } + + // check ECCB engines (I2C/LPC) for UE/CE conditions + // SLW does not use these engines to access main memory, so no need to check + rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, o_pore_sbe_state.i2cm_eccb_status); + if (rc) + { + FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetScom (PORE_ECCB_STATUS_REGISTER_READ_0x000C00002)"); + break; + } + + rc = fapiGetScom(i_target, LPC_STATUS_0x000B0002, o_pore_sbe_state.pnor_eccb_status); + if (rc) + { + FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetScom (LPC_STATUS_0x000B0002)"); + break; + } + + // determine if either engine has reached threshold of > 128 CEs + if (o_pore_sbe_state.i2cm_eccb_status.isBitSet(57)) + { + o_pore_sbe_state.soft_err = eSOFT_ERR_I2CM; + } + + if (o_pore_sbe_state.pnor_eccb_status.isBitSet(57)) + { + if (o_pore_sbe_state.soft_err == eSOFT_ERR_I2CM) + { + o_pore_sbe_state.soft_err = eSOFT_ERR_BOTH; + } + else + { + o_pore_sbe_state.soft_err = eSOFT_ERR_PNOR; + } + } + } while(0); + + FAPI_DBG("proc_extract_pore_engine_state_sbe_ffdc: End"); + return rc; +} + + +/** + * proc_extract_pore_engine_state_hw - Extract PORE engine state from HW + * + * @param[in] i_target - target of chip with failed SBE/SLW engine + * @param[in] i_engine - engine type (SBE/SLW) + * @param[out] o_vital_state - data buffer to hold SBE/SLW vital state + * @param[out] o_engine_state - data buffer to hold engine FFDC state + * + * @retval fapi::ReturnCode = SUCCESS + * @retval fapi::ReturnCode = results of cfam/SCOM access + */ +fapi::ReturnCode proc_extract_pore_engine_state_hw( + const fapi::Target & i_target, + const por_engine_t i_engine, + ecmdDataBufferBase & o_vital_state, + ecmdDataBufferBase & o_engine_state) +{ + // return codes + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; + + FAPI_DBG("proc_extract_pore_engine_state_hw: Start"); + + do + { + // collect SBE/SLW vital register value + if (i_engine == SBE) + { + ecmdDataBufferBase cfam_vital_data(32); + + // collect from SBE vital HW register + rc = fapiGetCfamRegister(i_target, CFAM_FSI_SBE_VITAL_0x0000281C, cfam_vital_data); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetCfamRegister (CFAM_FSI_SBE_VITAL_0x0000281C)"); + break; + } + + rc_ecmd |= o_vital_state.setWord(0, cfam_vital_data.getWord(0)); + rc_ecmd |= o_vital_state.setWord(1, 0x0); + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_engine_state_hw: Error %x forming SBE Vital FFDC data buffers", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + } + else + { + // collect from PIBMEM (virtual SLW vital state) + rc = fapiGetScom(i_target, + PIBMEM0_0x00080000 + SLW_VITAL_PIBMEM_OFFSET, + o_vital_state); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetCfamRegister (CFAM_FSI_SBE_VITAL_0x0000281C)"); + break; + } + } + + // collect SBE/SLW engine state + for (uint8_t offset = PORE_STATUS_OFFSET; + offset < PORE_NUM_REGS; + offset++) + { + ecmdDataBufferBase reg(64); + + rc = fapiGetScom(i_target, + (uint32_t) i_engine + offset, + reg); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetScom (0x%08X)", + (uint32_t) i_engine + offset); + break; + } + + rc_ecmd |= o_engine_state.setDoubleWord(offset, reg.getDoubleWord(0)); + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_engine_state_hw: Error %x inserting engine FFDC data value (DW=%d)", + rc_ecmd, offset); + rc.setEcmdError(rc_ecmd); + break; + } + } + if (!rc.ok()) + { + break; + } + } while(0); + + FAPI_DBG("proc_extract_pore_engine_state_hw: End"); + return rc; +} + + +/** + * proc_extract_pore_engine_state_virtual - Extract PORE engine state from virtual engine + * + * @param[in] i_target - target of chip with failed SBE engine + * @param[in] i_poreve - pointer to PoreVe object + * @param[out] o_vital_state - data buffer to hold SBE vital state + * @param[out] o_engine_state - data buffer to hold engine FFDC state + * + * @retval fapi::ReturnCode = SUCCESS + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR + */ +#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1 +fapi::ReturnCode proc_extract_pore_engine_state_virtual( + const fapi::Target & i_target, + vsbe::PoreVe * i_poreve, + ecmdDataBufferBase & o_vital_state, + ecmdDataBufferBase & o_engine_state) +{ + // return codes + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; + vsbe::ModelError me; + + FAPI_DBG("proc_extract_pore_engine_state_virtual: Start"); + + do + { + // extract SBE vital state + // - for processor chips, this should resolve to a getscom + // - for Centaur, the state should be extracted from the virtual model + uint64_t vital_data; + int pib_rc; + me = i_poreve->getscom(MBOX_SBEVITAL_0x0005001C, vital_data, pib_rc); + if (me != vsbe::ME_SUCCESS) + { + FAPI_ERR("proc_extract_pore_engine_state_virtual: Model error %x extracting SBE vital state", + (int) me); + const fapi::Target & CHIP = i_target; + const uint32_t & MODEL_ERROR = (uint32_t) me; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR); + break; + } + else if (pib_rc) + { + FAPI_ERR("proc_extract_pore_engine_state_virtual: PIB error getting SBE vital state (error code %d)", + pib_rc); + const fapi::Target & CHIP = i_target; + const int & PIB_ERROR = pib_rc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR); + break; + } + rc_ecmd = o_vital_state.setDoubleWord(0, vital_data); + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_engine_state_virtual: Error %x inserting SBE vital FFDC data value", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // extract engine state from model + vsbe::PoreState ve_state; + me = i_poreve->iv_pore.extractState(ve_state); + if (me != vsbe::ME_SUCCESS) + { + FAPI_ERR("proc_extract_pore_engine_state_virtual: Model error %x extracting virtual engine state", + (int) me); + const fapi::Target & CHIP = i_target; + const uint32_t & MODEL_ERROR = (uint32_t) me; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR); + break; + } + + uint64_t status; + ve_state.get(vsbe::PORE_STATUS, status); + uint64_t control; + ve_state.get(vsbe::PORE_CONTROL, control); + uint64_t reset; + ve_state.get(vsbe::PORE_RESET, reset); + uint64_t table_base; + ve_state.get(vsbe::PORE_TABLE_BASE_ADDR, table_base); + uint64_t ibuf0, ibuf1; + ve_state.get(vsbe::PORE_IBUF_01, ibuf0); + ve_state.get(vsbe::PORE_IBUF_2, ibuf1); + uint64_t dbg0, dbg1; + ve_state.get(vsbe::PORE_DBG0, dbg0); + ve_state.get(vsbe::PORE_DBG1, dbg1); + uint64_t stack0, stack1, stack2; + ve_state.get(vsbe::PORE_PC_STACK0, stack0); + ve_state.get(vsbe::PORE_PC_STACK1, stack1); + ve_state.get(vsbe::PORE_PC_STACK2, stack2); + uint64_t mrr; + ve_state.get(vsbe::PORE_MEM_RELOC, mrr); + uint64_t i2c_e0, i2c_e1, i2c_e2; + ve_state.get(vsbe::PORE_I2C_E0_PARAM, i2c_e0); + ve_state.get(vsbe::PORE_I2C_E1_PARAM, i2c_e1); + ve_state.get(vsbe::PORE_I2C_E2_PARAM, i2c_e2); + + rc_ecmd |= o_engine_state.setDoubleWord(PORE_STATUS_OFFSET, status); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_CONTROL_OFFSET, control); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_RESET_OFFSET, reset); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_ERR_MASK_OFFSET, i_poreve->iv_pore.emr.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_P0_OFFSET, (i_poreve->iv_pore.p0.read() << 32)); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_P1_OFFSET, (i_poreve->iv_pore.p1.read() << 32)); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_A0_OFFSET, i_poreve->iv_pore.a0.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_A1_OFFSET, i_poreve->iv_pore.a1.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_TBL_BASE_OFFSET, table_base); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_EXE_TRIGGER_OFFSET, i_poreve->iv_pore.etr.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_CTR_OFFSET, i_poreve->iv_pore.ctr.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_D0_OFFSET, i_poreve->iv_pore.d0.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_D1_OFFSET, i_poreve->iv_pore.d1.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_IBUF0_OFFSET, ibuf0); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_IBUF1_OFFSET, ibuf1); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_DEBUG0_OFFSET, dbg0); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_DEBUG1_OFFSET, dbg1); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK0_OFFSET, stack0); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK1_OFFSET, stack1); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK2_OFFSET, stack2); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_IDFLAGS_OFFSET, i_poreve->iv_pore.ifr.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_SPRG0_OFFSET, i_poreve->iv_pore.sprg0.read()); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_MRR_OFFSET, mrr); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE0_OFFSET, i2c_e0); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE1_OFFSET, i2c_e1); + rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE2_OFFSET, i2c_e2); + + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_engine_state_virtual: Error %x inserting engine FFDC data value", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + } while(0); + + FAPI_DBG("proc_extract_pore_engine_state_virtual: End"); + return rc; +} +#endif + +/** + * proc_extract_pore_engine_state - HWP entry point, extract PORE engine state + * + * @param[in] i_target - chip target, used to collect engine state if + * i_poreve is NULL + * @param[in] i_poreve - pointer to PoreVe object, used to collect engine + * state if non NULL + * @param[in] i_engine - engine type to analyze (SBE/SLW) + * @param[out] o_pore_state - PORE state/FFDC content + * @param[out] o_pore_sbe_state - PORE SBE-specific state/FFDC content (filled + * only if i_engine=SBE) + * + * @retval fapi::ReturnCode = SUCCESS + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION + */ +fapi::ReturnCode proc_extract_pore_engine_state(const fapi::Target & i_target, + void * i_poreve, + const por_engine_t i_engine, + por_base_state & o_pore_state, + por_sbe_base_state & o_pore_sbe_state) +{ + // return code + fapi::ReturnCode rc; + + do + { + // + // check arguments + // + + // virtual SBE for processor or Centaur OR + // real SBE/SLW for processor + bool is_virtual = (i_poreve != NULL); +#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1 + bool is_virtual_supported = true; + vsbe::PoreVe * ve = reinterpret_cast<vsbe::PoreVe *>(i_poreve); +#else + bool is_virtual_supported = false; +#endif + bool is_processor = (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP); + bool is_centaur = (i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP); + bool is_sbe = (i_engine == SBE); + bool is_slw = (i_engine == SLW); + + o_pore_state.target = i_target; + o_pore_state.engine = i_engine; + o_pore_state.is_virtual = is_virtual; + + if (!((is_virtual && is_virtual_supported && (is_processor || is_centaur) && is_sbe) || + (!is_virtual && is_processor && (is_sbe || is_slw)))) + { + FAPI_ERR("proc_extract_pore_engine_state: Unsupported invocation for target: %s, engine type: %s, virtual: %d", + i_target.toEcmdString(), ((i_engine == SBE)?("SBE"):("SLW")), is_virtual); + const fapi::Target & CHIP = i_target; + const por_engine_t & ENGINE = i_engine; + const bool & VIRTUAL = is_virtual; + const bool & VIRTUAL_IS_SUPPORTED = is_virtual_supported; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION); + break; + } + + + // + // extract engine state + // + + FAPI_INF("proc_extract_pore_engine_state: Extracting PORE engine FFDC for target: %s, engine type: %s, virtual: %d", + i_target.toEcmdString(), ((i_engine == SBE)?("SBE"):("SLW")), is_virtual); + + // collect engine state from virtual PORE engine + if (is_virtual) + { +#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1 + rc = proc_extract_pore_engine_state_virtual(i_target, + ve, + o_pore_state.vital_state, + o_pore_state.engine_state); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_virtual"); + break; + } +#endif + } + // HW + else + { + rc = proc_extract_pore_engine_state_hw(i_target, + i_engine, + o_pore_state.vital_state, + o_pore_state.engine_state); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_hw"); + break; + } + } + + FAPI_INF("proc_extract_pore_engine_state: PORE_VITAL = 0x%016llX", o_pore_state.vital_state.getDoubleWord(0)); + FAPI_INF("proc_extract_pore_engine_state: PORE_STATUS = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_CONTROL = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_CONTROL_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_RESET = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_RESET_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_ERR_MASK = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_ERR_MASK_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_P0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_P0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_P1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_P1_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_A0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_A0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_A1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_A1_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_TBL_BASE = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_TBL_BASE_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_EXE_TRIGGER = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_EXE_TRIGGER_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_CTR = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_CTR_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_D0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_D0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_D1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_D1_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_IBUF0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IBUF0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_IBUF1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IBUF1_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_DEBUG0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_DEBUG0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_DEBUG1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_DEBUG1_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_STACK0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_STACK1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK1_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_STACK2 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK2_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_IDFLAGS = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IDFLAGS_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_SPRG0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_SPRG0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_MRR = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_MRR_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE0_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE1_OFFSET)); + FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE2 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE2_OFFSET)); + + o_pore_state.pc = (o_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET) & 0x0000FFFFFFFFFFFFULL); + FAPI_INF("proc_extract_pore_engine_state: PORE_PC = 0x%016llX", o_pore_state.pc); + + // + // processor SBE specific state collection + // + + if (is_processor && is_sbe) + { + rc = proc_extract_pore_engine_state_sbe_ffdc(i_target, + o_pore_sbe_state); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_sbe_ffdc"); + break; + } + + FAPI_INF("proc_extract_pore_engine_state: SBE SEEPROM ECCB = %016llX", o_pore_sbe_state.i2cm_eccb_status.getDoubleWord(0)); + FAPI_INF("proc_extract_pore_engine_state: SBE PNOR ECCB = %016llX", o_pore_sbe_state.pnor_eccb_status.getDoubleWord(0)); + FAPI_INF("proc_extract_pore_engine_state: SBE soft error = %d", o_pore_sbe_state.soft_err); + FAPI_INF("proc_extract_pore_engine_state: SBE attn = %d", o_pore_sbe_state.reported_attn); + } + } while(0); + + FAPI_INF("proc_extract_pore_engine_state: End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H new file mode 100644 index 000000000..6a2b7fc42 --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H @@ -0,0 +1,97 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_extract_pore_engine_state.H,v 1.2 2014/07/24 03:16:22 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_engine_state.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** *** +// *| +// *! TITLE : proc_extract_pore_engine_state.H +// *! DESCRIPTION : Extract PORE (SBE/SLW) engine state +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_EXTRACT_PORE_ENGINE_STATE_H_ +#define _PROC_EXTRACT_PORE_ENGINE_STATE_H_ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi.H> +#include <proc_extract_sbe_rc.H> + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*proc_extract_pore_engine_state_FP_t)(const fapi::Target &, + void *, + const por_engine_t, + por_base_state &, + por_sbe_base_state &); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + + +extern "C" +{ + + +/** + * proc_extract_pore_engine_state - HWP entry point, extract PORE engine state + * + * @param[in] i_target - chip target, used to collect engine state if + * i_poreve is NULL + * @param[in] i_poreve - pointer to PoreVe object, used to collect engine + * state if non NULL + * @param[in] i_engine - engine type to analyze (SBE/SLW) + * @param[out] o_pore_state - PORE state/FFDC content + * @param[out] o_pore_sbe_state - PORE SBE-specific state/FFDC content (filled + * only if i_engine=SBE) + * + * @retval fapi::ReturnCode = SUCCESS + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR + * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION + */ +fapi::ReturnCode proc_extract_pore_engine_state(const fapi::Target & i_target, + void *, + const por_engine_t i_engine, + por_base_state & o_pore_state, + por_sbe_base_state & o_pore_sbe_state); + + +} // extern "C" + +#endif // _PROC_EXTRACT_PORE_ENGINE_STATE_H_ diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml new file mode 100644 index 000000000..711e5119e --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml @@ -0,0 +1,93 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_extract_pore_engine_state_errors.xml,v 1.2 2014/07/24 03:11:21 jmcgill Exp $ $ --> +<!-- Error definitions for proc_extract_pore_engine_state HWP --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR</rc> + <description> + Procedure: proc_extract_pore_engine_state + Virtual SBE model error occurred when attempting to access SBE vital state. + </description> + <ffdc>CHIP</ffdc> + <ffdc>MODEL_ERROR</ffdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR</rc> + <description> + Procedure: proc_extract_pore_engine_state + PIB error occurred when attempting to access SBE vital state from virtual SBE model. + </description> + <ffdc>CHIP</ffdc> + <ffdc>PIB_ERROR</ffdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP</target> + </deconfigure> + <gard> + <target>CHIP</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION</rc> + <description> + Procedure: proc_extract_pore_engine_state + Unsupported engine type presented for analysis. + </description> + <ffdc>CHIP</ffdc> + <ffdc>ENGINE</ffdc> + <ffdc>VIRTUAL</ffdc> + <ffdc>VIRTUAL_IS_SUPPORTED</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> +</hwpErrors>
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C new file mode 100644 index 000000000..aaf28f372 --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C @@ -0,0 +1,550 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_extract_pore_halt_ffdc.C,v 1.2 2014/08/07 13:32:17 thi Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_halt_ffdc.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** *** +// *| +// *! TITLE : proc_extract_pore_halt_ffdc.C +// *! DESCRIPTION : Extract halt-fail related FFDC for selected SBE/SLW errors +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p8_scom_addresses.H> +#include <proc_extract_pore_halt_ffdc.H> + + +// ----------------------------------------------------------------------------- +// Constant definitions +// ----------------------------------------------------------------------------- + +// X Clock Adjust Set register bit/field definitions +const uint32_t X_CLK_ADJ_SET_REG_SYNC_BIT = 2; +const uint32_t X_CLK_ADJ_SET_REG_RLM_SELECT_BIT = 5; +const uint32_t X_CLK_ADJ_SET_REG_CMD_START_BIT = 6; +const uint32_t X_CLK_ADJ_SET_REG_CMD_END_BIT = 9; +const uint32_t X_CLK_ADJ_SET_REG_DATA_START_BIT = 21; +const uint32_t X_CLK_ADJ_SET_REG_DATA_END_BIT = 28; + +const uint8_t X_CLK_ADJ_CMD_TYPE_READ = 0xE; + + +const uint64_t scan_ffdc_addr_arr[] = +{ + GENERIC_CLK_SYNC_CONFIG_0x00030000, + GENERIC_OPCG_CNTL0_0x00030002, + GENERIC_OPCG_CNTL1_0x00030003, + GENERIC_OPCG_CNTL2_0x00030004, + GENERIC_OPCG_CNTL3_0x00030005, + GENERIC_CLK_REGION_0x00030006, + GENERIC_CLK_SCANSEL_0x00030007, + GENERIC_CLK_STATUS_0x00030008, + GENERIC_CLK_ERROR_0x00030009, + GENERIC_CLK_SCANDATA0_0x00038000 +}; + +const uint64_t instruct_start_ffdc_addr_arr[] = +{ + EX_PERV_TCTL0_R_MODE_0x10013001, + EX_PERV_TCTL0_R_STAT_0x10013002, + EX_PERV_TCTL0_POW_STAT_0x10013004, + EX_PCNE_REG0_HOLD_OUT_0x1001300D, + EX_PERV_THREAD_ACTIVE_0x1001310E, + EX_CORE_FIR_0x10013100, + EX_SPATTN_0x10040004, + PM_SPECIAL_WKUP_FSP_0x100F010B, + PM_SPECIAL_WKUP_OCC_0x100F010C, + PM_SPECIAL_WKUP_PHYP_0x100F010D, + EX_OHA_RO_STATUS_REG_0x1002000B, + EX_OHA_MODE_REG_RWx1002000D, + EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, + EX_OHA_RO_STATUS_REG_0x1002000B, + EX_OHA_AISS_IO_REG_0x10020014, + EX_GP3_0x100F0012, + EX_PMGP0_0x100F0100, + EX_PMGP1_0x100F0103, + EX_PFET_CTL_REG_0x100F0106, + EX_PFET_STAT_REG_0x100F0107, + EX_PFET_CTL_REG_0x100F010E, + EX_PMSTATEHISTPERF_REG_0x100F0113, + EX_PCBS_FSM_MONITOR1_REG_0x100F0170, + EX_PCBS_FSM_MONITOR2_REG_0x100F0171, + EX_PMErr_REG_0x100F0109, + EX_PCBS_DPLL_STATUS_REG_100F0161, + EX_DPLL_CPM_PARM_REG_0x100F0152 +}; + +const uint64_t dpll_lock_ffdc_addr_arr[] = +{ + EX_DPLL_CPM_PARM_REG_0x100F0152, + EX_PMGP0_0x100F0100, + EX_GP3_0x100F0012 +}; + + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +extern "C" +{ + + +/** + * proc_extract_pore_halt_ffdc_unicast - collect FFDC data for one chiplet + * + * @param[in] i_target - target for FFDC collection + * @param[in] i_halt_type - FFDC type, for logging + * @param[in] i_ffdc_addrs - FFDC addresses to log + * @param[in] i_base_scom_addr - base SCOM address (XX000000) to apply + * to entries of i_ffdc_addrs_log + * @param[out] o_rc - target return code for extra FFDC + * + * @retval fapi::ReturnCode = SUCCESS + */ +fapi::ReturnCode proc_extract_pore_halt_ffdc_unicast(const fapi::Target & i_target, + const por_halt_type_t i_halt_type, + const std::vector<uint64_t> * i_ffdc_addrs, + const uint32_t i_base_scom_addr, + fapi::ReturnCode & o_rc) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; + + // FFDC collection + ecmdDataBufferBase ffdc_reg_addrs(64*(i_ffdc_addrs->size())); + ecmdDataBufferBase ffdc_reg_data(64*(i_ffdc_addrs->size())); + uint8_t dw_index = 0; + + FAPI_INF("proc_extract_pore_halt_ffdc_unicast: Start (target = %s, base = 0x%08X)", + i_target.toEcmdString(), i_base_scom_addr); + + do + { + rc_ecmd |= ffdc_reg_addrs.flushTo1(); + rc_ecmd |= ffdc_reg_data.flushTo1(); + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_unicast: Error %x flushing FFDC data buffers", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + for (std::vector<uint64_t>::const_iterator i = i_ffdc_addrs->begin(); + i != i_ffdc_addrs->end(); + i++) + { + ecmdDataBufferBase data(64); + uint32_t scom_addr = (uint32_t) (*i); + scom_addr &= 0x0FFFFFFF; + scom_addr += i_base_scom_addr; + + FAPI_DBG("proc_extract_pore_halt_ffdc_unicast: Dumping 0x%08X on %s", + scom_addr, i_target.toEcmdString()); + + // explicitly ignore return code, attempt to collect all FFDC registers + rc = fapiGetScom(i_target, scom_addr, data); + rc_ecmd |= ffdc_reg_addrs.setDoubleWord(dw_index, scom_addr); + if (rc.ok()) + { + rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, data.getDoubleWord(0)); + } + else + { + rc = fapi::FAPI_RC_SUCCESS; + } + + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_unicast: Error %x forming FFDC data buffers", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + dw_index++; + } + if (!rc.ok()) + { + break; + } + + } while(0); + + const fapi::Target & TARGET = i_target; + const por_halt_type_t & PORE_HALT_TYPE = i_halt_type; + const ecmdDataBufferBase & FFDC_ADDRESSES = ffdc_reg_addrs; + const ecmdDataBufferBase & FFDC_DATA = ffdc_reg_data; + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_HALT_FFDC); + + FAPI_INF("proc_extract_pore_halt_ffdc_unicast: End"); + return rc; +} + + +/** + * proc_extract_pore_halt_ffdc_skew_adjust - collect FFDC data for XBUS skew adjust halt + * + * @param[in] i_target - target for FFDC collection + * @param[in] i_halt_type - FFDC type, for logging + * @param[out] o_rc - target return code for extra FFDC + * + * @retval fapi::ReturnCode = SUCCESS + */ +fapi::ReturnCode proc_extract_pore_halt_ffdc_skew_adjust(const fapi::Target & i_target, + const por_halt_type_t i_halt_type, + fapi::ReturnCode & o_rc) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; + + // FFDC collection + const uint8_t READ_REGS = 16; + ecmdDataBufferBase ffdc_reg_addrs(64*READ_REGS); + ecmdDataBufferBase ffdc_reg_data(64*READ_REGS); + + FAPI_INF("proc_extract_pore_halt_ffdc_skew_adjust: Start (target = %s)", + i_target.toEcmdString()); + + for (uint8_t dw_index = 0; dw_index < READ_REGS; dw_index++) + { + ecmdDataBufferBase data(64); + bool iter_valid = true; + + // write set register with sync bit asserted + rc_ecmd |= data.setBit(X_CLK_ADJ_SET_REG_SYNC_BIT); + rc_ecmd |= data.setBit(X_CLK_ADJ_SET_REG_RLM_SELECT_BIT); + rc_ecmd |= data.insertFromRight( + X_CLK_ADJ_CMD_TYPE_READ, + X_CLK_ADJ_SET_REG_CMD_START_BIT, + (X_CLK_ADJ_SET_REG_CMD_END_BIT- + X_CLK_ADJ_SET_REG_CMD_START_BIT+1)); + rc_ecmd |= data.insertFromRight( + dw_index, + X_CLK_ADJ_SET_REG_DATA_START_BIT, + (X_CLK_ADJ_SET_REG_DATA_END_BIT- + X_CLK_ADJ_SET_REG_DATA_START_BIT+1)); + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming X CLK Adjust Set register data buffer (set)", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + rc = fapiPutScom(i_target, X_CLK_ADJ_SET_0x040F0016, data); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiPutScom (X_CLK_ADJ_SET_0x040F0016)"); + iter_valid = false; + } + + // write set register with sync bit cleared + rc_ecmd |= data.clearBit(X_CLK_ADJ_SET_REG_SYNC_BIT); + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming X CLK Adjust Set register data buffer (clear)", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + rc = fapiPutScom(i_target, X_CLK_ADJ_SET_0x040F0016, data); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiPutScom (X_CLK_ADJ_SET_0x040F0016)"); + iter_valid = false; + } + + rc = fapiGetScom(i_target, X_CLK_ADJ_DAT_REG_0x040F0015, data); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiGetScom (X_CLK_ADJ_DAT_REG_0x040F0015)"); + iter_valid = false; + } + + rc_ecmd |= ffdc_reg_addrs.setDoubleWord(dw_index, dw_index); + if (iter_valid) + { + rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, data.getDoubleWord(0)); + } + else + { + rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, 0xFFFFFFFFFFFFFFFFULL); + rc = fapi::FAPI_RC_SUCCESS; + } + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming FFDC data buffers", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + } + + const fapi::Target & TARGET = i_target; + const por_halt_type_t & PORE_HALT_TYPE = i_halt_type; + const ecmdDataBufferBase & FFDC_ADDRESSES = ffdc_reg_addrs; + const ecmdDataBufferBase & FFDC_DATA = ffdc_reg_data; + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_HALT_FFDC); + + FAPI_INF("proc_extract_pore_halt_ffdc_skew_adjust: End"); + return rc; +} + + + +/** + * proc_extract_pore_halt_ffdc - HWP entry point, log PORE fail FFDC + * + * @param[in] i_pore_state - struct holding PORE state + * @param[in] i_halt_type - FFDC type to collect + * @param[in] i_offset - offset to apply to FFDC registers for + * i_halt_type (constant/value of PORE + * pervasive base registers/none) + * @param[out] o_rc - target return code for extra FFDC + * + * @retval fapi::ReturnCode = SUCCESS + */ +fapi::ReturnCode proc_extract_pore_halt_ffdc(const por_base_state & i_pore_state, + const por_halt_type_t i_halt_type, + const por_ffdc_offset_t i_offset, + fapi::ReturnCode & o_rc) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; + + // FFDC register collection pointer + const std::vector<uint64_t> *p = NULL; + std::vector<uint64_t> scan_ffdc_addr(scan_ffdc_addr_arr, scan_ffdc_addr_arr + (sizeof(scan_ffdc_addr_arr) / sizeof(scan_ffdc_addr_arr[0]))); + std::vector<uint64_t> instruct_start_ffdc_addr(instruct_start_ffdc_addr_arr, instruct_start_ffdc_addr_arr + (sizeof(instruct_start_ffdc_addr_arr) / sizeof(instruct_start_ffdc_addr_arr[0]))); + std::vector<uint64_t> dpll_lock_ffdc_addr(dpll_lock_ffdc_addr_arr, dpll_lock_ffdc_addr_arr + (sizeof(dpll_lock_ffdc_addr_arr) / sizeof(dpll_lock_ffdc_addr_arr[0]))); + + FAPI_INF("proc_extract_pore_halt_ffdc: Start"); + + do + { + const fapi::Target & TARGET = i_pore_state.target; + const por_halt_type_t & PORE_HALT_TYPE = i_halt_type; + + if (i_halt_type == PORE_HALT_SKEW_ADJUST_FAIL) + { + FAPI_DBG("proc_extract_pore_halt_ffdc: Collecting skew adjust FFDC"); + if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP) + { + rc = proc_extract_pore_halt_ffdc_skew_adjust(i_pore_state.target, + i_halt_type, + o_rc); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_skew_adjust"); + break; + } + } + else + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE); + break; + } + } + else if (i_halt_type == PORE_HALT_FIR_FAIL) + { + FAPI_DBG("proc_extract_pore_halt_ffdc: Collecting FIR FFDC"); + if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP) + { + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_FIR_FFDC); + break; + } + else if (i_pore_state.target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP) + { + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_CEN_FIR_FFDC); + break; + } + else + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE); + break; + } + } + else + { + // set pointer based on halt type + switch (i_halt_type) + { + case PORE_HALT_SCAN_FAIL: + case PORE_HALT_SCAN_FLUSH_FAIL: + case PORE_HALT_ARRAYINIT_FAIL: + p = &(scan_ffdc_addr); + FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to scan FFDC array"); + break; + case PORE_HALT_INSTRUCT_FAIL: + p = &(instruct_start_ffdc_addr); + FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to instruction start FFDC array"); + break; + case PORE_HALT_DPLL_LOCK_FAIL: + p = &(dpll_lock_ffdc_addr); + FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to DPLL lock FFDC array"); + break; + default: + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE); + break; + } + if (!rc.ok()) + { + break; + } + + // determine chiplet ID offset to apply to FFDC registers collected + // for this halt type + uint32_t chiplet_id = i_offset; + if ((i_offset == POR_FFDC_OFFSET_USE_P0) || + (i_offset == POR_FFDC_OFFSET_USE_P1)) + { + chiplet_id = 0x0; + // chiplet addressed is stored in one of the PORE pervasive base registers + // use the value of that register to form the chiplet portion of the FFDC + // SCOM addresses + rc_ecmd |= i_pore_state.engine_state.extractPreserve( + &chiplet_id, + (64*(i_offset)) + 24, + 8, + 0); + + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_halt_ffdc: Error %x extracting P%d pervasive base content", + rc_ecmd, (i_offset == POR_FFDC_OFFSET_USE_P0)?(0):(1)); + rc.setEcmdError(rc_ecmd); + break; + } + } + + // multicast address + // only support EX multicast unrolling for processor chip targets + if (chiplet_id & 0x40000000) + { + uint8_t mc_group = (chiplet_id >> 24) & 0x3; + std::vector<fapi::Target> ex_chiplets; + + if ((i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP) && + ((mc_group == 1) || (mc_group == 2))) + { + // determine set of EX chiplets + rc = fapiGetChildChiplets(i_pore_state.target, + fapi::TARGET_TYPE_EX_CHIPLET, + ex_chiplets, + fapi::TARGET_STATE_FUNCTIONAL); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc: Error from fapiGetChildChiplets"); + break; + } + + // collect FFDC for chiplets which are part of the multicast group + for (std::vector<fapi::Target>::iterator i = ex_chiplets.begin(); + i != ex_chiplets.end(); + i++) + { + ecmdDataBufferBase mc_config_data(64); + uint64_t mc_group_addr = (mc_group == 1)?(EX_MCGR2_0x100F0002):(EX_MCGR3_0x100F0003); + uint8_t mc_group_listen; + + rc = fapiGetScom(*i, mc_group_addr, mc_config_data); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc: Error from fapiGetScom (EX_MCGR%d_0x%08llX)", + mc_group+1, mc_group_addr); + break; + } + + rc_ecmd |= mc_config_data.extractToRight(&mc_group_listen, 3, 3); + if (rc_ecmd) + { + FAPI_ERR("proc_extract_pore_halt_ffdc: Error %x extracting multicast group listen configuration", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + if (mc_group_listen == mc_group) + { + rc = proc_extract_pore_halt_ffdc_unicast(*i, i_halt_type, p, 0x10000000, o_rc); + if (!rc.ok()) + { + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_unicast"); + break; + } + } + } + else + { + FAPI_INF("proc_extract_pore_halt_ffdc: Skipping %s, not part of multicast group", + i->toEcmdString()); + } + } + if (!rc.ok()) + { + break; + } + } + else + { + FAPI_ERR("proc_extract_halt_ffdc: Unsupported multicast extraction for target: %s, group: %d", + i_pore_state.target.toEcmdString(), mc_group); + const uint8_t & CHIPLET_ID = chiplet_id; + const uint8_t & MC_GROUP = mc_group; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_MULTICAST); + break; + } + } + // unicast address + else + { + rc = proc_extract_pore_halt_ffdc_unicast(i_pore_state.target, i_halt_type, p, chiplet_id, o_rc); + if (!rc.ok()) + { + FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_unicast"); + break; + } + } + } + } while(0); + + FAPI_INF("proc_extract_pore_halt_ffdc: End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H new file mode 100644 index 000000000..1e9d4e2d3 --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H @@ -0,0 +1,88 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_extract_pore_halt_ffdc.H,v 1.1 2014/07/23 19:38:06 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_halt_ffdc.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** *** +// *| +// *! TITLE : proc_extract_pore_halt_ffdc.C +// *! DESCRIPTION : Extract SBE/SLW halt-fail related FFDC +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_EXTRACT_PORE_HALT_FFDC_H_ +#define _PROC_EXTRACT_PORE_HALT_FFDC_H_ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi.H> +#include <proc_extract_sbe_rc.H> + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*proc_extract_pore_halt_ffdc_FP_t)(const por_base_state &, + const por_halt_type_t, + const por_ffdc_offset_t, + fapi::ReturnCode &); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + + +extern "C" +{ + +/** + * proc_extract_pore_halt_ffdc - HWP entry point, log PORE fail FFDC + * + * @param[in] i_pore_state - struct holding PORE state + * @param[in] i_halt_type - FFDC type to collect + * @param[in] i_offset - offset to apply to FFDC registers for + * i_halt_type (constant/value of PORE + * pervasive base registers/none) + * @param[out] o_rc - target return code for extra FFDC + * + * @retval fapi::ReturnCode = SUCCESS + */ +fapi::ReturnCode proc_extract_pore_halt_ffdc(const por_base_state & i_pore_state, + const por_halt_type_t i_halt_type, + const por_ffdc_offset_t i_offset, + fapi::ReturnCode & o_rc); + +} // extern "C" + +#endif // _PROC_EXTRACT_PORE_HALT_FFDC_H_ diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml new file mode 100644 index 000000000..99afc14dc --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml @@ -0,0 +1,59 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2014 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_extract_pore_halt_ffdc.xml,v 1.1 2014/07/23 19:43:18 jmcgill Exp $ --> +<!-- Error definitions for proc_extract_pore_halt_ffdc procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_HALT_FFDC</rc> + <description> + FFDC collected on selected PORE engine halt failures + </description> + <ffdc>TARGET</ffdc> + <ffdc>PORE_HALT_TYPE</ffdc> + <ffdc>FFDC_ADDRESSES</ffdc> + <ffdc>FFDC_DATA</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_MULTICAST</rc> + <description> + Unsupported multicast analysis requested + </description> + <ffdc>TARGET</ffdc> + <ffdc>CHIPLET_ID</ffdc> + <ffdc>MC_GROUP</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE</rc> + <description> + Unsupported halt type analysis requested + </description> + <ffdc>TARGET</ffdc> + <ffdc>PORE_HALT_TYPE</ffdc> + </hwpError> + <!-- *********************************************************************** --> +</hwpErrors>
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C index d4151fa40..aefae9a5f 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C @@ -22,19 +22,19 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_extract_sbe_rc.C,v 1.18 2014/06/30 14:32:05 bgeukes Exp $ +// $Id: proc_extract_sbe_rc.C,v 1.20 2014/07/24 03:13:59 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.C,v $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2012 // *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** +// *! *** *** // *| // *! TITLE : proc_extract_sbe_rc.C -// *! DESCRIPTION : Create a return code for an SBE/SLW error +// *! DESCRIPTION : Create return code for PORE (SBE/SLW) error // *! -// *! OWNER NAME : Johannes Koesters Email: koesters@de.ibm.com +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com // *! // *! Overview: // *! - Analyze error state of SBE/SLW engine @@ -53,44 +53,26 @@ //------------------------------------------------------------------------------ #include <proc_extract_sbe_rc.H> #include <proc_reset_i2cm_bus_fence.H> -#include <p8_scom_addresses.H> -#include <proc_tp_collect_dbg_data.H> +#include <proc_extract_pore_engine_state.H> +#include <proc_extract_pore_base_ffdc.H> +#include <proc_extract_pore_halt_ffdc.H> //------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -enum soft_error_t -{ - eNO_ERROR = 0, - eSOFT_ERR_I2CM=1, - eSOFT_ERR_PNOR=2, - eSOFT_ERR_BOTH=3 -}; - -//------------------------------------------------------------------------------ // Constant definitions //------------------------------------------------------------------------------ -// address space/alignment masks -const uint64_t SBE_ADDR_MASK = 0x0000FFFFFFFFFFFFULL; -const uint64_t FOURBYTE_ALIGNMENT_MASK = 0x0000000000000003ULL; +// address space masks +const uint64_t PORE_ADDR_MASK = 0x0000FFFFFFFFFFFFULL; const uint64_t INTERNAL_ADDR_MASK = 0x000000007FFFFFFFULL; const uint64_t ADDR_TYPE_MASK = 0x0000FFFF80000000ULL; const uint64_t OTPROM_ADDR_TYPE = 0x0000000100000000ULL; const uint64_t PIBMEM_ADDR_TYPE = 0x0000000800000000ULL; const uint64_t SEEPROM_ADDR_TYPE = 0x0000800C80000000ULL; -const uint32_t ALIGN_FOUR_BYTE = 0xFFFFFFFC; - -// common SCOM register offsets for SBE/SLW engines -const uint32_t STATUS_OFFSET_0x00 = 0x00000000; -const uint32_t IBUF_OFFSET_0x0D = 0x0000000D; -const uint32_t DEBUG0_OFFSET_0x0F = 0x0000000F; -const uint32_t DEBUG1_OFFSET_0x10 = 0x00000010; +const uint64_t SLW_ADDR_TYPE = 0x0000800080000000ULL; // illegal instruction encoding for SW detected halt -const uint32_t HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' << 8) | ('t')); +const uint32_t PORE_HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' << 8) | ('t')); //------------------------------------------------------------------------------ @@ -100,506 +82,211 @@ const uint32_t HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' < extern "C" { -//------------------------------------------------------------------------------ -// subroutine: -// reads the word at the given address in SEEPROM pointer -// -// parameters: i_target => target of chip with failed SBE/SLW engine -// i_pSEEPROM => pointer to a memory-mapped SEEPROM image -// i_address => SEEPROM address to read -// i_engine => type of engine that failed (SBE/SLW) -// i_soft_err => engine soft error status, for FFDC -// o_data => return data -// -// returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_extract_sbe_rc_read_SEEPROM(const fapi::Target & i_target, - const void * i_pSEEPROM, - const uint32_t i_address, - const por_engine_t i_engine, - const soft_error_t i_soft_err, - uint32_t & o_data) -{ - // return codes - fapi::ReturnCode rc; - - do - { - if (i_pSEEPROM == NULL) - { - FAPI_ERR("Need to extract SEEPROM address 0x%08X, but pointer to SEEPROM image content is NULL", i_address); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint32_t & PC = i_address; - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = i_soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW); - } - break; - } - // copy the data out of the image pointer - uint8_t * p_errorCode = (uint8_t *)i_pSEEPROM + (i_address & ALIGN_FOUR_BYTE); - o_data = - (p_errorCode[0] << 3*8) | - (p_errorCode[1] << 2*8) | - (p_errorCode[2] << 1*8) | - (p_errorCode[3]); - } while(0); - - return rc; -} - - -//------------------------------------------------------------------------------ -// subroutine: -// Returns the PC of the given engine -// -// parameters: i_target => target of chip with failed SBE/SLW engine -// i_engine => type of engine that failed (SBE/SLW) -// i_soft_err => engine soft error status, for FFDC -// o_pc => referenee to the uint64_t containing the PC -// -// returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_extract_sbe_rc_get_pc(const fapi::Target & i_target, - const por_engine_t i_engine, - const soft_error_t i_soft_err, - uint64_t & o_pc) -{ - // return codes - fapi::ReturnCode rc; - - // data buffer to hold register values - ecmdDataBufferBase data(64); - - do - { - // read PC from the Status Register - rc = fapiGetScom(i_target, i_engine + STATUS_OFFSET_0x00, data); - if (rc) - { - FAPI_ERR("Error from fapiGetScom (STATUS_REG_0x%08X)", i_engine + STATUS_OFFSET_0x00); - break; - } - - o_pc = (data.getDoubleWord(0) & SBE_ADDR_MASK); - - if (o_pc & FOURBYTE_ALIGNMENT_MASK) - { - FAPI_ERR("Address isn't 4-byte aligned"); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = o_pc; - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = i_soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW); - } - break; - } - } while(0); - - return rc; -} - - -//------------------------------------------------------------------------------ -// subroutine: -// Returns the return code indicated by the PC of the engine -// -// parameters: i_target => target of chip with failed SBE/SLW engine -// i_pSEEPROM => pointer to a memory-mapped SEEPROM image -// i_engine => type of engine that failed (SBE/SLW) -// i_soft_err => engine soft error status, for FFDC -// -// returns: fapi::ReturnCode with the error -// This procedure will NEVER return SUCCESS -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_extract_sbe_rc_from_address(const fapi::Target & i_target, - const void * i_pSEEPROM, - const por_engine_t i_engine, - const soft_error_t i_soft_err) -{ - // return codes - fapi::ReturnCode rc; - - // data buffer to hold register values - ecmdDataBufferBase data(64); - uint64_t address_64; - - do - { - // read PC - rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, i_soft_err, address_64); - if (rc) - { - FAPI_ERR("Error from proc_extract_sbe_rc_get_pc"); - break; - } - - // add 4 because address_64 is pointing at the halt instruction - uint32_t internal_address = (uint32_t)(address_64 & INTERNAL_ADDR_MASK) + 4; - // error code to emit - uint32_t error_code = 0; - - if ((address_64 & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE) - { - // get the error code from that location in the SEEPROM image - FAPI_INF("Extracting the error code from address " - "0x%X in the SEEPROM", internal_address); - - rc = proc_extract_sbe_rc_read_SEEPROM(i_target, i_pSEEPROM, internal_address, i_engine, i_soft_err, error_code); - if (rc) - { - FAPI_ERR("Error from proc_extract_sbe_rc_read_SEEPROM (address = 0x%08X)", internal_address); - break; - } - } - else if ((address_64 & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE) - { - // get the error code from that location in the PIBMEM - FAPI_INF("Extracting the error code from address " - "0x%X in the PIBMEM", internal_address); - - rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (internal_address >>3), data); - if (rc) - { - FAPI_ERR("Error from fapiGetScom (PIBMEM address 0x%08X)", (uint32_t)PIBMEM0_0x00080000 + (internal_address >>3)); - break; - } - - error_code = data.getWord((internal_address & 0x04)?1:0); - } - else - { - FAPI_ERR("Address (0x%012llX) isn't in a known memory address space", address_64); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = address_64; - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = i_soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW); - } - break; - } - - // look up specified error code - FAPI_ERR("SBE got error code 0x%06X", error_code); - const fapi::Target CHIP_IN_ERROR = i_target; - const fapi::Target CHIP = i_target; - FAPI_SET_SBE_ERROR(rc, error_code); - } while(0); - - //Make sure the code doesn't return SUCCESS - if (rc.ok()) - { - FAPI_ERR("proc_extract_sbe_rc_from_addr tried to return SUCCESS," - " which should be impossible. Must be a code bug."); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = address_64; - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = i_soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW); - } - } - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Return an RC indicating the SBE/SLW error -// -// parameters: i_target => Target of chip with failed SBE/SLW -// i_pSEEPROM => pointer to a memory-mapped SEEPROM image -// i_engine => The type of engine that failed (SBE/SLW) -// -// returns: fapi::ReturnCode with the error -// This procedure will NEVER return SUCCESS -//------------------------------------------------------------------------------ +/** + * proc_extract_sbe_rc - HWP entry point, return RC indicating SBE/SLW error + * + * @param[in] i_target - target of chip with failed SBE/SLW engine + * @param[in] i_poreve - pointer to PoreVe object, used to collect engine + * state if non NULL + * @param[in] i_image - pointer to memory-mapped PORE image + * @param[in] i_engine - type of engine that failed (SBE/SLW) + * + * @retval fapi::ReturnCode - The error code the SBE hit, or the error hit + * while trying to get the error code + */ fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target, - const void * i_pSEEPROM, - const por_engine_t i_engine) + void * i_poreve, + const void * i_image, + const por_engine_t i_engine) { // return codes fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; - // data buffer to hold register values - ecmdDataBufferBase data(64); - ecmdDataBufferBase pnor_eccb_status(64); - ecmdDataBufferBase i2cm_eccb_status(64); - ecmdDataBufferBase fsi_data(32); - ecmdDataBufferBase sbe_data0(64); - ecmdDataBufferBase sbe_data1(64); - - // PC value - uint64_t pc = 0x0ULL; - - // SBE PNOR/SEEPROM soft error status - soft_error_t soft_err = eNO_ERROR; + // common state for analysis/FFDC + const fapi::Target & CHIP = i_target; + por_base_state pore_state; + // SBE specific state for analysis/FFDC + por_sbe_base_state pore_sbe_state; - // SBE attn status - bool sbe_reported_attn = false; + // process arguments + bool is_processor = (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP); + bool is_sbe = (i_engine == SBE); + bool is_slw = (i_engine == SLW); do { - // check engine type - if ((i_engine != SBE) && - (i_engine != SLW)) + // + // all engine types -- extract engine state + // + + FAPI_INF("proc_extract_sbe_rc: Processing PORE engine for target: %s, engine type: %s, virtual: %d", + i_target.toEcmdString(), + ((i_engine == SBE)?("SBE"):("SLW")), + (i_poreve == NULL)?(0):(1)); + + FAPI_EXEC_HWP(rc, proc_extract_pore_engine_state, + i_target, i_poreve, i_engine, pore_state, pore_sbe_state); + if (!rc.ok()) { - FAPI_ERR("Unknown engine type %i", i_engine); - const fapi::Target & CHIP_IN_ERROR = i_target; - const por_engine_t ENGINE = i_engine; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE); + FAPI_ERR("proc_extract_sbe_rc: Error from proc_extract_pore_engine_state"); break; } - FAPI_INF("Processing %s error", ((i_engine == SBE)?("SBE"):("SLW"))); - // if analyzing SBE engine failure - // - make sure I2C master bus fence is released before proceeding - // - check ECCB engines (I2C/LPC) for UE/CE conditions (SLW does not use - // these engines, so no need to check) - if (i_engine == SBE) + // + // processor SBE -- return SEEPROM/PNOR UE as highest priority callouts + // + + if (is_processor && is_sbe) { + // ensure I2C master bus fence is released before proceeding FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target); if (!rc.ok()) { - FAPI_ERR("Error from proc_reset_i2cm_bus_fence"); - break; - } - - // check on FSI 1007 for any PIB Access Error - rc = fapiGetCfamRegister(i_target, CFAM_FSI_STATUS_0x00001007, fsi_data); - if (rc) - { - FAPI_ERR("Error from fapiGetCfamRegister (CFAM_FSI_STATUS_0x00001007)"); + FAPI_ERR("proc_extract_sbe_rc: Error from proc_reset_i2cm_bus_fence"); break; } - if (fsi_data.getNumBitsSet(17,3) != 0) - { - FAPI_ERR("Error during PIB Access"); - const fapi::Target & CHIP_IN_ERROR = i_target; - const ecmdDataBufferBase & FSI_STATUS = fsi_data; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE); - break; - } - - if (fsi_data.isBitSet(30)) - { - FAPI_ERR("SELFBOOT_ENGINE_ATTENTION - SBE reported attention to FSI2PIB status register"); - sbe_reported_attn = true; - } - - // check on ECCB Error for I2C engine - rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, i2cm_eccb_status); - if (rc) + // return error if either ECCB engine reports an unrecoverable ECC error + if (pore_sbe_state.i2cm_eccb_status.isBitClear(41,2) && pore_sbe_state.i2cm_eccb_status.isBitSet(43)) { - FAPI_ERR("Error from fapiGetScom (PORE_ECCB_STATUS_REGISTER_READ_0x000C00002)"); + FAPI_ERR("proc_extract_sbe_rc: SBE encountered Unrecoverable ECC error on I2C Access"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_SEEPROM); break; } - // check on ECCB Engine for PNOR Access - rc = fapiGetScom(i_target, LPC_STATUS_0x000B0002, pnor_eccb_status); - if (rc) + if (pore_sbe_state.pnor_eccb_status.isBitClear(41,2) && pore_sbe_state.pnor_eccb_status.isBitSet(43)) { - FAPI_ERR("Error from fapiGetScom (LPC_STATUS_0x000B0002)"); + FAPI_ERR("proc_extract_sbe_rc: SBE encountered Unrecoverable ECC error on PNOR Access"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR); break; } - - // determine if either engine has reached threshold of > 128 CEs - if (i2cm_eccb_status.isBitSet(57)) - { - soft_err = eSOFT_ERR_I2CM; - } - - if (pnor_eccb_status.isBitSet(57)) - { - if (soft_err == eSOFT_ERR_I2CM) - { - soft_err = eSOFT_ERR_BOTH; - } - else - { - soft_err = eSOFT_ERR_PNOR; - } - } } - // read engine PC value - rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, soft_err, pc); - if (rc) - { - FAPI_ERR("Error from proc_extract_sbe_rc_get_pc"); - break; - } - if (i_engine == SBE) - { - // return error if either engine reports an unrecoverable ECC error - if (i2cm_eccb_status.isBitClear(41,2) && i2cm_eccb_status.isBitSet(43)) - { - FAPI_ERR("Unrecoverable ECC error on I2C Access"); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; - const ecmdDataBufferBase & ECCB_STATUS = i2cm_eccb_status; - const soft_error_t & SOFT_ERR_STATUS = soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE); - break; - } - - if (pnor_eccb_status.isBitClear(41,2) && pnor_eccb_status.isBitSet(43)) - { - FAPI_ERR("Unrecoverable ECC error on PNOR Access"); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; - const ecmdDataBufferBase & ECCB_STATUS = pnor_eccb_status; - const soft_error_t & SOFT_ERR_STATUS = soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE); - break; - } - } // if (i_engine == SBE) + // + // all engine types -- process PORE Debug0/Debug1 registers for HW detected/SW generated errors + // + ecmdDataBufferBase pore_debug0_reg; + ecmdDataBufferBase pore_debug1_reg; - // read Debug1 register state, check for any HW error - rc = fapiGetScom(i_target, i_engine + DEBUG1_OFFSET_0x10, sbe_data1); - if (rc) + rc_ecmd |= pore_state.engine_state.extractToRight(pore_debug0_reg, 64*PORE_DEBUG0_OFFSET, 64); + rc_ecmd |= pore_state.engine_state.extractToRight(pore_debug1_reg, 64*PORE_DEBUG1_OFFSET, 64); + if (rc_ecmd) { - FAPI_ERR("Error from fapiGetScom (DEBUG1_REG_0x%08X)", i_engine + DEBUG1_OFFSET_0x10); + FAPI_ERR("proc_extract_sbe_rc: Error %x extracting PORE engine debug register state", rc_ecmd); + rc.setEcmdError(rc_ecmd); break; } - if (sbe_data1.isBitSet(63)) // SBE ANYERROR + // any HW error will cause DBG_LOCK bit to be set + if (pore_debug1_reg.isBitSet(63)) { - FAPI_ERR("PIBMS_DBG_LOCK - error set"); - - // read Debug0 register state - rc = fapiGetScom(i_target, i_engine + DEBUG0_OFFSET_0x0F, sbe_data0); - if (rc) - { - FAPI_ERR("Error from fapiGetScom (DEBUG0_REG_0x%08X)", i_engine + DEBUG0_OFFSET_0x0F); - break; - } + FAPI_ERR("proc_extract_sbe_rc: PIBMS_DBG_LOCK - error set"); // print bitwise messages for error log, unique errors will be grouped/combined into callouts below - // grouping is done per guideance provided by Andreas Koenig - if (sbe_data1.isBitSet(48)) + // grouping is done per guidance provided by Andreas Koenig + if (pore_debug1_reg.isBitSet(48)) { - FAPI_ERR("OCI_DATA_READ_P_ERR - Parity error in read data from OCI"); + FAPI_ERR("proc_extract_sbe_rc: ERR_DATA_READ_P_ERR - Parity error in read data from OCI"); } - uint8_t oci_rc = (sbe_data0.getByte(7) >> 5) & 0x7; + uint8_t oci_rc = (pore_debug0_reg.getByte(7) >> 5) & 0x7; if (oci_rc) { - FAPI_ERR("Last return code from OCI SBE got return code %i", oci_rc); + FAPI_ERR("proc_extract_sbe_rc: Last return code from OCI received return code %i", oci_rc); } - if (sbe_data1.isBitSet(52)) + if (pore_debug1_reg.isBitSet(52)) { - FAPI_ERR("BAD_PAR - bad instruction parity"); + FAPI_ERR("proc_extract_sbe_rc: BAD_PAR - bad instruction parity"); } - if (sbe_data1.isBitSet(53)) + if (pore_debug1_reg.isBitSet(53)) { - FAPI_ERR("BAD_INSTRUCTION - invalid instruction"); + FAPI_ERR("proc_extract_sbe_rc: BAD_INSTRUCTION - invalid instruction"); } - if (sbe_data1.isBitSet(54)) + if (pore_debug1_reg.isBitSet(54)) { - FAPI_ERR("BAD_PC - PC overflow/underflow"); + FAPI_ERR("proc_extract_sbe_rc: BAD_PC - PC overflow/underflow"); } - if (sbe_data1.isBitSet(55)) + if (pore_debug1_reg.isBitSet(55)) { - FAPI_ERR("SCAN_DATA_CRC - Scan data CRC error"); + FAPI_ERR("proc_extract_sbe_rc: SCAN_DATA_CRC - Scan data CRC error"); } - if (sbe_data1.isBitSet(56)) + if (pore_debug1_reg.isBitSet(56)) { - FAPI_ERR("PC_STACK_ERR - PC stack PUSH error or POP error"); + FAPI_ERR("proc_extract_sbe_rc: PC_STACK_ERR - PC stack PUSH error or POP error"); } - if (sbe_data1.isBitSet(57)) + if (pore_debug1_reg.isBitSet(57)) { - FAPI_ERR("INSTR_FETCH_ERROR - Non-zero return code or read sbe_data1 parity error was received when during fetch - phase"); + FAPI_ERR("proc_extract_sbe_rc: INSTR_FETCH_ERROR - Non-zero return code or read DEBUG1 parity error was received when during fetch phase"); } - if (sbe_data1.isBitSet(58)) + if (pore_debug1_reg.isBitSet(58)) { - FAPI_ERR("BAD_OPERAND - Invalid Instruction Operand"); + FAPI_ERR("proc_extract_sbe_rc: BAD_OPERAND - Invalid Instruction Operand"); } - if (sbe_data1.isBitSet(59)) + if (pore_debug1_reg.isBitSet(59)) { - FAPI_ERR("BAD_INSTRUCTION_PATH - Invalid Instruction Path (e.g. FI2C parameter miss)"); + FAPI_ERR("proc_extract_sbe_rc: BAD_INSTRUCTION_PATH - Invalid Instruction Path (e.g. FI2C parameter miss)"); } - if (sbe_data1.isBitSet(60)) + if (pore_debug1_reg.isBitSet(60)) { - FAPI_ERR("BAD_START_VECTOR_TRIGGER - Invalid Start Vector triggered"); + FAPI_ERR("proc_extract_sbe_rc: BAD_START_VECTOR_TRIGGER - Invalid Start Vector triggered"); } - if (sbe_data1.isBitSet(61)) + if (pore_debug1_reg.isBitSet(61)) { - FAPI_ERR("FI2C_PROTOCOL_HANG - Fast I2C protocol hang detected - exceeded poll limit for FI2C engine"); + FAPI_ERR("proc_extract_sbe_rc: FI2C_PROTOCOL_HANG - Fast I2C protocol hang detected - exceeded poll limit for FI2C engine"); } - if (sbe_data1.isBitSet(62)) + if (pore_debug1_reg.isBitSet(62)) { - FAPI_ERR("ROL_INVALID - rotate invalid"); + FAPI_ERR("proc_extract_sbe_rc: ROL_INVALID - rotate invalid"); } - - if (sbe_data0.isBitSet(32)) + if (pore_debug0_reg.isBitSet(32)) { - FAPI_ERR("PIB_DATA_READ_P_ERR - Parity error in read data from PRV PIB"); + FAPI_ERR("proc_extract_sbe_rc: PIB_DATA_READ_P_ERR - Parity error in read data from PRV PIB"); } - uint8_t pcb_error = (sbe_data0.getByte(4) >> 4) & 0x7; - uint32_t scom_address = sbe_data0.getWord(0); + uint8_t pcb_error = (pore_debug0_reg.getByte(4) >> 4) & 0x7; + uint32_t scom_address = pore_debug0_reg.getWord(0); if (pcb_error) { - FAPI_ERR("SBE got PCB error %i accessing scom address 0x%08X", pcb_error, scom_address); + FAPI_ERR("proc_extract_sbe_rc: PORE engine got PCB error %i accessing scom address 0x%08X", pcb_error, scom_address); } - if (sbe_data0.isBitSet(36)) + if (pore_debug0_reg.isBitSet(36)) { - FAPI_ERR("I2C_BAD_STATUS_0 - I2CM internal errors including parity errors"); + FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_0 - I2CM internal errors including parity errors"); } - if (sbe_data0.isBitSet(37)) + if (pore_debug0_reg.isBitSet(37)) { - FAPI_ERR("I2C_BAD_STATUS_1 - bad PIB response code error for ECCAX to I2CM communication"); + FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_1 - bad PIB response code error for ECCAX to I2CM communication"); } - if (sbe_data0.isBitSet(38)) + if (pore_debug0_reg.isBitSet(38)) { - FAPI_ERR("I2C_BAD_STATUS_2 - ECCAX internal errors (UCE or PIB master resets)"); + FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_2 - ECCAX internal errors (UCE or PIB master resets)"); } - if (sbe_data0.isBitSet(39)) + if (pore_debug0_reg.isBitSet(39)) { - FAPI_ERR("I2C_BAD_STATUS_3 - I2C bus issues (I2C bus busy, NACK, stop bit error)"); + FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_3 - I2C bus issues (I2C bus busy, NACK, stop bit error)"); } - if (sbe_data0.isBitSet(40)) + if (pore_debug0_reg.isBitSet(40)) { - FAPI_ERR("GROUP_PARITY_ERROR_0 - parity error from debug or status or error mask or pc stack regs"); + FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_0 - parity error from DEBUG or STATUS or ERROR MASK or PC STACK regs"); } - if (sbe_data0.isBitSet(41)) + if (pore_debug0_reg.isBitSet(41)) { - FAPI_ERR("GROUP_PARITY_ERROR_1 - parity error from control or exe trigger or exe t_mask or i2c param regs"); + FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_1 - parity error from CONTROL or EXE TRIGGER or EXE T_MASK or I2C PARAM regs"); } - if (sbe_data0.isBitSet(42)) + if (pore_debug0_reg.isBitSet(42)) { - FAPI_ERR("GROUP_PARITY_ERROR_2 - parity error from perv/oci base addr or table base addr or memory reloc"); + FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_2 - parity error from PERV/OCI BASE ADDR or TABLE BASE ADDR or MEMORY RELOC regs"); } - if (sbe_data0.isBitSet(43)) + if (pore_debug0_reg.isBitSet(43)) { - FAPI_ERR("GROUP_PARITY_ERROR_3 - parity error from scr0 or scr1 or scr2 or sbe_data0 scr0 reg"); + FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_3 - parity error from SCR0 or SCR1 or SCR2 or DEBUG0 SCR0 reg"); } - if (sbe_data0.isBitSet(44)) + if (pore_debug0_reg.isBitSet(44)) { - FAPI_ERR("GROUP_PARITY_ERROR_4 - parity error from ibuf regs"); + FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_4 - parity error from IBUF regs"); } // @@ -607,237 +294,242 @@ fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target, // // "Internal Error" bucket (Error Event 3) - if ((sbe_data0.getNumBitsSet(40,5) != 0) || sbe_data1.isBitSet(55)) - { - FAPI_ERR("Internal %s Error", ((i_engine == SBE)?("SBE"):("SLW"))); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; - const uint8_t & GROUP_PARITY_ERROR_0_4 = (sbe_data0.getByte(5) >> 3) & 0x1F; - const bool & SCAN_DATA_CRC_ERROR = sbe_data1.isBitSet(55); - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW); - } + if ((pore_debug0_reg.getNumBitsSet(40,5) != 0) || pore_debug1_reg.isBitSet(55)) + { + FAPI_ERR("proc_extract_sbe_rc: Internal Error (Event 3)"); + const uint8_t & GROUP_PARITY_ERROR_0_4 = (pore_debug0_reg.getByte(5) >> 3) & 0x1F; + const bool & SCAN_DATA_CRC_ERROR = pore_debug1_reg.isBitSet(55); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR); break; } // "I2C Error" bucket (Error Event 0) - if ((sbe_data0.getNumBitsSet(36,4) != 0) || (sbe_data1.isBitSet(61))) + if ((pore_debug0_reg.getNumBitsSet(36,4) != 0) || (pore_debug1_reg.isBitSet(61))) { - FAPI_ERR("%s failed I2C Master operation", ((i_engine == SBE)?("SBE"):("SLW"))); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; - const uint8_t & I2C_BAD_STATUS_0_3 = sbe_data0.getHalfWord(10); - const bool & FI2C_HANG = sbe_data1.isBitSet(61); - - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW); - } + FAPI_ERR("proc_extract_sbe_rc: I2C Error (Event 0)"); + const uint8_t & I2C_BAD_STATUS_0_3 = pore_debug0_reg.getHalfWord(10); + const bool & FI2C_HANG = pore_debug1_reg.isBitSet(61); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR); break; } - // "SCOM Error" bucket (Error Event 0), raise in presence of no instruction execution error - if ((sbe_data0.getNumBitsSet(32,4) != 0) && (sbe_data1.getNumBitsSet(52,9) == 0) && (sbe_data1.isBitClear(62))) + // "SCOM Error" bucket (Error Event 0), raise only if no instruction execution error is present + if ((pore_debug0_reg.getNumBitsSet(32,4) != 0) && (pore_debug1_reg.getNumBitsSet(52,9) == 0) && (pore_debug1_reg.isBitClear(62))) { - FAPI_ERR("%s failed SCOM operation", ((i_engine == SBE)?("SBE"):("SLW"))); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; + FAPI_ERR("proc_extract_sbe_rc: SCOM operation failed (Event 0)"); const uint32_t & SCOM_ADDRESS = scom_address; const uint8_t & PIB_ERROR_CODE = pcb_error; - const bool & PIB_DATA_READ_PARITY_ERROR = sbe_data0.isBitSet(32); - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW); - } + const bool & PIB_DATA_READ_PARITY_ERROR = pore_debug0_reg.isBitSet(32); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR); break; } // "OCI Error" bucket (Error Event 1) - if ((i_engine == SLW) && (sbe_data1.getNumBitsSet(48,4) != 0)) + if (is_slw && (pore_debug1_reg.getNumBitsSet(48,4) != 0)) { - FAPI_ERR("%s failed OCI Master operation", ((i_engine == SBE)?("SBE"):("SLW"))); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; + FAPI_ERR("proc_extract_sbe_rc: OCI Master operation failed (Event 1)"); const uint8_t & OCI_ERROR_CODE = oci_rc; - const bool & OCI_DATA_READ_PARITY_ERROR = sbe_data1.isBitSet(48); - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW); + const bool & OCI_DATA_READ_PARITY_ERROR = pore_debug1_reg.isBitSet(48); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_OCI_ERROR); break; } - // check for the execution of an invalid instruction - // if present, check if the SBE stopped at a code detected error (instruction = 'halt') - if (sbe_data1.isBitSet(53) || sbe_data1.isBitSet(62)) + // check for PORE code generated halt + // code detected errors will result in the the execution of an invalid instruction -> ASCII 'halt' + if (pore_debug1_reg.isBitSet(53) || pore_debug1_reg.isBitSet(62)) { - rc = fapiGetScom(i_target, i_engine + IBUF_OFFSET_0x0D, data); - if (rc) + // check alignment of PC value + if (pore_state.pc & 0x3ULL) { - // fail through to "Instruction Execution Error" bucket below - FAPI_ERR("Error from fapiGetScom(IBUF_REG_0x%08X)", i_engine + IBUF_OFFSET_0x0D); - FAPI_ERR("SBE reported an invalid instruction error, but unable to determine if it was a code-detected error or not"); + FAPI_ERR("proc_extract_sbe_rc: Unexpected address alignment"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED); + break; } - else + + // examine first word of IBUF register + uint32_t instruction = pore_state.engine_state.getWord(2*PORE_IBUF0_OFFSET); + if (instruction == PORE_HALT_WITH_ERROR_INSTRUCTION) { - // lookup return code identifying halt from image, based on PC value - const uint32_t instruction = data.getWord(0); - if (instruction == HALT_WITH_ERROR_INSTRUCTION) - { - rc = proc_extract_sbe_rc_from_address(i_target, i_pSEEPROM, i_engine, soft_err); - break; - } + // halt encountered + // RC indicating unique exit point will be contained in next word + // retrieve RC from appropriate memory space + uint64_t rc_addr = (pore_state.pc & INTERNAL_ADDR_MASK)+4; + + if ((is_processor && + (((pore_state.pc & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE) || + ((pore_state.pc & ADDR_TYPE_MASK) == SLW_ADDR_TYPE))) || + (!is_processor)) + { + if (i_image == NULL) + { + FAPI_ERR("proc_extract_sbe_rc: PORE image pointer is NULL"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL); + break; + } + + FAPI_INF("proc_extract_sbe_rc: Extracting the error code from address 0x%llX in PORE image", rc_addr); + uint8_t * p_errorCode = (uint8_t *) i_image + rc_addr; + pore_state.rc = + (p_errorCode[0] << 3*8) | + (p_errorCode[1] << 2*8) | + (p_errorCode[2] << 1*8) | + (p_errorCode[3]); + } + else if (is_processor && ((pore_state.pc & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE)) + { + FAPI_INF("proc_extract_sbe_rc: Extracting the error code from address 0x%llX in the PIBMEM", rc_addr); + ecmdDataBufferBase pibmem_data(64); + rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (rc_addr >>3), pibmem_data); + if (rc) + { + FAPI_ERR("proc_extract_sbe_rc: Error from fapiGetScom (PIBMEM address 0x%08X)", (uint32_t) (PIBMEM0_0x00080000 + (rc_addr >>3))); + break; + } + pore_state.rc = pibmem_data.getWord((rc_addr & 0x04)?1:0); + } + else + { + FAPI_ERR("proc_extract_sbe_rc: Address (0x%012llX) isn't in a known memory address space", pore_state.pc); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED); + break; + } + + // invoke platform function to return XML defined RC associated with PORE state + FAPI_ERR("proc_extract_sbe_rc: PORE got error code 0x%06X", pore_state.rc); + FAPI_SET_SBE_ERROR(rc, pore_state.rc); + + // ensure that error is generated in this code path + if (rc.ok()) + { + FAPI_ERR("proc_extract_sbe_rc: PORE got error code 0x%06X, but this did not resolve to any return code!", pore_state.rc); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG); + } + break; } } // "Instruction Execution Error" bucket (Error Event 2) - if ((sbe_data1.getNumBitsSet(52,9) != 0) || (sbe_data1.isBitSet(62))) - { - FAPI_ERR("SBE encountered instruction execution error"); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; - const bool & INSTRUCTION_PARITY_ERROR = sbe_data1.isBitSet(52); - const bool & INVALID_INSTRUCTION_NON_ROTATE = sbe_data1.isBitSet(53); - const bool & PC_OVERFLOW_UNDERFLOW = sbe_data1.isBitSet(54); + if ((pore_debug1_reg.getNumBitsSet(52,9) != 0) || (pore_debug1_reg.isBitSet(62))) + { + FAPI_ERR("proc_extract_sbe_rc: Instruction execution error (Event 2)"); + const bool & INSTRUCTION_PARITY_ERROR = pore_debug1_reg.isBitSet(52); + const bool & INVALID_INSTRUCTION_NON_ROTATE = pore_debug1_reg.isBitSet(53); + const bool & PC_OVERFLOW_UNDERFLOW = pore_debug1_reg.isBitSet(54); // bit 55 covered by Internal Error check - const bool & PC_STACK_ERROR = sbe_data1.isBitSet(56); - const bool & INSTRUCTION_FETCH_ERROR = sbe_data1.isBitSet(57); - const bool & INVALID_OPERAND = sbe_data1.isBitSet(58); - const bool & I2C_ENGINE_MISS = sbe_data1.isBitSet(59); - const bool & INVALID_START_VECTOR = sbe_data1.isBitSet(60); - const bool & INVALID_INSTRUCTION_ROTATE = sbe_data1.isBitSet(62); - - if (i_engine == SBE) - { - const soft_error_t & SOFT_ERR_STATUS = soft_err; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW); - } + const bool & PC_STACK_ERROR = pore_debug1_reg.isBitSet(56); + const bool & INSTRUCTION_FETCH_ERROR = pore_debug1_reg.isBitSet(57); + const bool & INVALID_OPERAND = pore_debug1_reg.isBitSet(58); + const bool & I2C_ENGINE_MISS = pore_debug1_reg.isBitSet(59); + const bool & INVALID_START_VECTOR = pore_debug1_reg.isBitSet(60); + const bool & INVALID_INSTRUCTION_ROTATE = pore_debug1_reg.isBitSet(62); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR); break; } - } // SBE ANYERROR debug(63) + } + - // no error bits are set, check PC to check execution progress - // check for real halt (wait 0) instruction in OTPROM - if ((i_engine == SBE) && ((pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE)) + // + // processor SBE -- check for real halt in OTPROM + // + + // for processor SBE only, check for real halt (wait 0) instruction in OTPROM + if (is_processor && is_sbe && ((pore_state.pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE)) { // Note: OTPROM halts are actual halt instructions, which means the // SBE updated the PC before the halt. // Thus we have to subtract 4 to get back to the address of the halt - uint32_t internal_address = (uint32_t)(pc & INTERNAL_ADDR_MASK) - 4; + uint32_t pc_m4 = (uint32_t)(pore_state.pc & INTERNAL_ADDR_MASK)-4; // map the OTPROM address to the known error at that location // the OTPROM is write-once at mfg test, so addresses should remain fixed in this code - FAPI_INF("Determining the OTPROM error based on the address " - "0x%X", internal_address); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = internal_address; - - switch (internal_address) + FAPI_INF("proc_extract_sbe_rc: Determining OTPROM error at address 0x%X", pc_m4); + switch (pc_m4) { case (0x400fc): // original OTPROM version case (0x40118): // updated OTPROM version - FAPI_ERR("Chip not identified as Murano or Venice"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE); + FAPI_ERR("proc_extract_sbe_rc: Chip was not identified as Murano or Venice"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE); break; case (0x401c0): - FAPI_ERR("SEEPROM magic number didn't match \"XIP SEPM\""); - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE); + FAPI_ERR("proc_extract_sbe_rc: SEEPROM magic number didn't match \"XIP SEPM\""); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH); break; case (0x401ec): - FAPI_ERR("Branch to SEEPROM didn't happen"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE); + FAPI_ERR("proc_extract_sbe_rc: Branch to SEEPROM didn't happen"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL); break; default: - FAPI_ERR("Halted in OTPROM, but not at an expected halt location"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE); + FAPI_ERR("proc_extract_sbe_rc: Halted in OTPROM, but not at an expected halt location"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT); break; } - break; } - // check to see if engine was never started - if (((pc & SBE_ADDR_MASK) == 0x0000800000000000ULL) || - ((pc & SBE_ADDR_MASK) == 0x0000000000000000ULL)) - { - FAPI_ERR("PC is all zeros, which means %s was probably never started", ((i_engine == SBE)?("SBE"):("SLW"))); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; - if (i_engine == SBE) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE); - break; - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW); - break; - } + // + // all engine types -- validate execution progress of PC + // + + // determine if engine was ever started + if (((pore_state.pc & PORE_ADDR_MASK) == 0x0000800000000000ULL) || + ((pore_state.pc & PORE_ADDR_MASK) == 0x0000000000000000ULL)) + { + FAPI_ERR("proc_extract_sbe_rc: PC is all zeros, which means PORE engine was probably never started"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED); + break; } - // return soft error with lowest priority - if ((i_engine == SBE) && (soft_err != eNO_ERROR)) + + // + // processor SBE -- return soft error with lowest priority + // + + if (is_processor && is_sbe && (pore_sbe_state.soft_err != eNO_ERROR)) { - const fapi::Target & CHIP_IN_ERROR = i_target; - if (soft_err == eSOFT_ERR_I2CM) + if (pore_sbe_state.soft_err == eSOFT_ERR_I2CM) { - FAPI_ERR("Recoverable ECC Error on I2C Access"); - const ecmdDataBufferBase & I2C_ECCB_STATUS = i2cm_eccb_status; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_SBE); + FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on I2C Access"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM); break; } - else if (soft_err == eSOFT_ERR_PNOR) + else if (pore_sbe_state.soft_err == eSOFT_ERR_PNOR) { - FAPI_ERR("Recoverable ECC Error on PNOR Access"); - const ecmdDataBufferBase & PNOR_ECCB_STATUS = pnor_eccb_status; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR_SBE); + FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on PNOR Access"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR); break; } else // (soft_err == eSOFT_ERR_BOTH) { - FAPI_ERR("Recoverable ECC Error on PNOR Access"); - FAPI_ERR("Recoverable ECC Error on I2C Access"); - const ecmdDataBufferBase & PNOR_ECCB_STATUS = pnor_eccb_status; - const ecmdDataBufferBase & I2C_ECCB_STATUS = i2cm_eccb_status; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_AND_PNOR_SBE); + FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on I2C Access"); + FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on PNOR Access"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM_AND_PNOR); break; } } } while(0); - // if SBE, make sure that the code doesn't return FAPI_RC_SUCCESS - // if the engine reported an attn to the FSI2PIB status register - if (rc.ok() && (i_engine == SBE) && (sbe_reported_attn)) + // + // processor SBE -- ensure HWP doesn't return FAPI_RC_SUCCESS if the engine reported attn + // + if (rc.ok() && is_processor && is_sbe && pore_sbe_state.reported_attn) { - FAPI_ERR("SBE reported attention, but proc_extract_sbe_rc tried to return SUCCESS," - " which should be impossible. Must be a code bug."); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint64_t & PC = pc; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE); + FAPI_ERR("proc_extract_sbe_rc: SBE reported attention, but proc_extract_sbe_rc tried to return SUCCESS!"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG); } + + // + // all engine types -- append engine specific base FFDC to any non-zero return code + // + + if (!rc.ok()) + { + FAPI_ADD_INFO_TO_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_BASE_FFDC); + } + + FAPI_INF("proc_extract_sbe_rc: End"); return rc; } } // extern "C" -/* Local Variables: */ -/* c-basic-offset: 4 */ -/* End: */ diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H index 8571d3de3..3e2114749 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_extract_sbe_rc.H,v 1.7 2014/03/18 14:09:28 jmcgill Exp $ +// $Id: proc_extract_sbe_rc.H,v 1.9 2014/07/24 03:13:59 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.H,v $ //------------------------------------------------------------------------------ // *| @@ -31,31 +31,145 @@ // *! *** *** // *| // *! TITLE : proc_extract_sbe_rc.H -// *! DESCRIPTION : Create a return code for an SBE/SLW error. +// *! DESCRIPTION : Create return code for PORE (SBE/SLW) error // *! -// *! OWNER NAME : Johannes Koesters Email: koesters@de.ibm.com +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com // *! //------------------------------------------------------------------------------ #ifndef _PROC_EXTRACT_SBE_RC_H_ #define _PROC_EXTRACT_SBE_RC_H_ + //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ #include <fapi.H> #include <p8_scom_addresses.H> +#include <cen_scom_addresses.H> + //------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ + +// engine types enum por_engine_t { - SBE = PORE_SBE_0x000E0000, - SLW = PORE_SLW_0x00068000 + SBE = PORE_SBE_0x000E0000, + SLW = PORE_SLW_0x00068000 +}; + +// common SCOM register offsets for SBE/SLW engines +enum por_reg_offset_t { + PORE_STATUS_OFFSET = 0x00, + PORE_CONTROL_OFFSET = 0x01, + PORE_RESET_OFFSET = 0x02, + PORE_ERR_MASK_OFFSET = 0x03, + PORE_P0_OFFSET = 0x04, + PORE_P1_OFFSET = 0x05, + PORE_A0_OFFSET = 0x06, + PORE_A1_OFFSET = 0x07, + PORE_TBL_BASE_OFFSET = 0x08, + PORE_EXE_TRIGGER_OFFSET = 0x09, + PORE_CTR_OFFSET = 0x0A, + PORE_D0_OFFSET = 0x0B, + PORE_D1_OFFSET = 0x0C, + PORE_IBUF0_OFFSET = 0x0D, + PORE_IBUF1_OFFSET = 0x0E, + PORE_DEBUG0_OFFSET = 0x0F, + PORE_DEBUG1_OFFSET = 0x10, + PORE_STACK0_OFFSET = 0x11, + PORE_STACK1_OFFSET = 0x12, + PORE_STACK2_OFFSET = 0x13, + PORE_IDFLAGS_OFFSET = 0x14, + PORE_SPRG0_OFFSET = 0x15, + PORE_MRR_OFFSET = 0x16, + PORE_I2CE0_OFFSET = 0x17, + PORE_I2CE1_OFFSET = 0x18, + PORE_I2CE2_OFFSET = 0x19, + PORE_NUM_REGS = 0x1A +}; + +// SBE soft error types +enum por_sbe_soft_error_t +{ + eNO_ERROR = 0, + eSOFT_ERR_I2CM=1, + eSOFT_ERR_PNOR=2, + eSOFT_ERR_BOTH=3 +}; + +enum por_halt_type_t +{ + PORE_HALT_SCAN_FAIL = 0, + PORE_HALT_SCAN_FLUSH_FAIL = 1, + PORE_HALT_ARRAYINIT_FAIL = 2, + PORE_HALT_SKEW_ADJUST_FAIL = 3, + PORE_HALT_FIR_FAIL = 4, + PORE_HALT_INSTRUCT_FAIL = 5, + PORE_HALT_DPLL_LOCK_FAIL = 6 +}; + +enum por_ffdc_offset_t +{ + POR_FFDC_OFFSET_NONE = 0x0, + POR_FFDC_OFFSET_TP_CHIPLET = TP_CHIPLET_0x01000000, + POR_FFDC_OFFSET_NEST_CHIPLET = NEST_CHIPLET_0x02000000, + POR_FFDC_OFFSET_MEM_CHIPLET = MEM_CHIPLET_0x03000000, + POR_FFDC_OFFSET_XBUS_CHIPLET = X_BUS_CHIPLET_0x04000000, + POR_FFDC_OFFSET_ABUS_CHIPLET = A_BUS_CHIPLET_0x08000000, + POR_FFDC_OFFSET_PCIE_CHIPLET = PCIE_CHIPLET_0x09000000, + POR_FFDC_OFFSET_EX_CHIPLET = EX00_CHIPLET_0x10000000, + POR_FFDC_OFFSET_USE_P0 = PORE_P0_OFFSET, + POR_FFDC_OFFSET_USE_P1 = PORE_P1_OFFSET +}; + + +// structure to encapsulate PORE state/FFDC content +struct por_base_state +{ + fapi::Target target; // chip target associated with failed engine + por_engine_t engine; // engine type (SBE/SLW) + bool is_virtual; // virtual engine? + ecmdDataBufferBase vital_state; // SBE/SLW vital state + ecmdDataBufferBase engine_state; // SBE/SLW engine state + uint64_t pc; // SBE/SLW engine PC + uint32_t rc; // RC associated with SBE/SLW halt point + + por_base_state() + { + vital_state.setDoubleWordLength(1); + vital_state.flushTo1(); + engine_state.setDoubleWordLength(PORE_NUM_REGS); + engine_state.flushTo1(); + pc = 0xFFFFFFFFFFFFFFFFULL; + rc = 0x0; + } +}; + +// structure to encapsulate PORE SBE-specific base FFDC content +struct por_sbe_base_state +{ + ecmdDataBufferBase pnor_eccb_status; // PNOR ECCB status register state + ecmdDataBufferBase i2cm_eccb_status; // SEEPROM ECCB status register state + por_sbe_soft_error_t soft_err; // PNOR/SEEPROM soft error state + bool reported_attn; // SBE generated attention? + + por_sbe_base_state() + { + pnor_eccb_status.setDoubleWordLength(1); + pnor_eccb_status.flushTo1(); + i2cm_eccb_status.setDoubleWordLength(1); + i2cm_eccb_status.flushTo1(); + soft_err = eNO_ERROR; + reported_attn = false; + } }; // function pointer typedef definition for HWP call support typedef fapi::ReturnCode (*proc_extract_sbe_rc_FP_t)(const fapi::Target &, + void *, const void *, const por_engine_t); @@ -68,17 +182,21 @@ extern "C" { /** - * @brief Create a return code based off the current SBE/SLW RC. + * proc_extract_sbe_rc - HWP entry point, return RC indicating SBE/SLW error + * + * @param[in] i_target - target of chip with failed SBE/SLW engine + * @param[in] i_poreve - pointer to PoreVe object, used to collect engine + * state if non NULL + * @param[in] i_image - pointer to memory-mapped PORE image + * @param[in] i_engine - type of engine that failed (SBE/SLW) * - * @param[in] i_target Reference to processor target containing the SBE/SLW engine - * @param[in] i_pSEEPROM Pointer to a memory-mapped SEEPROM image (or NULL) - * @param[in] i_engine The POR engine type (SBE/SLW) - * @return ReturnCode The error code the SBE hit, or the error hit - * while trying to get the error code + * @retval fapi::ReturnCode - The error code the SBE hit, or the error hit + * while trying to get the error code */ - fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target, - const void * i_pSEEPROM, - const por_engine_t i_engine); +fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target, + void * i_poreve, + const void * i_image, + const por_engine_t i_engine); } // extern "C" diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml index a51a4a61f..3abfd4275 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml @@ -22,223 +22,143 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.15 2014/06/30 14:33:53 bgeukes Exp $ --> +<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.16 2014/07/23 19:51:48 jmcgill Exp $ --> <!-- Error definitions for proc_extract_sbe_rc procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED</rc> <description> Procedure: proc_extract_sbe_rc - NULL image pointer prevented extraction of SBE error code + The PORE engine PC isn't properly aligned </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_SEEPROM</rc> <description> Procedure: proc_extract_sbe_rc - NULL image pointer prevented extraction of SLW error code + ECCB indicates unrecoverable ECC error from I2C during SBE execution + Reload/update of SEEPROM required </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR</rc> <description> Procedure: proc_extract_sbe_rc - The SBE stop address isn't properly aligned + ECCB indicates unrecoverable ECC error from PNOR during SBE execution + Reload/Update of PNOR required </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR</rc> <description> Procedure: proc_extract_sbe_rc - The SLW stop address isn't properly aligned + PORE engine encountered an internal HW error </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> + <ffdc>GROUP_PARITY_ERROR_0_4</ffdc> + <ffdc>SCAN_DATA_CRC_ERROR</ffdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR</rc> <description> Procedure: proc_extract_sbe_rc - The SBE stop address isn't in a recognized address space + PORE engine encountered a I2C interface/setup error </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> + <ffdc>I2C_BAD_STATUS_0_3</ffdc> + <ffdc>FI2C_HANG</ffdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR</rc> <description> Procedure: proc_extract_sbe_rc - The SLW stop address isn't in a reognized address space + PORE engine encountered a SCOM error </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> + <ffdc>SCOM_ADDRESS</ffdc> + <ffdc>PIB_ERROR_CODE</ffdc> + <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_OCI_ERROR</rc> <description> Procedure: proc_extract_sbe_rc - Extract RC from address subroutine tried to return SUCCESS for SBE, which isn't allowed + PORE SLW engine encountered error on OCI interface </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> + <ffdc>OCI_ERROR_CODE</ffdc> + <ffdc>OCI_DATA_READ_PARITY_ERROR</ffdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL</rc> <description> Procedure: proc_extract_sbe_rc - Extract RC from address subroutine tried to return SUCCESS for SLW, which isn't allowed + PORE image pointer provided was NULL. </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <callout> @@ -246,22 +166,21 @@ <priority>LOW</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED</rc> <description> Procedure: proc_extract_sbe_rc - Tried to extract error from unknown engine type + The PORE halt address isn't in a recognized address space </description> - <ffdc>ENGINE</ffdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <callout> @@ -269,328 +188,58 @@ <priority>LOW</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE</rc> - <description> - Procedure: proc_extract_sbe_rc - Error during PIB access for SBE - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>FSI_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE</rc> - <description> - Procedure: proc_extract_sbe_rc - ECCB indicates unrecoverable ECC error from I2C during SBE execution - Reload/update of SEEPROM required - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>ECCB_STATUS</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE</rc> - <description> - Procedure: proc_extract_sbe_rc - ECCB indicates unrecoverable ECC error from PNOR during SBE execution - Reload/Update of PNOR required - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>ECCB_STATUS</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE</rc> - <description> - Procedure: proc_extract_sbe_rc - SBE engine encountered an internal error - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>GROUP_PARITY_ERROR_0_4</ffdc> - <ffdc>SCAN_DATA_CRC_ERROR</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW</rc> - <description> - Procedure: proc_extract_sbe_rc - SLW engine encountered an internal error - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>GROUP_PARITY_ERROR_0_4</ffdc> - <ffdc>SCAN_DATA_CRC_ERROR</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE</rc> - <description> - Procedure: proc_extract_sbe_rc - SBE engine encountered a SCOM error - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>SCOM_ADDRESS</ffdc> - <ffdc>PIB_ERROR_CODE</ffdc> - <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW</rc> + <rc>RC_SBE_UNKNOWN_ERROR</rc> <description> Procedure: proc_extract_sbe_rc - SLW engine encountered a SCOM error + FAPI_SET_SBE_ERROR did not resolve PORE halt code to known return code + May be caused by platform attempting to resolve engine state with mismatched binary image. </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>SCOM_ADDRESS</ffdc> - <ffdc>PIB_ERROR_CODE</ffdc> - <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> + <target>CHIP</target> + <priority>LOW</priority> </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW</rc> - <description> - Procedure: proc_extract_sbe_rc - SLW engine encountered error on OCI interface - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>OCI_ERROR_CODE</ffdc> - <ffdc>OCI_DATA_READ_PARITY_ERROR</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <procedure>CODE</procedure> <priority>HIGH</priority> </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG</rc> <description> Procedure: proc_extract_sbe_rc - SBE engine encountered a I2C interface/setup error + Failed to association PORE halt code with known return code </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>I2C_BAD_STATUS_0_3</ffdc> - <ffdc>FI2C_HANG</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW</rc> - <description> - Procedure: proc_extract_sbe_rc - SLW engine encountered a I2C interface/setup error - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>I2C_BAD_STATUS_0_3</ffdc> - <ffdc>FI2C_HANG</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE</rc> - <description> - Procedure: proc_extract_sbe_rc - SBE engine encountered an instruction fetch/decode/execution error - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <ffdc>INSTRUCTION_PARITY_ERROR</ffdc> - <ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc> - <ffdc>PC_OVERFLOW_UNDERFLOW</ffdc> - <ffdc>PC_STACK_ERROR</ffdc> - <ffdc>INSTRUCTION_FETCH_ERROR</ffdc> - <ffdc>INVALID_OPERAND</ffdc> - <ffdc>I2C_ENGINE_MISS</ffdc> - <ffdc>INVALID_START_VECTOR</ffdc> - <ffdc>INVALID_INSTRUCTION_ROTATE</ffdc> - <ffdc>SOFT_ERR_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> + <procedure>CODE</procedure> + <priority>LOW</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR</rc> <description> Procedure: proc_extract_sbe_rc - SLW engine encountered an instruction fetch/decode/execution error + PORE engine encountered an instruction fetch/decode/execution error </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> <ffdc>INSTRUCTION_PARITY_ERROR</ffdc> <ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc> <ffdc>PC_OVERFLOW_UNDERFLOW</ffdc> @@ -600,151 +249,119 @@ <ffdc>I2C_ENGINE_MISS</ffdc> <ffdc>INVALID_START_VECTOR</ffdc> <ffdc>INVALID_INSTRUCTION_ROTATE</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE</rc> <description> Procedure: proc_extract_sbe_rc - SBE execution of OTPROM code failed chip type (Murano/Venice) check + PORE SBE execution of OTPROM code failed chip type (Murano/Venice) check </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH</rc> <description> Procedure: proc_extract_sbe_rc - SBE execution of OTPROM code failed SEEPROM magic number check + PORE SBE execution of OTPROM code failed SEEPROM magic number check </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL</rc> <description> Procedure: proc_extract_sbe_rc - SBE execution of OTPROM code failed to branch to SEEPROM + PORE SBE execution of OTPROM code failed to branch to SEEPROM </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT</rc> <description> Procedure: proc_extract_sbe_rc - SBE execution of OTPROM code halted at an unexpected location + PORE SBE execution of OTPROM code halted at an unexpected location </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED</rc> <description> Procedure: proc_extract_sbe_rc - Procedure was called when no error bits were set and PC is all zeros. SBE - was probably never started. + Procedure was called when no error bits were set and PC is all zeros. + PORE engine was probably never started. </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> <collectRegisterFfdc> - <id>REG_FFDC_PROC_CFAM_REGISTERS</id> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </collectRegisterFfdc> - <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>HIGH</priority> </callout> <callout> @@ -752,153 +369,70 @@ <priority>LOW</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> <gard> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW</rc> - <description> - Procedure: proc_extract_sbe_rc - Procedure was called when no error bits were set and PC is all zeros. SLW - was probably never started. - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP_IN_ERROR</target> - </deconfigure> - <gard> - <target>CHIP_IN_ERROR</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM</rc> <description> Procedure: proc_extract_sbe_rc ECCB indicates correctable ECC error threshold from I2C was exceeded during SBE execution Reload/update of SEEPROM required </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>I2C_ECCB_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>LOW</priority> </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR</rc> <description> Procedure: proc_extract_sbe_rc ECCB indicates correctable ECC error threshold from PNOR was exceeded during SBE execution Reload/update of PNOR required </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PNOR_ECCB_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>LOW</priority> </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_AND_PNOR_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM_AND_PNOR</rc> <description> Procedure: proc_extract_sbe_rc ECCB indicates correctable ECC error threshold from both I2C and PNOR was exceeded during SBE execution Reload/update of SEEPROM/PNOR required </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>I2C_ECCB_STATUS</ffdc> - <ffdc>PNOR_ECCB_STATUS</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> <priority>LOW</priority> </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG</rc> <description> Procedure: proc_extract_sbe_rc - SBE reported attention, but procedure attempted to return SUCCESS + PORE SBE reported attention, but procedure attempted to return SUCCESS </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <ffdc>PC</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> <callout> <procedure>CODE</procedure> <priority>LOW</priority> </callout> <deconfigure> - <target>CHIP_IN_ERROR</target> + <target>CHIP</target> </deconfigure> </hwpError> <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_UNKNOWN_ERROR</rc> - <description> - Procedure: proc_extract_sbe_rc - FAPI_SET_SBE_ERROR did not resolve SBE/SLW PC to known RC. - May be caused by platform attempting to resolve engine state with mismatched binary image. - </description> - <ffdc>CHIP_IN_ERROR</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> - <id>REG_FFDC_PROC_MBOX_REGISTERS</id> - <target>CHIP_IN_ERROR</target> - </collectRegisterFfdc> - <callout> - <target>CHIP_IN_ERROR</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- *********************************************************************** --> </hwpErrors> + + + diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 7466ffba6..a8c706074 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -175,6 +175,13 @@ HWP_ERROR_XML_FILES += hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml HWP_ERROR_XML_FILES += hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml HWP_ERROR_XML_FILES += hwp/proc_sbe_errors/sbe_common_halt_codes.xml HWP_ERROR_XML_FILES += hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml +HWP_ERROR_XML_FILES += hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.xml +HWP_ERROR_XML_FILES += hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml +HWP_ERROR_XML_FILES += hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml +HWP_ERROR_XML_FILES += hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml +HWP_ERROR_XML_FILES += hwp/proc_pba_utils_registers.xml +HWP_ERROR_XML_FILES += hwp/p8_fir_registers.xml +HWP_ERROR_XML_FILES += hwp/cen_fir_registers.xml ## these get generated into obj/genfiles/AttributeIds.H HWP_ATTR_XML_FILES += hwp/memory_attributes.xml @@ -209,7 +216,6 @@ HWP_ATTR_XML_FILES += hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.x HWP_ATTR_XML_FILES += hwp/proc_chip_ec_feature.xml HWP_ATTR_XML_FILES += hwp/proc_abus_dmi_xbus_scominit_attributes.xml HWP_ATTR_XML_FILES += hwp/runtime_attributes/memory_occ_attributes.xml -HWP_ERROR_XML_FILES += hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.xml #------------------------------------------------------------------------------ # PLL Ring Data files diff --git a/src/usr/pore/fapiporeve/fapiPoreVe.C b/src/usr/pore/fapiporeve/fapiPoreVe.C index 59aacde62..653c3fbee 100644 --- a/src/usr/pore/fapiporeve/fapiPoreVe.C +++ b/src/usr/pore/fapiporeve/fapiPoreVe.C @@ -23,7 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: fapiPoreVe.C,v 1.35 2014/03/31 15:21:37 thi Exp $ +// $Id: fapiPoreVe.C,v 1.37 2014/07/25 15:19:10 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/poreve/working/fapiporeve/fapiPoreVe.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -69,11 +69,22 @@ #ifdef FAPIECMD extern "C" { + #if FAPIECMD == 1 + const uint32_t MBOX_SBEVITAL_0x0005001C = 0x0005001C; + #define FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC 0 + #else + #define FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC 1 + #endif +#else + #define FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC 1 #endif +#if FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC == 1 + #include <proc_extract_sbe_rc.H> +#endif + using namespace vsbe; -const uint32_t MBOX_SBEVITAL_0x0005001C = 0x0005001C; //****************************************************************************** // fapiPoreVe function @@ -625,7 +636,7 @@ fapi::ReturnCode fapiPoreVe( uint64_t data_64; int pib_rc; ModelError me; - me = poreve->getscom(MBOX_SBEVITAL_0x0005001C, data_64, pib_rc); + me = poreve->getscom((uint32_t) MBOX_SBEVITAL_0x0005001C, data_64, pib_rc); if( me == ME_SUCCESS ) { if( pib_rc == 0 ) @@ -635,10 +646,18 @@ fapi::ReturnCode fapiPoreVe( if( haltcode != 0xF ) { FAPI_ERR( "Halt code is 0x%x (ERROR)\n", haltcode ); - uint32_t & ERROR = haltcode; - FAPI_SET_HWP_ERROR(rc, - RC_FAPIPOREVE_HALTED_WITH_ERROR); poreve->iv_pore.dumpOnce(); +#if FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC == 1 + FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, poreve, + (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)?(poreve->iv_seepromMemory.iv_images->iv_image):(poreve->iv_pnorMemory.iv_images->iv_image), + SBE); +#endif + if (rc.ok()) + { + uint32_t & ERROR = haltcode; + FAPI_SET_HWP_ERROR(rc, + RC_FAPIPOREVE_HALTED_WITH_ERROR); + } } else { @@ -667,8 +686,16 @@ fapi::ReturnCode fapiPoreVe( { FAPI_ERR( "PORE is stopped due to an architected error\n"); runStatus &= ~PORE_STATUS_ERROR_HALT; - FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ARCHITECTED_ERROR); poreve->iv_pore.dumpOnce(); +#if FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC == 1 + FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, poreve, + (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)?(poreve->iv_seepromMemory.iv_images->iv_image):(poreve->iv_pnorMemory.iv_images->iv_image), + SBE); +#endif + if (rc.ok()) + { + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ARCHITECTED_ERROR); + } } if( runStatus & PORE_STATUS_HARDWARE_STOP ) { @@ -689,8 +716,16 @@ fapi::ReturnCode fapiPoreVe( { FAPI_ERR( "PORE is stopped due to a modeling error\n"); runStatus &= ~PORE_STATUS_MODEL_ERROR; - FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_MODELING_ERROR); poreve->iv_pore.dumpOnce(); +#if FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC == 1 + FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, poreve, + (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)?(poreve->iv_seepromMemory.iv_images->iv_image):(poreve->iv_pnorMemory.iv_images->iv_image), + SBE); +#endif + if (rc.ok()) + { + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_MODELING_ERROR); + } } if( runStatus & PORE_STATUS_DEBUG_STOP ) { @@ -703,8 +738,17 @@ fapi::ReturnCode fapiPoreVe( { FAPI_ERR( "PORE is stopped with an unknown status code:0x%X\n", runStatus); - int & STATUS = runStatus; - FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_UNKNOWN_STATUS_ERROR); + poreve->iv_pore.dumpOnce(); +#if FAPIPOREVE_USE_PROC_EXTRACT_SBE_RC == 1 + FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, poreve, + (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)?(poreve->iv_seepromMemory.iv_images->iv_image):(poreve->iv_pnorMemory.iv_images->iv_image), + SBE); +#endif + if (rc.ok()) + { + int & STATUS = runStatus; + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_UNKNOWN_STATUS_ERROR); + } } } else { //runStatus == 0 FAPI_IMP( "PORE ran the requested number of instructions " @@ -842,6 +886,8 @@ fapi::ReturnCode fapiPoreVe( HookManager::destroy(); #endif + FAPI_INF("\nfapiPoreVe return code = 0x%08X\n", (uint32_t) rc); + return rc; } //end function @@ -855,6 +901,12 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they are included here. $Log: fapiPoreVe.C,v $ +Revision 1.37 2014/07/25 15:19:10 jmcgill +add ifdefs to exclude proc_extract_sbe_rc analysis for Cronus + +Revision 1.36 2014/07/23 20:34:14 jmcgill +invoke proc_extract_sbe_rc on execution errors (SW261816/SW260441) + Revision 1.35 2014/03/31 15:21:37 thi Added FFDC and callouts diff --git a/src/usr/pore/fapiporeve/makefile b/src/usr/pore/fapiporeve/makefile index e62110a4a..280cc348a 100644 --- a/src/usr/pore/fapiporeve/makefile +++ b/src/usr/pore/fapiporeve/makefile @@ -5,7 +5,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2011,2014 +# Contributors Listed Below - COPYRIGHT 2012,2014 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -33,6 +35,8 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/porevesrc EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/pore_model EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/model +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/ +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include/ OBJS += fapiPoreVe.o OBJS += fapiPoreVeArg.o |
