diff options
| -rw-r--r-- | src/import/chips/p9/security/Centaur_Register_List.csv | 143 |
1 files changed, 143 insertions, 0 deletions
diff --git a/src/import/chips/p9/security/Centaur_Register_List.csv b/src/import/chips/p9/security/Centaur_Register_List.csv index e69de29bb..630913628 100644 --- a/src/import/chips/p9/security/Centaur_Register_List.csv +++ b/src/import/chips/p9/security/Centaur_Register_List.csv @@ -0,0 +1,143 @@ +#Register Address,WAND,WOR,Init/Expected Value,Mask Value, +1000000,1000004,1000005,7001900000000003,, +# @TODO: RTC 187288 +# Some bits (see mask) are not tracking as expected +2000000,2000004,2000005,7001900000000003,FFFE7FFFFFFFFFFD, +2010800,2010801,2010802,0000400000000000,, +2010803,2010804,2010805,FFFFFFE000000000,, +2010C42,,,,, +201140A,,,,, +201140B,,,,, +201140C,,,,, +201140D,,,0539770539770000,, +201140E,,,,, +2011681,,,,, +2011682,,,,, +2011683,,,,, +2011684,,,,, +2011685,,,,, +2011686,,,,, +2011687,,,,, +2011688,,,,, +2011689,,,,, +201168A,,,,, +2011781,,,,, +2011782,,,,, +2011783,,,,, +2011784,,,,, +2011785,,,,, +2011786,,,,, +2011787,,,,, +2011788,,,,, +2011789,,,,, +201178A,,,,, +2011882,,,,, +20118C2,,,,, +2012300,,,0000A00000000000,, +201230B,,,,, +2030000,,,,, +# @TODO: RTC 187288 +# 0:1 CLOCK_CMD masked off because it auto-resets to 0 +# Right now mask those bits off for the comparison, but consider +# modeling the auto reset behavior +2030006,,,0FE00E0000000000,3FFFFFFFFFFFFFFF, +2030007,,,,, +# @TODO: RTC 187288 +# Enabling causes 2011882 to report wrongly for some reason +#20F0012,20F0013,20F0014,4016620000000000,3FFFBDFFFFFFFFFF, +# @TODO: RTC 187288 +# This is broken, needs more attention +#3000000,3000004,3000005,7001900000000003,, +3010414,,,7FFFFFFFFFFFD7FF,, +3010415,,,BFFFFFFFFFFFEFFF,, +3010433,,,8484212100000000,, +301060A,,,,, +# @TODO: RTC 187288 +# First 2 bits reset by HW without SW knowledge +# So need to either let the HW read through for these bits, or +# ignore the register +#301060B,,,,3FFFFFFFFFFFFFFF, +# @TODO: RTC 187288 +# Expected value is way off from actual value for +# unknown reasons. Fix or ignore the register +#301060D,,,,, +301060E,,,,, +301060F,,,,, +3010614,,,FFE0000000000000,, +3010615,,,,, +3010616,,,,, +3010617,,,,, +3010618,,,,, +3010619,,,,, +301061A,,,,, +301061B,,,,, +301061C,,,,, +301061D,,,,, +301061E,,,,, +301061F,,,,, +3010620,,,,, +3010621,,,,, +3010622,,,,, +3010623,,,,, +3010624,,,,, +3010625,,,,, +3010626,,,,, +3010627,,,,, +3010628,,,,, +3010629,,,,, +301062A,,,,, +301062B,,,,, +301062C,,,,, +301062D,,,,, +301062E,,,,, +301062F,,,,, +3010630,,,,, +3010631,,,,, +3010632,,,,, +3010633,,,,, +3010634,,,,, +3010635,,,,, +3010636,,,,, +3010637,,,,, +3010638,,,,, +3010639,,,,, +301063A,,,,, +301063B,,,,, +301063C,,,,, +301063D,,,,, +301063E,,,,, +301063F,,,,, +301064A,,,,, +301064B,,,,, +301064C,,,,, +301064D,,,,, +301064E,,,,, +301064F,,,,, +3010650,,,,, +3010651,,,,, +3010652,,,,, +3010653,,,,, +# @TODO: RTC 187288 +# First 2 bits reset by HW without SW knowledge +# So need to either let the HW read through for these bits, or +# ignore the register +#30106A5,,,,3FFFFFFFFFFFFFFF, +30106A7,,,0000000400000000,, +30106BE,,,,, +30106BF,,,,, +30106C0,,,,, +30106C1,,,,, +30106C2,,,,, +30106C3,,,,, +30106C4,,,,, +30106C5,,,,, +30106C6,,,,, +30106C7,,,,, +30106DB,,,,, +3012300,,,0000A00000000000,, +301230B,,,,, +3030000,,,,, +# @TODO: RTC 187288 +# Enabling this register causes failing +# behavior for 303000 +#30F0012,30F0013,30F0014,,, |
