diff options
8 files changed, 700 insertions, 538 deletions
diff --git a/src/usr/hwas/hostbootIstep.C b/src/usr/hwas/hostbootIstep.C index cd9a4f455..fa64ab222 100644 --- a/src/usr/hwas/hostbootIstep.C +++ b/src/usr/hwas/hostbootIstep.C @@ -277,9 +277,8 @@ void* host_prd_hwreconfig( void *io_pArgs ) break; } - // Lists for present MCS/Centaurs + // Lists for present MCS TARGETING::TargetHandleList l_presMcsList; - TARGETING::TargetHandleList l_presCentaurList; // find all present MCS chiplets of all procs getChipletResources(l_presMcsList, TYPE_MCS, UTIL_FILTER_PRESENT); @@ -295,41 +294,17 @@ void* host_prd_hwreconfig( void *io_pArgs ) TARGETING::ATTR_HUID_type l_currMcsHuid = TARGETING::get_huid(l_pMcs); - // Find all the present Centaurs that are associated with this MCS - getChildAffinityTargetsByState(l_presCentaurList, l_pMcs, - CLASS_CHIP, TYPE_MEMBUF, UTIL_FILTER_PRESENT); - - // There will always be 1 Centaur associated with a MCS. - if(1 != l_presCentaurList.size()) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "No present Centaurs found for " - "MCS target HUID %.8X , skipping this MCS", - l_currMcsHuid); - continue; - } - - // Make a local copy - const TARGETING::Target * l_pCentaur = l_presCentaurList[0]; - // Retrieve HUID of current Centaur - TARGETING::ATTR_HUID_type l_currCentaurHuid = - TARGETING::get_huid(l_pCentaur); - // Dump current run on target TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Running proc_enable_reconfig HWP on " - "MCS target HUID %.8X CENTAUR target HUID %.8X", - l_currMcsHuid, l_currCentaurHuid); + "MCS target HUID %.8X", l_currMcsHuid); // Create FAPI Targets. fapi::Target l_fapiMcsTarget(TARGET_TYPE_MCS_CHIPLET, (const_cast<TARGETING::Target*>(l_pMcs))); - fapi::Target l_fapiCentaurTarget(TARGET_TYPE_MEMBUF_CHIP, - (const_cast<TARGETING::Target*>(l_pCentaur))); // Call the HWP with each fapi::Target - FAPI_INVOKE_HWP(errl, proc_enable_reconfig, - l_fapiMcsTarget, l_fapiCentaurTarget); + FAPI_INVOKE_HWP(errl, proc_enable_reconfig, l_fapiMcsTarget); if (errl) { @@ -353,9 +328,7 @@ void* host_prd_hwreconfig( void *io_pArgs ) // Success TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Successfully ran proc_enable_reconfig HWP on " - "MCS target HUID %.8X CENTAUR target HUID %.8X", - l_currMcsHuid, - l_currCentaurHuid); + "MCS target HUID %.8X", l_currMcsHuid); } } while(0); diff --git a/src/usr/hwas/makefile b/src/usr/hwas/makefile index 355e4fdf0..e8e5aae67 100644 --- a/src/usr/hwas/makefile +++ b/src/usr/hwas/makefile @@ -25,6 +25,7 @@ ROOTPATH = ../../.. EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwas EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwas/common EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training ## support for Targeting and fapi EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup.C b/src/usr/hwpf/hwp/bus_training/io_cleanup.C index 1a2bdab42..739f4e8ae 100644 --- a/src/usr/hwpf/hwp/bus_training/io_cleanup.C +++ b/src/usr/hwpf/hwp/bus_training/io_cleanup.C @@ -20,7 +20,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_cleanup.C,v 1.13 2014/05/16 18:23:37 dcrowell Exp $ +// $Id: io_cleanup.C,v 1.14 2014/06/06 19:43:41 steffen Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -44,280 +44,332 @@ #include <fapi.H> #include "io_cleanup.H" #include "gcr_funcs.H" - +#include <p8_scom_addresses.H> extern "C" { - using namespace fapi; + using namespace fapi; + // For clearing the FIR mask , used by io run training // As per Irving , it should be ok to clear all FIRs here since we will scom init , also we dont touch mask values ReturnCode clear_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ - ReturnCode rc; - ecmdDataBufferBase data(64); - FAPI_INF("io_cleanup:In the Clear FIR RW register function "); - - // use FIR AND mask register to un-mask selected bits - rc = fapiPutScom(i_target, fir_rw_reg_addr[i_chip_interface], data); - if (!rc.ok()) - { - FAPI_ERR("Error writing FIR mask register (=%08X)!", - fir_rw_reg_addr[i_chip_interface]); - } - return(rc); + ReturnCode rc; + ecmdDataBufferBase data(64); + FAPI_INF("io_cleanup:In the Clear FIR RW register function on %s", i_target.toEcmdString()); + rc = fapiPutScom(i_target, fir_rw_reg_addr[i_chip_interface], data); + if (!rc.ok()){FAPI_ERR("Error writing FIR mask register (=%08X)!",fir_rw_reg_addr[i_chip_interface]);} + return(rc); } -/* - from Megan's ipl1.sh - - istep -s0..11 -## forcing channel fail -getscom pu 02011C4A -pall -call -vs1 - getscom cen 0201080A -pall -call -vs1 - putscom pu 02011C4A 8000000480400000 -pall -call - putscom cen 0201080A 8000000000000000 -pall -call - getscom pu 02011C4A -pall -call -vs1 - getscom cen 0201080A -pall -call -vs1 -## masking fir bit -putscom pu.mcs 2011843 FFFFFFFFFFFFFFFF -all -### IO reset -iotk put rx_fence=1 -t=p8:bmcs -iotk put rx_fence=1 -t=cn -iotk put ioreset_hard_bus0=111111 -t=p8:bmcs -iotk put ioreset_hard_bus0=111111 -t=cn - -#exit -##clear_fir -./clear_fir.pl -### Reload -istep proc_dmi_scominit -istep dmi_scominit -##checking Zcal -iotk get tx_zcal_p_4x -t=p8:bmcs -iotk get tx_zcal_p_4x -t=cn -iotk get tx_zcal_sm_min_val -t=p8:bmcs -iotk get tx_zcal_sm_min_val -t=cn -iotk get tx_zcal_sm_max_val -t=p8:bmcs -iotk get tx_zcal_sm_max_val -t=cn -### Loading Zcal -iotk put tx_zcal_p_4x=00100 -iotk put tx_zcal_sm_min_val=0010101 -iotk put tx_zcal_sm_max_val=1000110 -## Runing Zcal -istep dmi_io_dccal -## forcing channel fail - getscom pu 02011C4A -pall -call -vs1 - getscom cen 0201080A -pall -call -vs1 - putscom pu 02011C4A 8000000480400000 -pall -call - putscom cen 0201080A 8000000000000000 -pall -call - getscom pu 02011C4A -pall -call -vs1 - getscom cen 0201080A -pall -call -vs1 -*/ - -ReturnCode do_cleanup(const Target &master_target,io_interface_t master_interface,uint32_t master_group,const Target &slave_target,io_interface_t slave_interface,uint32_t slave_group) -{ - ReturnCode rc; - uint32_t rc_ecmd = 0; - uint8_t chip_unit = 0; - ecmdDataBufferBase data(64); - ecmdDataBufferBase reg_data(16),set_bits(16),clear_bits(16),temp_bits(16); - - //iotk put rx_fence=1 -t=p8:bmcs - // No other field in this reg , so no need for RMW - rc_ecmd = temp_bits.setBit(0); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc=GCR_write(master_target, master_interface, rx_fence_pg, master_group,0, temp_bits, temp_bits,1,1); - if(rc) return rc; - - //iotk put rx_fence=1 -t=cn - rc=GCR_write(slave_target, slave_interface, rx_fence_pg, slave_group,0, temp_bits, temp_bits,1,1); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, - &master_target, - chip_unit); - if (!rc.ok()) - { - FAPI_ERR("Error retreiving MCS chiplet number!"); - return rc; - } - - // swizzle to DMI number - if (master_interface == CP_IOMC0_P0) - { - chip_unit = 3-(chip_unit % 4); - // swap 0 and 1 due to Clock group swap in layout - if(chip_unit==1){ - chip_unit=0; - } - else if(chip_unit==0){ - chip_unit=1; - } - - FAPI_DBG("CHIP UNIT IS %d",chip_unit); +ReturnCode do_cleanup(const Target &master_target,io_interface_t master_interface,uint32_t master_group){ + ReturnCode rc; + uint32_t rc_ecmd = 0; + ecmdDataBufferBase set_bits(16); + ecmdDataBufferBase clear_bits(16); + ecmdDataBufferBase mask_buffer_64(64); + ecmdDataBufferBase data_buffer_64(64); + ecmdDataBufferBase rx_set_bits(16); + ecmdDataBufferBase tx_set_bits(16); + bool memory_attached = false; + bool reset_required = false; + uint8_t l_attr_mss_init_state = 0x0; + uint8_t l_attr_proc_ec_mss_reconfig_possible = 0x0; + uint8_t mcs_unit_id = 0x0; + uint8_t mcs_unit_lower_limit = 0; + uint8_t mcs_unit_upper_limit = 3; + io_interface_t slave_interface = CEN_DMI; // Centaur scom base + uint32_t slave_group = 0x0; + // vector to hold MCS chiplet targets + std::vector<fapi::Target> mcs_chiplets; + fapi::Target master_parent_target; + fapi::Target attached_cen_target; - } - rc = fapiGetScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data); - if (!rc.ok()) - { - FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!", - scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); - return rc; - } + // Find DMI0 or DMI1 controller limits based on passed in target. + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &master_target, mcs_unit_id); // read chip unit number + if(rc){return rc;} + if(mcs_unit_id == 0){ // DMI0, not on Tuleta, on Brazos + mcs_unit_lower_limit = 0; + mcs_unit_upper_limit = 3; + }else if(mcs_unit_id == 4){ // DMI1, on Tuleta and Brazos + mcs_unit_lower_limit = 4; + mcs_unit_upper_limit = 7; + }else{ + return rc; + } - rc_ecmd = data.setBit(2+chip_unit,1); // Scom_mode_pb ,ioreset starts at bit 2 - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - FAPI_DBG("Writing the Hard reset on PU "); - // use FIR AND mask register to un-mask selected bits - rc = fapiPutScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data); - if (!rc.ok()) - { - FAPI_ERR("Error writing SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!", - scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); - return rc; - } + //Get Master Parent Target + rc = fapiGetParentChip(master_target, master_parent_target); if(rc){return rc;} - rc_ecmd = data.flushTo0(); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - // Centaur is always bus0 in reset register - if(slave_interface == CEN_DMI){ - chip_unit=0; - } - rc = fapiGetScom(slave_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data); - if (!rc.ok()) - { - FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!", - scom_mode_pb_reg_addr[FIR_CEN_DMI]); - return rc; - } - rc_ecmd = data.setBit(2+chip_unit,1); // Scom_mode_pb ,ioreset starts at bit 2 - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - // use FIR AND mask register to un-mask selected bits - rc = fapiPutScom(slave_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data); - if (!rc.ok()) - { - FAPI_ERR("Error writing SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!", - scom_mode_pb_reg_addr[FIR_CEN_DMI]); - return rc; - } - ///////////////////////////////SW256413////////////////////////////// - ecmdDataBufferBase rx_set_bits(16); - ecmdDataBufferBase tx_set_bits(16); - ecmdDataBufferBase mask_bits( 16); + // Loop over all present MCS chiplets in the controller, to see if a reset is required + rc = fapiGetChildChiplets(master_parent_target,fapi::TARGET_TYPE_MCS_CHIPLET,mcs_chiplets, fapi::TARGET_STATE_PRESENT); + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if(rc){return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(!rc){ // An error from this means that there is no centaur attached. + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + if(l_attr_mss_init_state != ENUM_ATTR_MSS_INIT_STATE_COLD){ + reset_required = true; + } + }else{ + rc = FAPI_RC_SUCCESS; + } + } + } + if(!reset_required){ + return(rc); + } + FAPI_INF("IO CleanUp: Global Reset Required"); - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &master_target, chip_unit); - if (!rc.ok()){ - FAPI_ERR("Error retreiving MCS chiplet number, while setting bus id."); - return rc; - } - mask_bits.flushTo0(); - uint32_t rxbits = 0; - uint32_t txbits = 0; - // Tuleta has MCS4-7 corresponding to port DMI1 - // Brazos has MCS0-7 corresponding to port DMI0 and DMI1 - if(chip_unit == 0){ - rxbits = 0x0000; //bus_id: 0 group_id: 0 - txbits = 0x0100; //bus_id: 0 group_id: 32 - }else if(chip_unit == 1){ - rxbits = 0x0400; //bus_id: 1 group_id: 0 - txbits = 0x0500; //bus_id: 1 group_id: 32 - }else if(chip_unit == 2){ - rxbits = 0x0800; //bus_id: 2 group_id: 0 - txbits = 0x0900; //bus_id: 2 group_id: 32 - }else if(chip_unit == 3){ - rxbits = 0x0C00; //bus_id: 3 group_id: 0 - txbits = 0x0D00; //bus_id: 3 group_id: 32 - }else if(chip_unit == 4){ - rxbits = 0x0000; //bus_id: 0 group_id: 0 - txbits = 0x0100; //bus_id: 0 group_id: 32 - }else if(chip_unit == 5){ - rxbits = 0x0400; //bus_id: 1 group_id: 0 - txbits = 0x0500; //bus_id: 1 group_id: 32 - }else if(chip_unit == 6){ - rxbits = 0x0800; //bus_id: 2 group_id: 0 - txbits = 0x0900; //bus_id: 2 group_id: 32 - }else if(chip_unit == 7){ - rxbits = 0x0C00; //bus_id: 3 group_id: 0 - txbits = 0x0D00; //bus_id: 3 group_id: 32 - }else{ //If chip_unit is unkown, set return error - FAPI_ERR("Invalid io_cleanup HWP invocation . MCS chiplet number is unknown while setting the bus id."); - const fapi::Target & MASTER_TARGET = master_target; - FAPI_SET_HWP_ERROR(rc, IO_CLEANUP_INVALID_MCS_RC); - return rc; - } - rc_ecmd |= rx_set_bits.insertFromRight(rxbits, 0, 16); - rc_ecmd |= tx_set_bits.insertFromRight(txbits, 0, 16); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = GCR_write(master_target, master_interface, rx_id1_pg, master_group, 0, rx_set_bits, mask_bits,1,1);if (rc) {return(rc);} - rc = GCR_write(master_target, master_interface, tx_id1_pg, master_group, 0, tx_set_bits, mask_bits,1,1);if (rc) {return(rc);} - ///////////////////////////////SW256413////////////////////////////// + // + rc = FAPI_ATTR_GET(ATTR_PROC_EC_MSS_RECONFIG_POSSIBLE, &master_parent_target, l_attr_proc_ec_mss_reconfig_possible); if(rc){return rc;} + // Loop over all present MCS chiplets in the controller + // Turn off FIR propagator, Mask FIRs, and force channel fail + rc = fapiGetChildChiplets(master_parent_target,fapi::TARGET_TYPE_MCS_CHIPLET,mcs_chiplets, fapi::TARGET_STATE_PRESENT); + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if(rc){return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + memory_attached = true; + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(rc){ // An error from this means that there is no centaur attached. + memory_attached = false; + }else{ + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + } + // turn off the FIR propagator + if( l_attr_proc_ec_mss_reconfig_possible){ + rc_ecmd = data_buffer_64.setBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.setBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScomUnderMask(*i, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); if(rc) return rc; + }else{ + FAPI_ERR("This processor cannot go through a reconfig loop. Please upgrade to > DD1\n"); + const fapi::Target & PROC = master_parent_target; + FAPI_SET_HWP_ERROR(rc, RC_IO_CLEANUP_UNSUPPORTED); + return rc; + } + // Mask firs in the MCS + rc_ecmd = data_buffer_64.setBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScom(*i, MCS_MCIFIRMASK_0x02011843, data_buffer_64); if(rc) return rc; + // force a channel fail only if you are up to DMI ACTIVE state on this pair + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = data_buffer_64.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScomUnderMask(master_target, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); if(rc) return rc; + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = data_buffer_64.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64); + } + rc_ecmd = set_bits.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc=GCR_write(*i, master_interface, rx_fence_pg, master_group, 0, set_bits, set_bits, 1, 1); + if(rc) return rc; + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc=GCR_write(attached_cen_target, slave_interface, rx_fence_pg, slave_group, 0, set_bits, set_bits, 1, 1); + if(rc) return rc; + } + } + } + /// reset start + // pu + rc = fapiGetScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data_buffer_64); + if (!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!",scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); return rc;} + rc_ecmd = data_buffer_64.setBit(2,6); // Scom_mode_pb ,ioreset starts at bit 2 + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + rc = fapiPutScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data_buffer_64); + if (!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on master side(=%08X)!",scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); return rc;} - // NOW We clear FIRS.. need to see if we need to do this or some other procedure will do this . Bellows/Irving to respond + // cen + rc = fapiGetChildChiplets(master_parent_target,fapi::TARGET_TYPE_MCS_CHIPLET,mcs_chiplets, fapi::TARGET_STATE_PRESENT); + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if (!rc.ok()){FAPI_ERR("Error retreiving MCS chiplet number, while setting bus id.");return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(!rc){ // An error from this means that there is no centaur attached. + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + if((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE) ){ + rc_ecmd = data_buffer_64.flushTo0(); + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + rc = fapiGetScom(attached_cen_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data_buffer_64); + if(!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",scom_mode_pb_reg_addr[FIR_CEN_DMI]); return rc;} + rc_ecmd = data_buffer_64.setBit(2,1); // Scom_mode_pb ,ioreset starts at bit 2 + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + rc = fapiPutScom(attached_cen_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data_buffer_64); + if(!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",scom_mode_pb_reg_addr[FIR_CEN_DMI]); return rc;} + } + } + } + } + FAPI_INF("IO CleanUp: Global Reset Done"); + /// reset end - rc = clear_fir_reg(slave_target,FIR_CEN_DMI); - if(rc) - { - return(rc); - } - rc = clear_fir_reg(master_target,FIR_CP_IOMC0_P0); - if(rc) - { - return(rc); - } - return rc; + // Set Bus IDs, Clear FIRs, Turn on FIR Propagator + rc = fapiGetChildChiplets(master_parent_target,fapi::TARGET_TYPE_MCS_CHIPLET,mcs_chiplets, fapi::TARGET_STATE_PRESENT); + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if (!rc.ok()){FAPI_ERR("Error retreiving MCS chiplet number, while setting bus id.");return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + // Set Bus IDs + clear_bits.flushTo0(); + uint32_t rxbits = 0; + uint32_t txbits = 0; + // Tuleta has MCS4-7 corresponding to port DMI1 + // Brazos has MCS0-7 corresponding to port DMI0 and DMI1 + if(mcs_unit_id == 0){ + rxbits = 0x0000; //bus_id: 0 group_id: 0 + txbits = 0x0100; //bus_id: 0 group_id: 32 + }else if(mcs_unit_id == 1){ + rxbits = 0x0400; //bus_id: 1 group_id: 0 + txbits = 0x0500; //bus_id: 1 group_id: 32 + }else if(mcs_unit_id == 2){ + rxbits = 0x0800; //bus_id: 2 group_id: 0 + txbits = 0x0900; //bus_id: 2 group_id: 32 + }else if(mcs_unit_id == 3){ + rxbits = 0x0C00; //bus_id: 3 group_id: 0 + txbits = 0x0D00; //bus_id: 3 group_id: 32 + }else if(mcs_unit_id == 4){ + rxbits = 0x0000; //bus_id: 0 group_id: 0 + txbits = 0x0100; //bus_id: 0 group_id: 32 + }else if(mcs_unit_id == 5){ + rxbits = 0x0400; //bus_id: 1 group_id: 0 + txbits = 0x0500; //bus_id: 1 group_id: 32 + }else if(mcs_unit_id == 6){ + rxbits = 0x0800; //bus_id: 2 group_id: 0 + txbits = 0x0900; //bus_id: 2 group_id: 32 + }else if(mcs_unit_id == 7){ + rxbits = 0x0C00; //bus_id: 3 group_id: 0 + txbits = 0x0D00; //bus_id: 3 group_id: 32 + }else{ //If chip_unit is unkown, set return error + FAPI_ERR("Invalid io_cleanup HWP. MCS chiplet number is unknown while setting the bus id."); + const fapi::Target & TARGET = *i; + FAPI_SET_HWP_ERROR(rc, IO_CLEANUP_POST_RESET_MCS_UNIT_ID_FAIL); + return rc; + } + rc_ecmd |= rx_set_bits.insertFromRight(rxbits, 0, 16); + rc_ecmd |= tx_set_bits.insertFromRight(txbits, 0, 16); + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + rc = GCR_write(*i, master_interface, rx_id1_pg, master_group, 0, rx_set_bits, clear_bits,1,1); + if(rc){ + FAPI_INF("io_cleanup rx putscom fail"); + return(rc); + } + rc = GCR_write(*i, master_interface, tx_id1_pg, master_group, 0, tx_set_bits, clear_bits,1,1); + if(rc){ + FAPI_INF("in_cleanup tx putscom fail"); + return(rc); + } + memory_attached = true; + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(rc){ // An error from this means that there is no centaur attached. + memory_attached = false; + }else{ + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + } + // Clear FIR on MCS and CEN (DMI FIR) + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc = clear_fir_reg(attached_cen_target,FIR_CEN_DMI); + if(rc){return(rc);} + } + rc = clear_fir_reg(*i,FIR_CP_IOMC0_P0); + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + if(rc){return(rc);} + // # cen mbi fir + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_FIR_0x02010800, data_buffer_64); + if(rc) return rc; + // # cen mbicrc syndromes + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CRCSYN_0x0201080C, data_buffer_64); + if(rc) return rc; + // # cen mbicfg configuration register + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64); + if(rc) return rc; + // # cen dmi fir + rc = fapiPutScom(attached_cen_target, CENTAUR_CEN_DMIFIR_0x02010400, data_buffer_64); + if(rc) return rc; + } + rc = fapiPutScom(*i, MCS_MCIFIR_0x02011840, data_buffer_64); + if(rc) return rc; + // # pu mcicrcsyn + rc = fapiPutScom(*i, MCS_MCICRCSYN_0x0201184C, data_buffer_64); + if(rc) return rc; + // # pu mcicfg + rc = fapiPutScom(*i, MCS_MCICFG_0x0201184A, data_buffer_64); + if(rc) return rc; + // #dmi fir + rc = fapiPutScom(*i, IOMC0_BUSCNTL_FIR_0x02011A00, data_buffer_64); + if(rc) return rc; + //Turn off indication of valid MCS for OCC + rc = fapiPutScom(*i, MCS_MCFGPR_0x02011802, data_buffer_64); + if(rc) return rc; + // turn on the FIR propagator so FIR bits shut down the DMI + if(l_attr_proc_ec_mss_reconfig_possible){ + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = data_buffer_64.clearBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.setBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScomUnderMask(*i, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); + if(rc) return rc; + }else{ + FAPI_ERR("This processor cannot go through a reconfig loop. Please upgrade to > DD1\n"); + const fapi::Target & PROC = master_parent_target; + FAPI_SET_HWP_ERROR(rc, RC_IO_CLEANUP_UNSUPPORTED); + return rc; + } + } + } + FAPI_INF("IO CleanUp: Done"); + return rc; } // Cleans up for Centaur Reconfig or Abus hot plug case -ReturnCode io_cleanup(const Target &master_target,const Target &slave_target){ - ReturnCode rc; - io_interface_t master_interface,slave_interface; - uint32_t master_group=0; - uint32_t slave_group=0; +ReturnCode io_cleanup(const Target &master_target){ + ReturnCode rc; + io_interface_t master_interface; + uint32_t master_group = 0; + // This is a DMI/MC bus + if( master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET ){ + FAPI_DBG("This is a DMI bus using base DMI scom address"); + master_interface = CP_IOMC0_P0; // base scom for MC bus + master_group = 3; // Design requires us to do this as per scom map and layout + rc=do_cleanup(master_target,master_interface,master_group); + if(rc){ + FAPI_INF("io_cleanup exited early."); + return rc; + } + } - // This is a DMI/MC bus - if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){ - FAPI_DBG("This is a DMI bus using base DMI scom address"); - master_interface=CP_IOMC0_P0; // base scom for MC bus - slave_interface=CEN_DMI; // Centaur scom base - master_group=3; // Design requires us to do this as per scom map and layout - slave_group=0; - rc=do_cleanup(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); - if(rc) return rc; - } - //This is an A Bus - else if( (master_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){ - // This procedure only supports DMI for now - } - else{ - const Target &MASTER_TARGET = master_target; - const Target &SLAVE_TARGET = slave_target; - FAPI_ERR("Invalid io_cleanup HWP invocation . Pair of targets dont belong to DMI or A bus instances"); - FAPI_SET_HWP_ERROR(rc, IO_CLEANUP_INVALID_INVOCATION_RC); - } - return rc; + //This is an A Bus + else if( master_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT ){ + // This procedure only supports DMI for now + } + else{ + const Target &MASTER_TARGET = master_target; + FAPI_ERR("Invalid io_cleanup HWP invocation . Pair of targets dont belong to DMI or A bus instances"); + FAPI_SET_HWP_ERROR(rc, IO_CLEANUP_INVALID_MCS_RC); + } + return rc; } diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup.H b/src/usr/hwpf/hwp/bus_training/io_cleanup.H index 214060283..bfae99447 100644 --- a/src/usr/hwpf/hwp/bus_training/io_cleanup.H +++ b/src/usr/hwpf/hwp/bus_training/io_cleanup.H @@ -21,35 +21,41 @@ /* */ /* IBM_PROLOG_END_TAG */ -//$Id: io_cleanup.H,v 1.2 2013/12/10 09:22:24 varkeykv Exp $
+//$Id: io_cleanup.H,v 1.3 2014/06/06 19:43:49 steffen Exp $
#ifndef IO_CLEANUP_H_
#define IO_CLEANUP_H_
#include <fapi.H>
+#include <p8_scom_addresses.H>
#include "io_clear_firs.H"
using namespace fapi;
+ CONST_UINT64_T( CENTAUR_MBI_CFG_0x0201080A , ULL(0x0201080A) );
+ CONST_UINT64_T( CENTAUR_MBI_FIR_0x02010800 , ULL(0x02010800) );
+ CONST_UINT64_T( CENTAUR_MBI_CRCSYN_0x0201080C , ULL(0x0201080C) );
+ CONST_UINT64_T( CENTAUR_CEN_DMIFIR_0x02010400 , ULL(0x02010400) );
+
/**
- * io_cleanup func pointer Typedef for hostboot
+ * io_cleanup func pointer Typedef for hostboot
*
*/
-typedef fapi::ReturnCode (*io_cleanup_FP_t)(const fapi::Target &,const fapi::Target &);
+typedef fapi::ReturnCode (*io_cleanup_FP_t)(const fapi::Target &);
extern "C"
{
/**
- * io_cleanup
+ * io_cleanup
*
- * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric
+ * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric
* slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric
- * while these are called master or slave... I actually do a check in the code to see
+ * while these are called master or slave... I actually do a check in the code to see
* whether these are actually master chips by reading a GCR master_mode bit
- * and accordingly will perform a target swap if required
+ * and accordingly will perform a target swap if required
* @return ReturnCode
*/
-fapi::ReturnCode io_cleanup(const fapi::Target &master_target,const fapi::Target & slave_target);
+fapi::ReturnCode io_cleanup(const fapi::Target &master_target);
} // extern "C"
diff --git a/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml b/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml index b7db5e430..ed2d5f526 100755 --- a/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml +++ b/src/usr/hwpf/hwp/bus_training/io_cleanup_errors.xml @@ -20,27 +20,32 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: io_cleanup_errors.xml,v 1.5 2014/05/16 18:33:48 dcrowell Exp $ --> +<!-- $Id: io_cleanup_errors.xml,v 1.6 2014/06/06 19:37:30 steffen Exp $ --> <hwpErrors> <hwpError> - <rc>IO_CLEANUP_INVALID_INVOCATION_RC</rc> - <description>io_cleanup invoked with wrong pair of targets</description> + <rc>IO_CLEANUP_INVALID_MCS_RC</rc> + <description>io_cleanup invoked with invalid mcs target</description> <ffdc>MASTER_TARGET</ffdc> - <ffdc>SLAVE_TARGET</ffdc> <callout> <procedure>CODE</procedure> <priority>HIGH</priority> </callout> </hwpError> - + <!-- *********************************************************************** --> <hwpError> - <rc>IO_CLEANUP_INVALID_MCS_RC</rc> - <description>io_cleanup invoked with invalid mcs target</description> - <ffdc>MASTER_TARGET</ffdc> - <ffdc>chip_unit</ffdc> + <rc>RC_IO_CLEANUP_UNSUPPORTED</rc> + <description>Processor Hardware does not support reconfiguration loops. For Venice and Murano, DD2.0 and greater hardware support this function</description> + <deconfigure><target>PROC</target></deconfigure> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>IO_CLEANUP_POST_RESET_MCS_UNIT_ID_FAIL</rc> + <description>io cleanup was unable to determine the correct mcs unit id to set the bus id. </description> + <ffdc>TARGET</ffdc> <callout> <procedure>CODE</procedure> <priority>HIGH</priority> </callout> </hwpError> + <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C index 9d3dd258b..e9b6b9e51 100644 --- a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C +++ b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C @@ -20,7 +20,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_enable_reconfig.C,v 1.12 2014/05/14 18:08:38 jdsloat Exp $ +// $Id: proc_enable_reconfig.C,v 1.15 2014/06/20 18:58:18 steffen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_enable_reconfig.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2013 @@ -59,228 +59,334 @@ #include <fapi.H> #include "proc_enable_reconfig.H" #include <p8_scom_addresses.H> -#include <io_cleanup.H> +#include <cen_scom_addresses.H> +#include "gcr_funcs.H" extern "C" { - using namespace fapi; - - ReturnCode proc_enable_reconfig(fapi::Target & i_target_pu_mcs, fapi::Target & i_target_cen) { - - ReturnCode rc; - ecmdDataBufferBase mask_buffer_64(64); - ecmdDataBufferBase data_buffer_64(64); - uint8_t l_attr_mss_init_state; - uint8_t cold=true; - uint8_t dmi_active=false; - uint8_t clocks_on=false; - Target l_target_pu; - uint8_t l_attr_proc_ec_mss_reconfig_possible; - uint32_t rc_ecmd; - - // determine how far into the IPL we have gone - rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &i_target_cen, l_attr_mss_init_state); - if(rc) return rc; - - if(l_attr_mss_init_state != ENUM_ATTR_MSS_INIT_STATE_COLD ) - cold=false; - - if(l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON ) - clocks_on=true; - - if(l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE ) { - clocks_on=true; - dmi_active=true; - } - - - if(cold) { // If the centaur has not made it past cold, then exit with success - return rc; - } - - rc= fapiGetParentChip(i_target_pu_mcs, l_target_pu); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_PROC_EC_MSS_RECONFIG_POSSIBLE, &l_target_pu, l_attr_proc_ec_mss_reconfig_possible); - if(rc) return rc; - - if(dmi_active) { - - if(l_attr_proc_ec_mss_reconfig_possible) { - // turn off the FIR propagator - rc_ecmd = data_buffer_64.setBit(42); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = mask_buffer_64.setBit(42); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - - rc = fapiPutScomUnderMask(i_target_pu_mcs, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); - if(rc) return rc; - - } - else { - FAPI_ERR("This processor cannot go through a reconfig loop. Please upgrade to > DD1\n"); - const fapi::Target & PROC = l_target_pu; - FAPI_SET_HWP_ERROR(rc, RC_PROC_ENABLE_RECONFIG_UNSUPPORTED); - return rc; - } - } - - // mask firs in the MCS - rc_ecmd = data_buffer_64.setBit(0,64); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = fapiPutScom(i_target_pu_mcs, MCS_MCIFIRMASK_0x02011843, data_buffer_64); - if(rc) return rc; - - - // force a channel fail only if you are up to DMI ACTIVE state on this pair - rc_ecmd = data_buffer_64.clearBit(0,64); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = data_buffer_64.setBit(0); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = mask_buffer_64.clearBit(0,64); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = mask_buffer_64.setBit(0); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - - if(dmi_active) { - rc = fapiPutScomUnderMask(i_target_pu_mcs, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); - if(rc) return rc; - } - - rc_ecmd = data_buffer_64.clearBit(0,64); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = data_buffer_64.setBit(0); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - if(dmi_active) { - rc = fapiPutScom(i_target_cen, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64); - if(rc) return rc; - } - - // perform IO cleanup on active dmi channels - if(dmi_active) { - - FAPI_INF("mcs %s / cen %s : types %d %d\n", i_target_pu_mcs.toEcmdString(), i_target_cen.toEcmdString(), i_target_pu_mcs.getType(), i_target_cen.getType() ); - - rc = io_cleanup(i_target_pu_mcs, i_target_cen ); - if(rc) return rc; - } - - if(clocks_on ){ - - rc_ecmd = data_buffer_64.clearBit(0,64); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - - // # cen mbi fir - rc = fapiPutScom(i_target_cen, CENTAUR_MBI_FIR_0x02010800, data_buffer_64); - if(rc) return rc; - - // # cen mbicrc syndromes - rc = fapiPutScom(i_target_cen, CENTAUR_MBI_CRCSYN_0x0201080C, data_buffer_64); - if(rc) return rc; - - // # cen mbicfg configuration register - rc = fapiPutScom(i_target_cen, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64); - if(rc) return rc; - - // # cen dmi fir - rc = fapiPutScom(i_target_cen, CENTAUR_CEN_DMIFIR_0x02010400, data_buffer_64); - if(rc) return rc; - - rc = fapiPutScom(i_target_pu_mcs, MCS_MCIFIR_0x02011840, data_buffer_64); - if(rc) return rc; - - // # pu mcicrcsyn - rc = fapiPutScom(i_target_pu_mcs, MCS_MCICRCSYN_0x0201184C, data_buffer_64); - if(rc) return rc; - - // # pu mcicfg - rc = fapiPutScom(i_target_pu_mcs, MCS_MCICFG_0x0201184A, data_buffer_64); - if(rc) return rc; - - // #dmi fir - rc = fapiPutScom(i_target_pu_mcs, IOMC0_BUSCNTL_FIR_0x02011A00, data_buffer_64); - if(rc) return rc; - - //Turn off indication of valid MCS for OCC - rc = fapiPutScom( i_target_pu_mcs, MCS_MCFGPR_0x02011802, data_buffer_64); - if(rc) return rc; - - } - - if(dmi_active) { - ecmdDataBufferBase mask_buffer_64(64); - ecmdDataBufferBase data_buffer_64(64); - - // turn on the FIR propagator so FIR bits shut down the DMI - if(l_attr_proc_ec_mss_reconfig_possible) { - rc_ecmd = data_buffer_64.clearBit(0,64); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = mask_buffer_64.clearBit(0,64); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = data_buffer_64.clearBit(42); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc_ecmd = mask_buffer_64.setBit(42); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - return(rc); - } - rc = fapiPutScomUnderMask(i_target_pu_mcs, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); - if(rc) return rc; - } - else { - FAPI_ERR("This processor cannot go through a reconfig loop. Please upgrade to > DD1\n"); - const fapi::Target & PROC = l_target_pu; - FAPI_SET_HWP_ERROR(rc, RC_PROC_ENABLE_RECONFIG_UNSUPPORTED); - return rc; - } - } - - /* - l_attr_mss_init_state=ENUM_ATTR_MSS_INIT_STATE_COLD; // who knows where we might end on another pass through - rc = FAPI_ATTR_SET(ATTR_MSS_INIT_STATE, &i_target_cen, l_attr_mss_init_state); - */ - return rc; - - } + using namespace fapi; + +// For clearing the FIR mask , used by io run training +// As per Irving , it should be ok to clear all FIRs here since we will scom init , also we dont touch mask values +fapi::ReturnCode clear_fir_reg(const fapi::Target &i_target,fir_io_interface_t i_chip_interface){ + ReturnCode rc; + ecmdDataBufferBase data(64); + FAPI_INF("Clear Fir Reg:In the Clear FIR RW register function on %s", i_target.toEcmdString()); + rc = fapiPutScom(i_target, fir_rw_reg_addr[i_chip_interface], data); + if (!rc.ok()){FAPI_ERR("Error writing FIR mask register (=%08X)!",fir_rw_reg_addr[i_chip_interface]);} + return(rc); +} + +// Cleans up for Centaur Reconfig +ReturnCode proc_enable_reconfig_cleanup(const Target &master_target){ + ReturnCode rc; + io_interface_t master_interface; + master_interface = CP_IOMC0_P0; // base scom for MC bus + uint32_t master_group = 3; // Design requires us to do this as per scom map and layout + uint32_t rc_ecmd = 0; + ecmdDataBufferBase set_bits(16); + ecmdDataBufferBase clear_bits(16); + ecmdDataBufferBase mask_buffer_64(64); + ecmdDataBufferBase data_buffer_64(64); + ecmdDataBufferBase rx_set_bits(16); + ecmdDataBufferBase tx_set_bits(16); + bool memory_attached = false; + bool reset_required = false; + uint8_t l_attr_mss_init_state = 0x0; + uint8_t l_attr_proc_ec_mss_reconfig_possible = 0x0; + uint8_t mcs_unit_id = 0x0; + uint8_t mcs_unit_lower_limit = 0; + uint8_t mcs_unit_upper_limit = 3; + io_interface_t slave_interface = CEN_DMI; // Centaur scom base + uint32_t slave_group = 0x0; + // vector to hold MCS chiplet targets + std::vector<fapi::Target> mcs_chiplets; + fapi::Target master_parent_target; + fapi::Target attached_cen_target; + + // Verify MCS Chiplet Type + if(master_target.getType() != fapi::TARGET_TYPE_MCS_CHIPLET){ + const Target &MASTER_TARGET = master_target; + FAPI_ERR("Invalid io_cleanup HWP invocation . Pair of targets dont belong to DMI bus instances"); + FAPI_SET_HWP_ERROR(rc, PROC_ENABLE_RECONFIG_CLEANUP_INVALID_MCS_RC); + return(rc); + } + + // Find DMI0 or DMI1 controller limits based on passed in target. + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &master_target, mcs_unit_id); // read chip unit number + if(rc){return rc;} + if(mcs_unit_id == 0){ // DMI0, not on Tuleta, on Brazos + mcs_unit_lower_limit = 0; + mcs_unit_upper_limit = 3; + }else if(mcs_unit_id == 4){ // DMI1, on Tuleta and Brazos + mcs_unit_lower_limit = 4; + mcs_unit_upper_limit = 7; + }else{ + return rc; + } + + // Get Master Parent Target + rc = fapiGetParentChip(master_target, master_parent_target); if(rc){return rc;} + // Get mcs_chiplets list on processor + rc = fapiGetChildChiplets(master_parent_target,fapi::TARGET_TYPE_MCS_CHIPLET,mcs_chiplets, fapi::TARGET_STATE_PRESENT); if(rc){return rc;} + + // Loop over all present MCS chiplets in the controller, to see if a reset is required + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if(rc){return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(!rc){ // An error from this means that there is no centaur attached. + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + if(l_attr_mss_init_state != ENUM_ATTR_MSS_INIT_STATE_COLD){ + reset_required = true; + break; + } + }else{ + rc = FAPI_RC_SUCCESS; + } + } + } + if(!reset_required){ + return(rc); + } + + FAPI_INF("CleanUp: Global Reset Required"); + + // Get l_attr_proc_ec_mss_reconfig_possible, an attribute that states whether the part is DD1(0) or DD2(1) + rc = FAPI_ATTR_GET(ATTR_PROC_EC_MSS_RECONFIG_POSSIBLE, &master_parent_target, l_attr_proc_ec_mss_reconfig_possible); if(rc){return rc;} + if(!l_attr_proc_ec_mss_reconfig_possible){ + FAPI_ERR("This processor cannot go through a reconfig loop. Please upgrade to > DD1\n"); + const fapi::Target & PROC = master_parent_target; + FAPI_SET_HWP_ERROR(rc, RC_PROC_ENABLE_RECONFIG_CLEANUP_UNSUPPORTED); + return rc; + } + + // Loop over all present MCS chiplets in the controller + // Turn off FIR propagator, Mask FIRs, and force channel fail + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if(rc){return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + memory_attached = true; + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(rc){ // An error from this means that there is no centaur attached. + memory_attached = false; + }else{ + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + } + // turn off the FIR propagator + rc_ecmd = data_buffer_64.setBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.setBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScomUnderMask(*i, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); if(rc) return rc; + + // Mask firs in the MCS, We do not mask firs on Centaur as they should not matter + rc_ecmd = data_buffer_64.setBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScom(*i, MCS_MCIFIRMASK_0x02011843, data_buffer_64); if(rc) return rc; + + // Force a channel fail on mcs and on Centaur if possible + // *** + // *** Causes too many bus errors on Centaur side. This is okay as long as the function makes it to clearing the firs after reset. + // *** If GCR hang after reset happens, the function will exit early before clearing firs and cause too many bus errors + // *** GCR hang is fixed by doing global reset! Since global reset also does a GCR reset. + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = data_buffer_64.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScomUnderMask(master_target, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); if(rc) return rc; + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = data_buffer_64.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64); + if(rc) return rc; + } + + // Set fence bits on mcs and on Centaur if possible + rc_ecmd = set_bits.setBit(0); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = GCR_write(*i, master_interface, rx_fence_pg, master_group, 0, set_bits, set_bits, 1, 1); + if(rc) return rc; + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc=GCR_write(attached_cen_target, slave_interface, rx_fence_pg, slave_group, 0, set_bits, set_bits, 1, 1); + if(rc) return rc; + } + } + } + + /// reset start + // pu + rc = fapiGetScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data_buffer_64); + if (!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on master side(%08X)!",scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); return rc;} + rc_ecmd = data_buffer_64.setBit(2,6); // Scom_mode_pb ,ioreset starts at bit 2, will reset every mcs on the memory controller + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + rc = fapiPutScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data_buffer_64); + if (!rc.ok()){FAPI_ERR("Error Writing SCOM mode PB register for ioreset_hard_bus0 on master side(%08X)!",scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); return rc;} + + // cen + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if (!rc.ok()){FAPI_ERR("Error retreiving MCS chiplet number, while resetting Centaurs.");return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(!rc){ // An error from this means that there is no centaur attached. + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + if((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE) ){ + rc_ecmd = data_buffer_64.flushTo0(); + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + rc = fapiGetScom(attached_cen_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data_buffer_64); + if(!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",scom_mode_pb_reg_addr[FIR_CEN_DMI]); return rc;} + rc_ecmd = data_buffer_64.setBit(2,1); // Scom_mode_pb ,ioreset starts at bit 2 + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + rc = fapiPutScom(attached_cen_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data_buffer_64); + if(!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",scom_mode_pb_reg_addr[FIR_CEN_DMI]); return rc;} + } + } + } + } + FAPI_INF("CleanUp: Global Reset Done"); + /// reset end + + // Set Bus IDs, Clear FIRs, Turn on FIR Propagator + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){ + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id); // read chip unit number + if (!rc.ok()){FAPI_ERR("Error retreiving MCS chiplet number, while setting bus id.");return rc;} + if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){ //To limit these actions to a single DMI controller + // Set Bus IDs -- Must rewrite bus ids after reset since reset sets all bus ids to 0 and there would be contention on the GCR ring + clear_bits.flushTo0(); + uint32_t rxbits = 0; + uint32_t txbits = 0; + // Tuleta has MCS4-7 corresponding to port DMI1 + // Brazos has MCS0-7 corresponding to port DMI0 and DMI1 + if(mcs_unit_id == 0){ + rxbits = 0x0000; //bus_id: 0 group_id: 0 + txbits = 0x0100; //bus_id: 0 group_id: 32 + }else if(mcs_unit_id == 1){ + rxbits = 0x0400; //bus_id: 1 group_id: 0 + txbits = 0x0500; //bus_id: 1 group_id: 32 + }else if(mcs_unit_id == 2){ + rxbits = 0x0800; //bus_id: 2 group_id: 0 + txbits = 0x0900; //bus_id: 2 group_id: 32 + }else if(mcs_unit_id == 3){ + rxbits = 0x0C00; //bus_id: 3 group_id: 0 + txbits = 0x0D00; //bus_id: 3 group_id: 32 + }else if(mcs_unit_id == 4){ + rxbits = 0x0000; //bus_id: 0 group_id: 0 + txbits = 0x0100; //bus_id: 0 group_id: 32 + }else if(mcs_unit_id == 5){ + rxbits = 0x0400; //bus_id: 1 group_id: 0 + txbits = 0x0500; //bus_id: 1 group_id: 32 + }else if(mcs_unit_id == 6){ + rxbits = 0x0800; //bus_id: 2 group_id: 0 + txbits = 0x0900; //bus_id: 2 group_id: 32 + }else if(mcs_unit_id == 7){ + rxbits = 0x0C00; //bus_id: 3 group_id: 0 + txbits = 0x0D00; //bus_id: 3 group_id: 32 + }else{ //If chip_unit is unkown, set return error + FAPI_ERR("Invalid io_cleanup HWP. MCS chiplet number is unknown while setting the bus id."); + const fapi::Target & TARGET = *i; + FAPI_SET_HWP_ERROR(rc, PROC_ENABLE_RECONFIG_CLEANUP_POST_RESET_MCS_UNIT_ID_FAIL); + return rc; + } + rc_ecmd |= rx_set_bits.insertFromRight(rxbits, 0, 16); + rc_ecmd |= tx_set_bits.insertFromRight(txbits, 0, 16); + if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);} + // We do not need to rewrite bus ids for Centaur. + // Write RX bus id on MCS + rc = GCR_write(*i, master_interface, rx_id1_pg, master_group, 0, rx_set_bits, clear_bits,1,1); + if(rc){ + FAPI_INF("io_cleanup rx putscom fail"); + return(rc); + } + // Write TX bus id on MCS + rc = GCR_write(*i, master_interface, tx_id1_pg, master_group, 0, tx_set_bits, clear_bits,1,1); + if(rc){ + FAPI_INF("in_cleanup tx putscom fail"); + return(rc); + } + memory_attached = true; + rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT); + if(rc){ // An error from this means that there is no centaur attached. + memory_attached = false; + }else{ + rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state); if(rc) return rc; + } + // Clear FIR on MCS and CEN (DMI FIR) + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc = clear_fir_reg(attached_cen_target,FIR_CEN_DMI); + if(rc){return(rc);} + } + rc = clear_fir_reg(*i,FIR_CP_IOMC0_P0); + if(rc){return(rc);} + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + // # cen mbi fir + if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){ + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_FIR_0x02010800, data_buffer_64); + if(rc) return rc; + // # cen mbicrc syndromes + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CRCSYN_0x0201080C, data_buffer_64); + if(rc) return rc; + // # cen mbicfg configuration register + rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64); + if(rc) return rc; + // # cen dmi fir + rc = fapiPutScom(attached_cen_target, CENTAUR_CEN_DMIFIR_0x02010400, data_buffer_64); + if(rc) return rc; + } + rc = fapiPutScom(*i, MCS_MCIFIR_0x02011840, data_buffer_64); + if(rc) return rc; + // # pu mcicrcsyn + rc = fapiPutScom(*i, MCS_MCICRCSYN_0x0201184C, data_buffer_64); + if(rc) return rc; + // # pu mcicfg + rc = fapiPutScom(*i, MCS_MCICFG_0x0201184A, data_buffer_64); + if(rc) return rc; + // # dmi fir + rc = fapiPutScom(*i, IOMC0_BUSCNTL_FIR_0x02011A00, data_buffer_64); + if(rc) return rc; + //Turn off indication of valid MCS for OCC + rc = fapiPutScom(*i, MCS_MCFGPR_0x02011802, data_buffer_64); + if(rc) return rc; + + // Turn on the FIR propagator so FIR bits shut down the DMI + rc_ecmd = data_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.clearBit(0,64); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = data_buffer_64.clearBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc_ecmd = mask_buffer_64.setBit(42); + if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);} + rc = fapiPutScomUnderMask(*i, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); + if(rc) return rc; + } + } + FAPI_INF("CleanUp: Done"); + return rc; +} + + +ReturnCode proc_enable_reconfig(fapi::Target & i_target_pu_mcs) { + ReturnCode rc; + uint8_t mcs_unit_id = 0x0; // Valid values for DMI0 (0-3) and DMI1 (4-7) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_pu_mcs, mcs_unit_id); // read mcs unit id value + if(rc){return rc;} + if((mcs_unit_id == 0) || (mcs_unit_id == 4) ){ // calls proc_enable_reconfig_cleanup only if mcs unit id is 0 or 4 (beginning of each memory controller) + FAPI_INF("mcs %s : type %d\n", i_target_pu_mcs.toEcmdString(), i_target_pu_mcs.getType() ); + rc = proc_enable_reconfig_cleanup(i_target_pu_mcs); + if(rc) return rc; + } + return rc; +} } // extern C diff --git a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H index dbb1590f2..e7110393f 100644 --- a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H +++ b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H @@ -20,7 +20,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_enable_reconfig.H,v 1.3 2013/11/11 21:29:36 bellows Exp $ +// $Id: proc_enable_reconfig.H,v 1.6 2014/06/20 18:58:18 steffen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_enable_reconfig.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2013 @@ -52,28 +52,29 @@ #include <fapi.H> #include <p8_scom_addresses.H> +#include "io_clear_firs.H" -typedef fapi::ReturnCode (*proc_enable_reconfig_FP_t)(fapi::Target & i_target_pu_mcs, fapi::Target & i_target_cen); + using namespace fapi; + + CONST_UINT64_T( CENTAUR_MBI_CFG_0x0201080A , ULL(0x0201080A) ); + CONST_UINT64_T( CENTAUR_MBI_FIR_0x02010800 , ULL(0x02010800) ); + CONST_UINT64_T( CENTAUR_MBI_CRCSYN_0x0201080C , ULL(0x0201080C) ); + CONST_UINT64_T( CENTAUR_CEN_DMIFIR_0x02010400 , ULL(0x02010400) ); + +typedef fapi::ReturnCode (*proc_enable_reconfig_FP_t)(fapi::Target & i_target_pu_mcs); extern "C" { - using namespace fapi; - - CONST_UINT64_T( CENTAUR_MBI_CFG_0x0201080A , ULL(0x0201080A) ); - CONST_UINT64_T( CENTAUR_MBI_FIR_0x02010800 , ULL(0x02010800) ); - CONST_UINT64_T( CENTAUR_MBI_CRCSYN_0x0201080C , ULL(0x0201080C) ); - CONST_UINT64_T( CENTAUR_CEN_DMIFIR_0x02010400 , ULL(0x02010400) ); /** - * @brief proc_clear_firs procedure. Turn off FIR spreading and causes a channel fail + * @brief proc_enable_reconfig procedure. Reset memory controller to known state which includes masking/clearing FIRs, causing a channel fails, and global resetting the memory controller and gcr ring. * - * @param[in] std::vector<fapi::Target> i_target_mcs, // an MCS with an attached centaur - * @param[in] std::vector<fapi::Target> i_target_cen, // The associated centaur + * @param[in] fapi::Target i_target_mcs, // an MCS with an attached centaur * * @return ReturnCode */ - ReturnCode proc_enable_reconfig(fapi::Target & i_target_pu_mcs, fapi::Target & i_target_cen); + ReturnCode proc_enable_reconfig(fapi::Target & i_target_pu_mcs); } // extern "C" diff --git a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig_errors.xml b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig_errors.xml index ceff427c0..c19490a78 100644 --- a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig_errors.xml +++ b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig_errors.xml @@ -20,19 +20,37 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_enable_reconfig_errors.xml,v 1.2 2014/02/19 13:45:27 bellows Exp $ --> +<!-- $Id: proc_enable_reconfig_errors.xml,v 1.6 2014/06/20 21:01:32 dcrowell Exp $ --> <!-- Error definitions for proc_enable_reconfig procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_ENABLE_RECONFIG_UNSUPPORTED</rc> + <rc>PROC_ENABLE_RECONFIG_CLEANUP_INVALID_MCS_RC</rc> + <description>io_cleanup invoked with invalid mcs target</description> + <ffdc>MASTER_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_ENABLE_RECONFIG_CLEANUP_UNSUPPORTED</rc> <description>Processor Hardware does not support reconfiguration loops. For Venice and Murano, DD2.0 and greater hardware support this function</description> <callout> <target>PROC</target> <priority>HIGH</priority> </callout> - <deconfigure> - <target>PROC</target> - </deconfigure> </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>PROC_ENABLE_RECONFIG_CLEANUP_POST_RESET_MCS_UNIT_ID_FAIL</rc> + <description>io cleanup was unable to determine the correct mcs unit id to set the bus id. </description> + <ffdc>TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> </hwpErrors> |
