diff options
3 files changed, 231 insertions, 27 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C index 4bda7081e..5e085638e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C @@ -61,6 +61,10 @@ template<> fapi2::ReturnCode after_memdiags( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { fapi2::ReturnCode l_rc; + fapi2::buffer<uint64_t> dsm0_buffer; + uint64_t rd_tag_delay = 0; + uint64_t wr_done_delay = 0; + uint64_t mnfg_flag = 0; for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target)) { @@ -70,14 +74,26 @@ fapi2::ReturnCode after_memdiags( const fapi2::Target<TARGET_TYPE_MCBIST>& i_tar fir::reg<MCA_MBACALFIRQ> l_cal_fir_reg(p, l_rc); FAPI_TRY(l_rc, "unable to create fir::reg for %d", MCA_MBACALFIRQ); + // Read out the wr_done and rd_tag delays and find min + // and set the RCD Protect Time to this value + FAPI_TRY (mss::read_dsm0q_register(p, dsm0_buffer) ); + mss::get_wrdone_delay(dsm0_buffer, wr_done_delay); + mss::get_rdtag_delay(dsm0_buffer, rd_tag_delay); + const auto rcd_protect_time = std::min(wr_done_delay, rd_tag_delay); + FAPI_TRY (mss::change_rcd_protect_time(p, rcd_protect_time) ); + l_ecc64_fir_reg.checkstop<MCA_FIR_MAINLINE_AUE>() .recoverable_error<MCA_FIR_MAINLINE_UE>() .checkstop<MCA_FIR_MAINLINE_IAUE>() .recoverable_error<MCA_FIR_MAINLINE_IUE>(); - // TODO RTC:165157 check for manufacturing flags and don't unmask this if - // thresholds policy is enabled. - l_ecc64_fir_reg.recoverable_error<MCA_FIR_MAINTENANCE_IUE>(); + // If MNFG FLAG Threshhold is enabled skip IUE unflagging + FAPI_TRY (mss::mnfg_flags(mnfg_flag) ); + + if (mnfg_flag != fapi2::ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) + { + l_ecc64_fir_reg.recoverable_error<MCA_FIR_MAINTENANCE_IUE>(); + } l_cal_fir_reg.recoverable_error<MCA_MBACALFIRQ_PORT_FAIL>(); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 160800f81..d660c4631 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -228,8 +228,12 @@ class portTraits<fapi2::TARGET_TYPE_MCA> CAL3Q_ALL_PERIODIC_LENGTH_LEN = MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN, CAL3Q_FREEZE_ON_PARITY_ERROR_DIS = MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS, - DSM0Q_CFG_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY, - DSM0Q_CFG_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, + DSM0Q_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY, + DSM0Q_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, + DSM0Q_WRDONE_DLY = MCA_MBA_DSM0Q_CFG_WRDONE_DLY, + DSM0Q_WRDONE_DLY_LEN = MCA_MBA_DSM0Q_CFG_WRDONE_DLY_LEN, + FARB0Q_RCD_PROTECTION_TIME = MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME, + FARB0Q_RCD_PROTECTION_TIME_LEN = MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN, PER_ZCAL_ENA_RANK = MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK, PER_ZCAL_ENA_RANK_LEN = MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK_LEN, @@ -264,28 +268,130 @@ class portTraits<fapi2::TARGET_TYPE_MCA> }; /// -/// @brief Read the rdtag delay value +/// @brief Read the data state machine register /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the port /// @param[in] i_target the target -/// @param[out] o_delay RDTAG_DLY value (in cycles) +/// @param[out] o_delay the buffer to write the register data into /// @return FAPI2_RC_SUCCESS if and only if ok /// template< fapi2::TargetType T, typename TT = portTraits<T> > -fapi2::ReturnCode read_rdtag_delay( const fapi2::Target<T>& i_target, uint64_t& o_delay ) +fapi2::ReturnCode read_dsm0q_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_delay ) +{ + FAPI_TRY( mss::getScom(i_target, TT::DSM0Q_REG, o_delay) ); + + FAPI_INF( "Data State machine register is %d for %s", uint64_t(o_delay), mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write to dsm0q register +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_delay the buffer that holds the register data to write +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode write_dsm0q_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t> i_delay ) +{ + FAPI_INF( "Change Data State machine register to %d for %s", i_delay, mss::c_str(i_target) ); + + FAPI_TRY( mss::putScom(i_target, TT::DSM0Q_REG, i_delay) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Get the wrdone delay value from DSM0Q +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_data the data buffer containing the DSM0Q register +/// @param[out] o_delay WRDONE_DLY value (in cycles) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void get_wrdone_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay ) +{ + i_data.template extractToRight<TT::DSM0Q_WRDONE_DLY, TT::DSM0Q_WRDONE_DLY_LEN>(o_delay); + + FAPI_INF( "WRDONE_DLY: %d ", uint64_t(o_delay) ); +} + +/// +/// @brief Sets wrdone delay in buffer +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_delay WRDONE_DLY value (in cycles) to set +/// @param[in,out] io_data the target data buffer +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data ) { + FAPI_INF( "Set WRDONE_DLY to %d ", i_delay); + + io_data.template insertFromRight<TT::DSM0Q_WRDONE_DLY, TT::DSM0Q_WRDONE_DLY_LEN>(i_delay); +} +/// +/// @brief Change the wrdone delay value +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_delay WRDONE_DLY value (in cycles) to set +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode change_wrdone_delay( const fapi2::Target<T>& i_target, const uint64_t i_delay ) +{ fapi2::buffer<uint64_t> l_data; - FAPI_TRY( mss::getScom(i_target, TT::DSM0Q_REG, l_data) ); - l_data.template extractToRight<TT::DSM0Q_CFG_RDTAG_DLY, TT::DSM0Q_CFG_RDTAG_DLY_LEN>(o_delay); - FAPI_INF( "RDTAG_DLY %d for %s", uint64_t(o_delay), mss::c_str(i_target) ); + FAPI_DBG( "Change WRDONE_DLY to %d for %s", i_delay, mss::c_str(i_target) ); + + FAPI_TRY( read_dsm0q_register(i_target, l_data) ); + set_wrdone_delay(i_delay, l_data); + FAPI_TRY( write_dsm0q_register(i_target, l_data) ); + + FAPI_INF( "DSM0Q_REG 0x%016lx for %s", uint64_t(l_data), mss::c_str(i_target) ); fapi_try_exit: return fapi2::current_err; } /// +/// @brief Get the rdtag delay value +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_data the data buffer containing the DSM0Q register +/// @param[out] o_delay RDTAG_DLY value (in cycles) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void get_rdtag_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay ) +{ + i_data.template extractToRight<TT::DSM0Q_RDTAG_DLY, TT::DSM0Q_RDTAG_DLY_LEN>(o_delay); + + FAPI_INF( "RDTAG_DLY: %d ", uint64_t(o_delay) ); +} + +/// +/// @brief Sets rdtag delay in buffer +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_delay RDTAG_DLY value (in cycles) to set +/// @param[in,out] io_data the target data buffer +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data ) +{ + FAPI_DBG( "Set RDTAG_DLY to %d ", i_delay); + + io_data.template insertFromRight<TT::DSM0Q_RDTAG_DLY, TT::DSM0Q_RDTAG_DLY_LEN>(i_delay); +} + + +/// /// @brief Change the rdtag delay value /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the port @@ -296,25 +402,13 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode change_rdtag_delay( const fapi2::Target<T>& i_target, const uint64_t i_delay ) { - // RDTAG is only 6 bits in length, input could be bigger - // so we just let the user know of an invalid input. - // This is a programming error so we assert out. - // 6 bits - 0b0011 1111 (right aligned) - constexpr uint64_t MAX_DELAY = 0x3F; - - if( i_delay > MAX_DELAY ) - { - FAPI_ERR("Invalid delay received: %d, largest possible: %d", i_delay, MAX_DELAY); - fapi2::Assert(false); - } - fapi2::buffer<uint64_t> l_data; FAPI_DBG( "Change RDTAG_DLY to %d for %s", i_delay, mss::c_str(i_target) ); - FAPI_TRY( mss::getScom(i_target, TT::DSM0Q_REG, l_data) ); - l_data.insertFromRight<TT::DSM0Q_CFG_RDTAG_DLY, TT::DSM0Q_CFG_RDTAG_DLY_LEN>(i_delay); - FAPI_TRY( mss::putScom(i_target, TT::DSM0Q_REG, l_data) ); + FAPI_TRY( read_dsm0q_register(i_target, l_data) ); + set_rdtag_delay(i_delay, l_data); + FAPI_TRY( write_dsm0q_register(i_target, l_data) ); FAPI_INF( "DSM0Q_REG 0x%016lx for %s", uint64_t(l_data), mss::c_str(i_target) ); @@ -323,6 +417,100 @@ fapi_try_exit: } /// +/// @brief Read to FARB0Q register +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[out] o_time the buffer to read the register data into +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode read_farb0q_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_time ) +{ + FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, o_time) ); + + FAPI_INF( "FARB0Q is %d for %s", uint64_t(o_time), mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write to FARB0Q register +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_delay the buffer containing the data to be written +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode write_farb0q_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t> i_time ) +{ + FAPI_INF( "Change FARB0Q_REG to 0x%016lx for %s", uint64_t(i_time), mss::c_str(i_target) ); + + FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, i_time) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Get the RCD Protect Time value +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_data the data buffer containing the FARB0Q register +/// @param[out] o_time RCD_PROTECT_TIME value (in cycles) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void get_rcd_protect_time( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_time ) +{ + i_data.template extractToRight<TT::FARB0Q_RCD_PROTECTION_TIME, TT::FARB0Q_RCD_PROTECTION_TIME_LEN>(o_time); + + FAPI_INF( "RCD_PROTECT_TIME: %d", uint64_t(o_time) ); +} + + +/// +/// @brief Sets RCD Protect Time in buffer +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_delay RCD Protect Time value (in cycles) to set +/// @param[in,out] io_data the target data buffer +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer<uint64_t>& io_data ) +{ + FAPI_DBG( "Set RCD_PROTECT_TIME to %d ", i_time); + + io_data.template insertFromRight<TT::FARB0Q_RCD_PROTECTION_TIME, TT::FARB0Q_RCD_PROTECTION_TIME_LEN>(i_time); +} + +/// +/// @brief Change the RCD Protect Time value +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_time RCD Protect Time value (in cycles) to set +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode change_rcd_protect_time( const fapi2::Target<T>& i_target, const uint64_t i_time ) +{ + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY( read_farb0q_register(i_target, l_data) ); + + set_rcd_protect_time(i_time, l_data); + + FAPI_TRY( write_farb0q_register(i_target, l_data) ); + + FAPI_INF( "RCD_PROTECT_TIME %d for %s", uint64_t(i_time), mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Change the state of the port_fail_disable bit /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the port diff --git a/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml b/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml index d8f631350..030e43b02 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/system_attributes.xml @@ -56,9 +56,9 @@ <valueType>uint64</valueType> <enum> MNFG_NO_FLAG = 0x0000000000000000, + MNFG_THRESHOLDS = 0x0000000000000001, MNFG_DISABLE_DRAM_REPAIRS = 0x0000000000000080 <!-- - MNFG_THRESHOLDS = 0x0000000000000001, MNFG_AVP_ENABLE = 0x0000000000000002, MNFG_HDAT_AVP_ENABLE = 0x0000000000000004, MNFG_SRC_TERM = 0x0000000000000008, |
